clang: Store vendor GPU kinds in OffloadArch instead of re-listing GPUs (#213362)
OffloadArch was a flat enum that hand-duplicated every AMDGPU and NVPTX target, plus a few edge cases. This was yet another place that needed updating every time a new target is added, which should now be avoided. Replace with a tagged union-like scheme. Co-authored-by: Claude (Claude-Opus-4.8) <noreply@anthropic.com>
This commit is contained in:
Matt Arsenault
GitHub
parent
b94b699857
commit
3c3a18e239
14 changed files with 304 additions and 381 deletions
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@ -10,161 +10,121 @@
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#define LLVM_CLANG_BASIC_OFFLOADARCH_H
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#include "llvm/ADT/StringRef.h"
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#include <cstdint>
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#include <tuple>
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namespace llvm {
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class Triple;
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template <typename T> class SmallVectorImpl;
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namespace NVPTX {
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enum GPUKind : uint8_t;
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}
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namespace AMDGPU {
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enum GPUKind : uint8_t;
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}
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} // namespace llvm
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namespace clang {
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enum class OffloadArch {
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Unused,
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Unknown,
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// TODO: Deprecate and remove GPU architectures older than sm_52.
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SM_20,
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SM_21,
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SM_30,
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// This has a name conflict with sys/mac.h on AIX, rename it as a workaround.
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SM_32_,
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SM_35,
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SM_37,
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SM_50,
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SM_52,
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SM_53,
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SM_60,
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SM_61,
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SM_62,
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SM_70,
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SM_72,
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SM_75,
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SM_80,
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SM_86,
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SM_87,
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SM_88,
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SM_89,
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SM_90,
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SM_90a,
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SM_100,
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SM_100a,
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SM_100f,
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SM_101,
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SM_101a,
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SM_101f,
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SM_103,
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SM_103a,
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SM_103f,
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SM_110,
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SM_110a,
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SM_110f,
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SM_120,
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SM_120a,
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SM_120f,
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SM_121,
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SM_121a,
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SM_121f,
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GFX600,
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GFX601,
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GFX602,
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GFX700,
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GFX701,
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GFX702,
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GFX703,
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GFX704,
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GFX705,
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GFX801,
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GFX802,
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GFX803,
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GFX805,
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GFX810,
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GFX9_GENERIC,
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GFX900,
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GFX902,
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GFX904,
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GFX906,
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GFX908,
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GFX909,
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GFX90a,
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GFX90c,
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GFX9_4_GENERIC,
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GFX942,
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GFX950,
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GFX10_1_GENERIC,
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GFX1010,
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GFX1011,
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GFX1012,
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GFX1013,
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GFX10_3_GENERIC,
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GFX1030,
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GFX1031,
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GFX1032,
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GFX1033,
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GFX1034,
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GFX1035,
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GFX1036,
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GFX11_GENERIC,
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GFX1100,
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GFX1101,
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GFX1102,
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GFX1103,
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GFX1150,
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GFX1151,
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GFX1152,
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GFX1153,
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GFX1154,
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GFX11_7_GENERIC,
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GFX1170,
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GFX1171,
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GFX1172,
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GFX12_GENERIC,
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GFX1200,
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GFX1201,
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GFX12_5_GENERIC,
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GFX1250,
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GFX1251,
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GFX13_GENERIC,
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GFX1310,
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AMDGCNSPIRV,
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Generic, // A processor model named 'generic' if the target backend defines a
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// public one.
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// Intel CPUs
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GRANITERAPIDS,
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// Intel GPUs
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BMG_G21,
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LAST = BMG_G21,
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/// A processor an offloading action can target. This is a tagged handle pairing
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/// a TargetArch with the matching TargetParser GPU kind; it does not enumerate
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/// individual GPUs, so new targets are added in the TargetParser data alone.
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class OffloadArch {
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public:
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enum class TargetArch : uint8_t {
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Unused, // Default-constructed; no architecture bound.
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Unknown, // A name that matched no known architecture.
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NVPTX, // Kind is an llvm::NVPTX::GPUKind.
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AMDGPU, // Kind is an llvm::AMDGPU::GPUKind.
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SPIRV, // The 'amdgcnspirv' pseudo target.
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IntelCPU, // Kind is an IntelArch.
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IntelGPU, // Kind is an IntelArch.
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Generic, // The 'generic' processor model.
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};
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CudaDefault = OffloadArch::SM_52,
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HIPDefault = OffloadArch::GFX906,
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// Intel architectures, which have no TargetParser list yet.
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enum class IntelArch : uint32_t {
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GRANITERAPIDS,
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BMG_G21,
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};
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private:
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// Interpreted according to V; unused for the tagless TargetArch values.
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uint32_t Kind = 0;
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TargetArch V = TargetArch::Unused;
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constexpr OffloadArch(TargetArch V, uint32_t Kind) : Kind(Kind), V(V) {}
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public:
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constexpr OffloadArch() = default;
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static OffloadArch getNVPTX(llvm::NVPTX::GPUKind K) {
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return {TargetArch::NVPTX, static_cast<uint32_t>(K)};
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}
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static OffloadArch getAMDGPU(llvm::AMDGPU::GPUKind K) {
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return {TargetArch::AMDGPU, static_cast<uint32_t>(K)};
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}
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static constexpr OffloadArch getIntel(TargetArch V, IntelArch A) {
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return {V, static_cast<uint32_t>(A)};
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}
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static constexpr OffloadArch getUnused() { return {TargetArch::Unused, 0}; }
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static constexpr OffloadArch getUnknown() { return {TargetArch::Unknown, 0}; }
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static constexpr OffloadArch getSPIRV() { return {TargetArch::SPIRV, 0}; }
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static constexpr OffloadArch getGeneric() { return {TargetArch::Generic, 0}; }
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/// Default architectures used when the user does not specify one.
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static OffloadArch CudaDefault();
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static OffloadArch HIPDefault();
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TargetArch targetArch() const { return V; }
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bool isNVPTX() const { return V == TargetArch::NVPTX; }
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bool isAMDGPU() const { return V == TargetArch::AMDGPU; }
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bool isSPIRV() const { return V == TargetArch::SPIRV; }
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bool isIntelCPU() const { return V == TargetArch::IntelCPU; }
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bool isIntelGPU() const { return V == TargetArch::IntelGPU; }
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bool isIntel() const { return isIntelCPU() || isIntelGPU(); }
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bool isGeneric() const { return V == TargetArch::Generic; }
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bool isUnused() const { return V == TargetArch::Unused; }
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bool isUnknown() const { return V == TargetArch::Unknown; }
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// Only valid when isNVPTX() / isAMDGPU() respectively.
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llvm::NVPTX::GPUKind nvptxKind() const {
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return static_cast<llvm::NVPTX::GPUKind>(Kind);
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}
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llvm::AMDGPU::GPUKind amdgpuKind() const {
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return static_cast<llvm::AMDGPU::GPUKind>(Kind);
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}
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bool operator==(const OffloadArch &Other) const {
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return V == Other.V && Kind == Other.Kind;
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}
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bool operator!=(const OffloadArch &Other) const { return !(*this == Other); }
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bool operator<(const OffloadArch &Other) const {
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return std::tie(V, Kind) < std::tie(Other.V, Other.Kind);
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}
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};
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static inline bool IsNVIDIAOffloadArch(OffloadArch A) {
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return A >= OffloadArch::SM_20 && A < OffloadArch::GFX600;
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}
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static inline bool IsAMDOffloadArch(OffloadArch A) {
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// Generic processor model is for testing only.
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return A >= OffloadArch::GFX600 && A < OffloadArch::Generic;
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}
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static inline bool IsIntelCPUOffloadArch(OffloadArch Arch) {
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return Arch >= OffloadArch::GRANITERAPIDS && Arch < OffloadArch::BMG_G21;
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}
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static inline bool IsIntelGPUOffloadArch(OffloadArch Arch) {
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return Arch >= OffloadArch::BMG_G21 && Arch <= OffloadArch::LAST;
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}
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static inline bool IsIntelOffloadArch(OffloadArch Arch) {
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return IsIntelCPUOffloadArch(Arch) || IsIntelGPUOffloadArch(Arch);
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inline bool IsNVIDIAOffloadArch(OffloadArch A) { return A.isNVPTX(); }
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inline bool IsAMDOffloadArch(OffloadArch A) {
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// amdgcnspirv is compiled through the AMDGPU toolchain.
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return A.isAMDGPU() || A.isSPIRV();
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}
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inline bool IsIntelCPUOffloadArch(OffloadArch A) { return A.isIntelCPU(); }
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inline bool IsIntelGPUOffloadArch(OffloadArch A) { return A.isIntelGPU(); }
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inline bool IsIntelOffloadArch(OffloadArch A) { return A.isIntel(); }
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const char *OffloadArchToString(OffloadArch A);
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const char *OffloadArchToVirtualArchString(OffloadArch A);
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// Convert a string to an OffloadArch enum value. Returns
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// OffloadArch::Unknown if the string is not recognized.
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// Convert a string to an OffloadArch. Returns an Unknown OffloadArch if the
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// string is not recognized.
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OffloadArch StringToOffloadArch(llvm::StringRef S);
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/// Append the canonical names of all NVIDIA and AMDGPU GPUs.
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void fillValidOffloadArchList(llvm::SmallVectorImpl<llvm::StringRef> &Values);
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llvm::Triple OffloadArchToTriple(const llvm::Triple &DefaultToolchainTriple,
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OffloadArch ID);
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@ -173,19 +133,19 @@ llvm::Triple OffloadArchToTriple(const llvm::Triple &DefaultToolchainTriple,
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struct BoundArch {
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llvm::StringRef ArchName;
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/// The parsed offload architecture enum.
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/// Will be OffloadArch::Unknown if ArchName not recognized.
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OffloadArch Arch = OffloadArch::Unused;
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/// The parsed offload architecture.
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/// Will be an Unknown OffloadArch if ArchName is not recognized.
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OffloadArch Arch = OffloadArch::getUnused();
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BoundArch() = default;
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explicit BoundArch(llvm::StringRef Name)
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: ArchName(Name),
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Arch(Name.empty() ? OffloadArch::Unknown : StringToOffloadArch(Name)) {}
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: ArchName(Name), Arch(Name.empty() ? OffloadArch::getUnknown()
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: StringToOffloadArch(Name)) {}
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BoundArch(llvm::StringRef Name, OffloadArch A) : ArchName(Name), Arch(A) {}
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bool empty() const { return ArchName.empty(); }
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explicit operator bool() const { return Arch != OffloadArch::Unused; }
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explicit operator bool() const { return !Arch.isUnused(); }
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bool operator==(const BoundArch &Other) const {
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return Arch == Other.Arch && ArchName == Other.ArchName;
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@ -11,6 +11,7 @@
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#include "clang/Basic/Cuda.h"
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#include "clang/Driver/Driver.h"
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#include "llvm/TargetParser/NVPTXTargetParser.h"
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#include <bitset>
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namespace clang {
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@ -28,9 +29,9 @@ private:
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std::string IncludePath;
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llvm::StringMap<std::string> LibDeviceMap;
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// CUDA architectures for which we have raised an error in
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// CheckCudaVersionSupportsArch.
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mutable std::bitset<(int)OffloadArch::LAST> ArchsWithBadVersion;
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// NVIDIA architectures (indexed by GPUKind) for which we have raised an error
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// in CheckCudaVersionSupportsArch.
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mutable std::bitset<llvm::NVPTX::GK_LAST + 1> ArchsWithBadVersion;
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public:
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CudaInstallationDetector(const Driver &D, const llvm::Triple &HostTriple,
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@ -4,6 +4,7 @@
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/VersionTuple.h"
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#include "llvm/TargetParser/NVPTXTargetParser.h"
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#include <cassert>
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namespace clang {
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@ -78,16 +79,16 @@ CudaVersion ToCudaVersion(llvm::VersionTuple Version) {
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}
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CudaVersion MinVersionForOffloadArch(OffloadArch A) {
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if (A == OffloadArch::Unknown)
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if (A.isUnknown())
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return CudaVersion::UNKNOWN;
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// AMD GPUs do not depend on CUDA versions.
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if (IsAMDOffloadArch(A))
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return CudaVersion::CUDA_70;
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switch (A) {
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switch (A.nvptxKind()) {
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#define NVPTX_GPU(NAME, KIND, VIRTUAL, SM_ID, MIN_VER, MAX_VER, SUFFIX) \
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case OffloadArch::KIND: \
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case llvm::NVPTX::GK_##KIND: \
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return CudaVersion::MIN_VER;
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#include "llvm/TargetParser/NVPTXTargetParser.def"
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default:
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@ -100,11 +101,12 @@ CudaVersion MaxVersionForOffloadArch(OffloadArch A) {
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if (IsAMDOffloadArch(A))
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return CudaVersion::NEW;
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switch (A) {
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case OffloadArch::Unknown:
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if (!A.isNVPTX())
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return CudaVersion::UNKNOWN;
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switch (A.nvptxKind()) {
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#define NVPTX_GPU(NAME, KIND, VIRTUAL, SM_ID, MIN_VER, MAX_VER, SUFFIX) \
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case OffloadArch::KIND: \
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case llvm::NVPTX::GK_##KIND: \
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return CudaVersion::MAX_VER;
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#include "llvm/TargetParser/NVPTXTargetParser.def"
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default:
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@ -127,33 +129,15 @@ bool CudaFeatureEnabled(CudaVersion Version, CudaFeature Feature) {
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}
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unsigned CudaArchToID(OffloadArch Arch) {
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switch (Arch) {
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#define NVPTX_GPU(NAME, KIND, VIRTUAL, SM_ID, MIN_VER, MAX_VER, SUFFIX) \
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case OffloadArch::KIND: \
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return SM_ID;
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#include "llvm/TargetParser/NVPTXTargetParser.def"
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default:
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break;
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}
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llvm_unreachable("invalid NVIDIA GPU architecture");
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}
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static llvm::NVPTX::GPUKind OffloadArchToNVPTXKind(OffloadArch Arch) {
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switch (Arch) {
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#define NVPTX_GPU(NAME, KIND, VIRTUAL, SM_ID, MIN_VER, MAX_VER, SUFFIX) \
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case OffloadArch::KIND: \
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return llvm::NVPTX::GK_##KIND;
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#include "llvm/TargetParser/NVPTXTargetParser.def"
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default:
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return llvm::NVPTX::GK_NONE;
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}
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assert(Arch.isNVPTX() && "invalid NVIDIA GPU architecture");
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return llvm::NVPTX::getSmVersion(Arch.nvptxKind());
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}
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bool IsNVIDIAAcceleratedOffloadArch(OffloadArch Arch) {
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return llvm::NVPTX::isAcceleratedArch(OffloadArchToNVPTXKind(Arch));
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return Arch.isNVPTX() && llvm::NVPTX::isAcceleratedArch(Arch.nvptxKind());
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}
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bool IsNVIDIAFamilySpecificOffloadArch(OffloadArch Arch) {
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return llvm::NVPTX::isFamilySpecificArch(OffloadArchToNVPTXKind(Arch));
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return Arch.isNVPTX() && llvm::NVPTX::isFamilySpecificArch(Arch.nvptxKind());
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}
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} // namespace clang
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@ -7,164 +7,101 @@
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//===----------------------------------------------------------------------===//
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#include "clang/Basic/OffloadArch.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/StringRef.h"
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#include "llvm/TargetParser/AMDGPUTargetParser.h"
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#include "llvm/TargetParser/NVPTXTargetParser.h"
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#include "llvm/TargetParser/Triple.h"
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namespace clang {
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namespace {
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struct OffloadArchToStringMap {
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OffloadArch Arch;
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const char *ArchName;
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const char *VirtualArchName;
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};
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} // namespace
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OffloadArch OffloadArch::CudaDefault() {
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return getNVPTX(llvm::NVPTX::parseArch("sm_52"));
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}
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#define SM(sm) {OffloadArch::SM_##sm, "sm_" #sm, "compute_" #sm}
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#define GFX(gpu) {OffloadArch::GFX##gpu, "gfx" #gpu, "compute_amdgcn"}
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static const OffloadArchToStringMap ArchNames[] = {
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// clang-format off
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{OffloadArch::Unused, "", ""},
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SM(20), {OffloadArch::SM_21, "sm_21", "compute_20"}, // Fermi
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SM(30), {OffloadArch::SM_32_, "sm_32", "compute_32"}, SM(35), SM(37), // Kepler
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SM(50), SM(52), SM(53), // Maxwell
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SM(60), SM(61), SM(62), // Pascal
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SM(70), SM(72), // Volta
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SM(75), // Turing
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SM(80), SM(86), // Ampere
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SM(87), // Jetson/Drive AGX Orin
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SM(88), // Ampere
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SM(89), // Ada Lovelace
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SM(90), // Hopper
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SM(90a), // Hopper
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SM(100), // Blackwell
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SM(100a), // Blackwell
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SM(100f), // Blackwell
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SM(101), // Blackwell
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SM(101a), // Blackwell
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SM(101f), // Blackwell
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SM(103), // Blackwell
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SM(103a), // Blackwell
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SM(103f), // Blackwell
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SM(110), // Blackwell
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SM(110a), // Blackwell
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SM(110f), // Blackwell
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SM(120), // Blackwell
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SM(120a), // Blackwell
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SM(120f), // Blackwell
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SM(121), // Blackwell
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SM(121a), // Blackwell
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SM(121f), // Blackwell
|
||||
GFX(600), // gfx600
|
||||
GFX(601), // gfx601
|
||||
GFX(602), // gfx602
|
||||
GFX(700), // gfx700
|
||||
GFX(701), // gfx701
|
||||
GFX(702), // gfx702
|
||||
GFX(703), // gfx703
|
||||
GFX(704), // gfx704
|
||||
GFX(705), // gfx705
|
||||
GFX(801), // gfx801
|
||||
GFX(802), // gfx802
|
||||
GFX(803), // gfx803
|
||||
GFX(805), // gfx805
|
||||
GFX(810), // gfx810
|
||||
{OffloadArch::GFX9_GENERIC, "gfx9-generic", "compute_amdgcn"},
|
||||
GFX(900), // gfx900
|
||||
GFX(902), // gfx902
|
||||
GFX(904), // gfx903
|
||||
GFX(906), // gfx906
|
||||
GFX(908), // gfx908
|
||||
GFX(909), // gfx909
|
||||
GFX(90a), // gfx90a
|
||||
GFX(90c), // gfx90c
|
||||
{OffloadArch::GFX9_4_GENERIC, "gfx9-4-generic", "compute_amdgcn"},
|
||||
GFX(942), // gfx942
|
||||
GFX(950), // gfx950
|
||||
{OffloadArch::GFX10_1_GENERIC, "gfx10-1-generic", "compute_amdgcn"},
|
||||
GFX(1010), // gfx1010
|
||||
GFX(1011), // gfx1011
|
||||
GFX(1012), // gfx1012
|
||||
GFX(1013), // gfx1013
|
||||
{OffloadArch::GFX10_3_GENERIC, "gfx10-3-generic", "compute_amdgcn"},
|
||||
GFX(1030), // gfx1030
|
||||
GFX(1031), // gfx1031
|
||||
GFX(1032), // gfx1032
|
||||
GFX(1033), // gfx1033
|
||||
GFX(1034), // gfx1034
|
||||
GFX(1035), // gfx1035
|
||||
GFX(1036), // gfx1036
|
||||
{OffloadArch::GFX11_GENERIC, "gfx11-generic", "compute_amdgcn"},
|
||||
GFX(1100), // gfx1100
|
||||
GFX(1101), // gfx1101
|
||||
GFX(1102), // gfx1102
|
||||
GFX(1103), // gfx1103
|
||||
GFX(1150), // gfx1150
|
||||
GFX(1151), // gfx1151
|
||||
GFX(1152), // gfx1152
|
||||
GFX(1153), // gfx1153
|
||||
GFX(1154), // gfx1154
|
||||
{OffloadArch::GFX11_7_GENERIC, "gfx11-7-generic", "compute_amdgcn"},
|
||||
GFX(1170), // gfx1170
|
||||
GFX(1171), // gfx1171
|
||||
GFX(1172), // gfx1172
|
||||
{OffloadArch::GFX12_GENERIC, "gfx12-generic", "compute_amdgcn"},
|
||||
GFX(1200), // gfx1200
|
||||
GFX(1201), // gfx1201
|
||||
{OffloadArch::GFX12_5_GENERIC, "gfx12-5-generic", "compute_amdgcn"},
|
||||
GFX(1250), // gfx1250
|
||||
GFX(1251), // gfx1251
|
||||
{OffloadArch::GFX13_GENERIC, "gfx13-generic", "compute_amdgcn"},
|
||||
GFX(1310), // gfx1310
|
||||
{OffloadArch::AMDGCNSPIRV, "amdgcnspirv", "compute_amdgcn"},
|
||||
// Intel CPUs
|
||||
{OffloadArch::GRANITERAPIDS, "graniterapids", ""},
|
||||
// Intel GPUS
|
||||
{OffloadArch::BMG_G21, "bmg_g21", ""},
|
||||
{OffloadArch::Generic, "generic", ""},
|
||||
// clang-format on
|
||||
};
|
||||
#undef SM
|
||||
#undef GFX
|
||||
OffloadArch OffloadArch::HIPDefault() {
|
||||
return getAMDGPU(llvm::AMDGPU::parseArchAMDGCN("gfx906"));
|
||||
}
|
||||
|
||||
const char *OffloadArchToString(OffloadArch A) {
|
||||
auto Result =
|
||||
llvm::find_if(ArchNames, [A](const OffloadArchToStringMap &Map) {
|
||||
return A == Map.Arch;
|
||||
});
|
||||
if (Result == std::end(ArchNames))
|
||||
switch (A.targetArch()) {
|
||||
case OffloadArch::TargetArch::Unused:
|
||||
return "";
|
||||
case OffloadArch::TargetArch::Unknown:
|
||||
return "unknown";
|
||||
case OffloadArch::TargetArch::NVPTX:
|
||||
return llvm::NVPTX::getArchName(A.nvptxKind()).data();
|
||||
case OffloadArch::TargetArch::AMDGPU:
|
||||
return llvm::AMDGPU::getArchNameAMDGCN(A.amdgpuKind()).data();
|
||||
case OffloadArch::TargetArch::SPIRV:
|
||||
return "amdgcnspirv";
|
||||
case OffloadArch::TargetArch::IntelCPU:
|
||||
return "graniterapids";
|
||||
case OffloadArch::TargetArch::IntelGPU:
|
||||
return "bmg_g21";
|
||||
case OffloadArch::TargetArch::Generic:
|
||||
return "generic";
|
||||
}
|
||||
return "unknown";
|
||||
return Result->ArchName;
|
||||
}
|
||||
|
||||
const char *OffloadArchToVirtualArchString(OffloadArch A) {
|
||||
auto Result =
|
||||
llvm::find_if(ArchNames, [A](const OffloadArchToStringMap &Map) {
|
||||
return A == Map.Arch;
|
||||
});
|
||||
if (Result == std::end(ArchNames))
|
||||
switch (A.targetArch()) {
|
||||
case OffloadArch::TargetArch::NVPTX:
|
||||
return llvm::NVPTX::getVirtualArch(A.nvptxKind()).data();
|
||||
case OffloadArch::TargetArch::AMDGPU:
|
||||
case OffloadArch::TargetArch::SPIRV:
|
||||
return "compute_amdgcn";
|
||||
case OffloadArch::TargetArch::Unknown:
|
||||
return "unknown";
|
||||
case OffloadArch::TargetArch::Unused:
|
||||
case OffloadArch::TargetArch::IntelCPU:
|
||||
case OffloadArch::TargetArch::IntelGPU:
|
||||
case OffloadArch::TargetArch::Generic:
|
||||
return "";
|
||||
}
|
||||
return "unknown";
|
||||
return Result->VirtualArchName;
|
||||
}
|
||||
|
||||
OffloadArch StringToOffloadArch(llvm::StringRef S) {
|
||||
auto Result =
|
||||
llvm::find_if(ArchNames, [S](const OffloadArchToStringMap &Map) {
|
||||
return S == Map.ArchName;
|
||||
});
|
||||
if (Result == std::end(ArchNames))
|
||||
return OffloadArch::Unknown;
|
||||
return Result->Arch;
|
||||
// The empty string denotes the "unused" architecture.
|
||||
if (S.empty())
|
||||
return OffloadArch::getUnused();
|
||||
|
||||
// Non-GPU-table pseudo/sentinel architectures.
|
||||
if (S == "amdgcnspirv")
|
||||
return OffloadArch::getSPIRV();
|
||||
if (S == "generic")
|
||||
return OffloadArch::getGeneric();
|
||||
if (S == "graniterapids")
|
||||
return OffloadArch::getIntel(OffloadArch::TargetArch::IntelCPU,
|
||||
OffloadArch::IntelArch::GRANITERAPIDS);
|
||||
if (S == "bmg_g21")
|
||||
return OffloadArch::getIntel(OffloadArch::TargetArch::IntelGPU,
|
||||
OffloadArch::IntelArch::BMG_G21);
|
||||
|
||||
// Otherwise defer to the vendor TargetParser GPU lists.
|
||||
if (llvm::NVPTX::GPUKind NV = llvm::NVPTX::parseArch(S))
|
||||
return OffloadArch::getNVPTX(NV);
|
||||
if (llvm::AMDGPU::GPUKind AK = llvm::AMDGPU::parseArchAMDGCN(S))
|
||||
return OffloadArch::getAMDGPU(AK);
|
||||
return OffloadArch::getUnknown();
|
||||
}
|
||||
|
||||
void fillValidOffloadArchList(llvm::SmallVectorImpl<llvm::StringRef> &Values) {
|
||||
#define NVPTX_GPU(NAME, KIND, VIRTUAL, SM_ID, MIN_VER, MAX_VER, SUFFIX) \
|
||||
Values.push_back(NAME);
|
||||
#include "llvm/TargetParser/NVPTXTargetParser.def"
|
||||
llvm::AMDGPU::fillValidArchListAMDGCN(Values, llvm::Triple::NoSubArch);
|
||||
}
|
||||
|
||||
llvm::Triple OffloadArchToTriple(const llvm::Triple &DefaultToolchainTriple,
|
||||
OffloadArch ID) {
|
||||
if (ID == OffloadArch::AMDGCNSPIRV)
|
||||
if (ID.isSPIRV())
|
||||
return llvm::Triple(llvm::Triple::spirv64, llvm::Triple::NoSubArch,
|
||||
llvm::Triple::AMD, llvm::Triple::AMDHSA);
|
||||
|
||||
if (IsNVIDIAOffloadArch(ID)) {
|
||||
if (ID.isNVPTX()) {
|
||||
llvm::Triple::ArchType Arch = DefaultToolchainTriple.isArch64Bit()
|
||||
? llvm::Triple::nvptx64
|
||||
: llvm::Triple::nvptx;
|
||||
|
|
@ -172,7 +109,7 @@ llvm::Triple OffloadArchToTriple(const llvm::Triple &DefaultToolchainTriple,
|
|||
llvm::Triple::CUDA);
|
||||
}
|
||||
|
||||
if (IsAMDOffloadArch(ID))
|
||||
if (ID.isAMDGPU())
|
||||
return llvm::Triple("amdgcn-amd-amdhsa");
|
||||
|
||||
return {};
|
||||
|
|
|
|||
|
|
@ -64,7 +64,7 @@ NVPTXTargetInfo::NVPTXTargetInfo(const llvm::Triple &Triple,
|
|||
// Define available target features
|
||||
// These must be defined in sorted order!
|
||||
NoAsmVariants = true;
|
||||
GPU = OffloadArch::Unused;
|
||||
GPU = OffloadArch::getUnused();
|
||||
|
||||
// PTX supports f16 as a fundamental type.
|
||||
HasFastHalfType = true;
|
||||
|
|
|
|||
|
|
@ -72,7 +72,7 @@ public:
|
|||
initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
|
||||
StringRef CPU,
|
||||
const std::vector<std::string> &FeaturesVec) const override {
|
||||
if (GPU != OffloadArch::Unused)
|
||||
if (!GPU.isUnused())
|
||||
Features[OffloadArchToString(GPU)] = true;
|
||||
// Only add PTX feature if explicitly requested. Otherwise, let the backend
|
||||
// use the minimum required PTX version for the target SM.
|
||||
|
|
@ -131,18 +131,16 @@ public:
|
|||
}
|
||||
|
||||
bool isValidCPUName(StringRef Name) const override {
|
||||
return StringToOffloadArch(Name) != OffloadArch::Unknown;
|
||||
return !StringToOffloadArch(Name).isUnknown();
|
||||
}
|
||||
|
||||
void fillValidCPUList(SmallVectorImpl<StringRef> &Values) const override {
|
||||
for (int i = static_cast<int>(OffloadArch::SM_20);
|
||||
i < static_cast<int>(OffloadArch::Generic); ++i)
|
||||
Values.emplace_back(OffloadArchToString(static_cast<OffloadArch>(i)));
|
||||
fillValidOffloadArchList(Values);
|
||||
}
|
||||
|
||||
bool setCPU(StringRef Name) override {
|
||||
GPU = StringToOffloadArch(Name);
|
||||
return GPU != OffloadArch::Unknown;
|
||||
return !GPU.isUnknown();
|
||||
}
|
||||
|
||||
void setSupportedOpenCLOpts() override {
|
||||
|
|
|
|||
|
|
@ -961,7 +961,7 @@ static TripleSet inferOffloadToolchains(Compilation &C,
|
|||
TripleSet Triples;
|
||||
for (llvm::StringRef Arch : Archs) {
|
||||
OffloadArch ID = StringToOffloadArch(Arch);
|
||||
if (ID == OffloadArch::Unknown)
|
||||
if (ID.isUnknown())
|
||||
ID = StringToOffloadArch(
|
||||
getProcessorFromTargetID(llvm::Triple("amdgcn-amd-amdhsa"), Arch));
|
||||
|
||||
|
|
@ -975,13 +975,12 @@ static TripleSet inferOffloadToolchains(Compilation &C,
|
|||
<< "CUDA" << Arch;
|
||||
return {};
|
||||
}
|
||||
if (Kind == Action::OFK_OpenMP &&
|
||||
(ID == OffloadArch::Unknown || ID == OffloadArch::Unused)) {
|
||||
if (Kind == Action::OFK_OpenMP && (ID.isUnknown() || ID.isUnused())) {
|
||||
C.getDriver().Diag(clang::diag::err_drv_failed_to_deduce_target_from_arch)
|
||||
<< Arch;
|
||||
return {};
|
||||
}
|
||||
if (ID == OffloadArch::Unknown || ID == OffloadArch::Unused) {
|
||||
if (ID.isUnknown() || ID.isUnused()) {
|
||||
C.getDriver().Diag(clang::diag::err_drv_offload_bad_gpu_arch)
|
||||
<< "offload" << Arch;
|
||||
return {};
|
||||
|
|
@ -3466,7 +3465,7 @@ class OffloadingActionBuilder final {
|
|||
bool Relocatable = false;
|
||||
|
||||
/// Default GPU architecture if there's no one specified.
|
||||
OffloadArch DefaultOffloadArch = OffloadArch::Unknown;
|
||||
OffloadArch DefaultOffloadArch = OffloadArch::getUnknown();
|
||||
|
||||
/// Compilation unit ID specified by option '-fuse-cuid=' or'-cuid='.
|
||||
const CUIDOptions &CUIDOpts;
|
||||
|
|
@ -3644,7 +3643,7 @@ class OffloadingActionBuilder final {
|
|||
CudaActionBuilder(Compilation &C, DerivedArgList &Args,
|
||||
const InputList &Inputs)
|
||||
: CudaActionBuilderBase(C, Args, Inputs, Action::OFK_Cuda) {
|
||||
DefaultOffloadArch = OffloadArch::CudaDefault;
|
||||
DefaultOffloadArch = OffloadArch::CudaDefault();
|
||||
}
|
||||
|
||||
ActionBuilderReturnCode
|
||||
|
|
@ -3769,7 +3768,7 @@ class OffloadingActionBuilder final {
|
|||
const InputList &Inputs)
|
||||
: CudaActionBuilderBase(C, Args, Inputs, Action::OFK_HIP) {
|
||||
|
||||
DefaultOffloadArch = OffloadArch::HIPDefault;
|
||||
DefaultOffloadArch = OffloadArch::HIPDefault();
|
||||
|
||||
if (Args.hasArg(options::OPT_fhip_emit_relocatable,
|
||||
options::OPT_fno_hip_emit_relocatable)) {
|
||||
|
|
@ -4882,13 +4881,12 @@ static StringRef getCanonicalArchString(Compilation &C,
|
|||
// expecting the triple to be only NVPTX / AMDGPU.
|
||||
OffloadArch Arch =
|
||||
StringToOffloadArch(getProcessorFromTargetID(Triple, ArchStr));
|
||||
if (Triple.isNVPTX() &&
|
||||
(Arch == OffloadArch::Unknown || !IsNVIDIAOffloadArch(Arch))) {
|
||||
if (Triple.isNVPTX() && (Arch.isUnknown() || !IsNVIDIAOffloadArch(Arch))) {
|
||||
C.getDriver().Diag(clang::diag::err_drv_offload_bad_gpu_arch)
|
||||
<< "CUDA" << ArchStr;
|
||||
return StringRef();
|
||||
} else if (Triple.isAMDGPU() &&
|
||||
(Arch == OffloadArch::Unknown || !IsAMDOffloadArch(Arch))) {
|
||||
(Arch.isUnknown() || !IsAMDOffloadArch(Arch))) {
|
||||
C.getDriver().Diag(clang::diag::err_drv_offload_bad_gpu_arch)
|
||||
<< "HIP" << ArchStr;
|
||||
return StringRef();
|
||||
|
|
@ -4992,12 +4990,12 @@ Driver::getOffloadArchs(Compilation &C, const llvm::opt::DerivedArgList &Args,
|
|||
if (Archs.empty()) {
|
||||
if (Kind == Action::OFK_Cuda) {
|
||||
Archs.insert(OffloadArchToString(TC.getTriple().isSPIRV()
|
||||
? OffloadArch::Unused
|
||||
: OffloadArch::CudaDefault));
|
||||
? OffloadArch::getUnused()
|
||||
: OffloadArch::CudaDefault()));
|
||||
} else if (Kind == Action::OFK_HIP) {
|
||||
Archs.insert(OffloadArchToString(TC.getTriple().isSPIRV()
|
||||
? OffloadArch::Generic
|
||||
: OffloadArch::HIPDefault));
|
||||
? OffloadArch::getGeneric()
|
||||
: OffloadArch::HIPDefault()));
|
||||
} else if (Kind == Action::OFK_SYCL) {
|
||||
Archs.insert(StringRef());
|
||||
} else if (Kind == Action::OFK_OpenMP) {
|
||||
|
|
|
|||
|
|
@ -83,8 +83,7 @@ OffloadTargetInfo::OffloadTargetInfo(const StringRef Target,
|
|||
StringRef TargetIdWithFeature =
|
||||
Components.size() == 6 ? Components.back() : "";
|
||||
StringRef TargetId = TargetIdWithFeature.split(':').first;
|
||||
if (!TargetId.empty() &&
|
||||
clang::StringToOffloadArch(TargetId) != clang::OffloadArch::Unknown)
|
||||
if (!TargetId.empty() && !clang::StringToOffloadArch(TargetId).isUnknown())
|
||||
this->TargetID = TargetIdWithFeature;
|
||||
else
|
||||
this->TargetID = "";
|
||||
|
|
|
|||
|
|
@ -235,14 +235,12 @@ CudaInstallationDetector::CudaInstallationDetector(
|
|||
// CUDA-9+ uses single libdevice file for all GPU variants.
|
||||
std::string FilePath = LibDevicePath + "/libdevice.10.bc";
|
||||
if (FS.exists(FilePath)) {
|
||||
for (int Arch = (int)OffloadArch::SM_30, E = (int)OffloadArch::LAST;
|
||||
Arch < E; ++Arch) {
|
||||
OffloadArch OA = static_cast<OffloadArch>(Arch);
|
||||
if (!IsNVIDIAOffloadArch(OA))
|
||||
continue;
|
||||
std::string OffloadArchName(OffloadArchToString(OA));
|
||||
LibDeviceMap[OffloadArchName] = FilePath;
|
||||
}
|
||||
// CUDA-9+ uses a single libdevice file for every NVIDIA GPU variant
|
||||
// (sm_30 and newer).
|
||||
#define NVPTX_GPU(NAME, KIND, VIRTUAL, SM_ID, MIN_VER, MAX_VER, SUFFIX) \
|
||||
if ((SM_ID) >= 300) \
|
||||
LibDeviceMap[NAME] = FilePath;
|
||||
#include "llvm/TargetParser/NVPTXTargetParser.def"
|
||||
}
|
||||
} else {
|
||||
std::error_code EC;
|
||||
|
|
@ -326,14 +324,15 @@ void CudaInstallationDetector::AddCudaIncludeArgs(
|
|||
|
||||
void CudaInstallationDetector::CheckCudaVersionSupportsArch(
|
||||
OffloadArch Arch) const {
|
||||
if (Arch == OffloadArch::Unknown || Version == CudaVersion::UNKNOWN ||
|
||||
ArchsWithBadVersion[(int)Arch])
|
||||
// Only NVIDIA architectures depend on the CUDA toolkit version.
|
||||
if (!Arch.isNVPTX() || Version == CudaVersion::UNKNOWN ||
|
||||
ArchsWithBadVersion[Arch.nvptxKind()])
|
||||
return;
|
||||
|
||||
auto MinVersion = MinVersionForOffloadArch(Arch);
|
||||
auto MaxVersion = MaxVersionForOffloadArch(Arch);
|
||||
if (Version < MinVersion || Version > MaxVersion) {
|
||||
ArchsWithBadVersion[(int)Arch] = true;
|
||||
ArchsWithBadVersion[Arch.nvptxKind()] = true;
|
||||
D.Diag(diag::err_drv_cuda_version_unsupported)
|
||||
<< OffloadArchToString(Arch) << CudaVersionToString(MinVersion)
|
||||
<< CudaVersionToString(MaxVersion) << InstallPath
|
||||
|
|
@ -414,7 +413,7 @@ void NVPTX::Assembler::ConstructJob(Compilation &C, const JobAction &JA,
|
|||
}
|
||||
|
||||
// Obtain architecture from the action.
|
||||
assert(GPUArch.Arch != OffloadArch::Unknown &&
|
||||
assert(!GPUArch.Arch.isUnknown() &&
|
||||
"Device action expected to have an architecture.");
|
||||
|
||||
// Check that our installation's ptxas supports gpu_arch.
|
||||
|
|
@ -778,7 +777,7 @@ NVPTXToolChain::TranslateArgs(const llvm::opt::DerivedArgList &Args,
|
|||
|
||||
if (!DAL->hasArg(options::OPT_march_EQ) && OffloadKind != Action::OFK_None) {
|
||||
DAL->AddJoinedArg(nullptr, Opts.getOption(options::OPT_march_EQ),
|
||||
OffloadArchToString(OffloadArch::CudaDefault));
|
||||
OffloadArchToString(OffloadArch::CudaDefault()));
|
||||
} else if (DAL->getLastArgValue(options::OPT_march_EQ) == "generic" &&
|
||||
OffloadKind == Action::OFK_None) {
|
||||
DAL->eraseArg(options::OPT_march_EQ);
|
||||
|
|
|
|||
|
|
@ -72,6 +72,7 @@
|
|||
#include "llvm/Support/ErrorHandling.h"
|
||||
#include "llvm/Support/MathExtras.h"
|
||||
#include "llvm/Support/raw_ostream.h"
|
||||
#include "llvm/TargetParser/NVPTXTargetParser.h"
|
||||
#include "llvm/TargetParser/Triple.h"
|
||||
#include <optional>
|
||||
|
||||
|
|
@ -6129,8 +6130,8 @@ Sema::CreateLaunchBoundsAttr(const AttributeCommonInfo &CI, Expr *MaxThreads,
|
|||
// launch bounds attribute within ompx_attribute to support other archs.
|
||||
if (!IgnoreArch) {
|
||||
// '.maxclusterrank' ptx directive requires .target sm_90 or higher.
|
||||
auto SM = getOffloadArch(Context.getTargetInfo());
|
||||
if (SM == OffloadArch::Unknown || SM < OffloadArch::SM_90) {
|
||||
OffloadArch SM = getOffloadArch(Context.getTargetInfo());
|
||||
if (SM.isUnknown() || llvm::NVPTX::getSmVersion(SM.nvptxKind()) < 900) {
|
||||
Diag(MaxBlocks->getBeginLoc(), diag::warn_cuda_maxclusterrank_sm_90)
|
||||
<< OffloadArchToString(SM) << CI << MaxBlocks->getSourceRange();
|
||||
// Ignore it by setting MaxBlocks to null;
|
||||
|
|
@ -6244,7 +6245,8 @@ void Sema::addNoClusterAttr(Decl *D, const AttributeCommonInfo &CI) {
|
|||
static void handleClusterDimsAttr(Sema &S, Decl *D, const ParsedAttr &AL) {
|
||||
const TargetInfo &TTI = S.Context.getTargetInfo();
|
||||
OffloadArch Arch = StringToOffloadArch(TTI.getTargetOpts().CPU);
|
||||
if ((TTI.getTriple().isNVPTX() && Arch < clang::OffloadArch::SM_90) ||
|
||||
if ((TTI.getTriple().isNVPTX() &&
|
||||
llvm::NVPTX::getSmVersion(Arch.nvptxKind()) < 900) ||
|
||||
(TTI.getTriple().isAMDGPU() &&
|
||||
!TTI.hasFeatureEnabled(TTI.getTargetOpts().FeatureMap, "clusters"))) {
|
||||
S.Diag(AL.getLoc(), diag::err_cluster_attr_not_supported) << AL;
|
||||
|
|
@ -6263,7 +6265,8 @@ static void handleClusterDimsAttr(Sema &S, Decl *D, const ParsedAttr &AL) {
|
|||
static void handleNoClusterAttr(Sema &S, Decl *D, const ParsedAttr &AL) {
|
||||
const TargetInfo &TTI = S.Context.getTargetInfo();
|
||||
OffloadArch Arch = StringToOffloadArch(TTI.getTargetOpts().CPU);
|
||||
if ((TTI.getTriple().isNVPTX() && Arch < clang::OffloadArch::SM_90) ||
|
||||
if ((TTI.getTriple().isNVPTX() &&
|
||||
llvm::NVPTX::getSmVersion(Arch.nvptxKind()) < 900) ||
|
||||
(TTI.getTriple().isAMDGPU() &&
|
||||
!TTI.hasFeatureEnabled(TTI.getTargetOpts().FeatureMap, "clusters"))) {
|
||||
S.Diag(AL.getLoc(), diag::err_cluster_attr_not_supported) << AL;
|
||||
|
|
|
|||
|
|
@ -59,7 +59,6 @@
|
|||
// CHECK-SAME: {{^}}, gfx803
|
||||
// CHECK-SAME: {{^}}, gfx805
|
||||
// CHECK-SAME: {{^}}, gfx810
|
||||
// CHECK-SAME: {{^}}, gfx9-generic
|
||||
// CHECK-SAME: {{^}}, gfx900
|
||||
// CHECK-SAME: {{^}}, gfx902
|
||||
// CHECK-SAME: {{^}}, gfx904
|
||||
|
|
@ -68,15 +67,12 @@
|
|||
// CHECK-SAME: {{^}}, gfx909
|
||||
// CHECK-SAME: {{^}}, gfx90a
|
||||
// CHECK-SAME: {{^}}, gfx90c
|
||||
// CHECK-SAME: {{^}}, gfx9-4-generic
|
||||
// CHECK-SAME: {{^}}, gfx942
|
||||
// CHECK-SAME: {{^}}, gfx950
|
||||
// CHECK-SAME: {{^}}, gfx10-1-generic
|
||||
// CHECK-SAME: {{^}}, gfx1010
|
||||
// CHECK-SAME: {{^}}, gfx1011
|
||||
// CHECK-SAME: {{^}}, gfx1012
|
||||
// CHECK-SAME: {{^}}, gfx1013
|
||||
// CHECK-SAME: {{^}}, gfx10-3-generic
|
||||
// CHECK-SAME: {{^}}, gfx1030
|
||||
// CHECK-SAME: {{^}}, gfx1031
|
||||
// CHECK-SAME: {{^}}, gfx1032
|
||||
|
|
@ -84,7 +80,6 @@
|
|||
// CHECK-SAME: {{^}}, gfx1034
|
||||
// CHECK-SAME: {{^}}, gfx1035
|
||||
// CHECK-SAME: {{^}}, gfx1036
|
||||
// CHECK-SAME: {{^}}, gfx11-generic
|
||||
// CHECK-SAME: {{^}}, gfx1100
|
||||
// CHECK-SAME: {{^}}, gfx1101
|
||||
// CHECK-SAME: {{^}}, gfx1102
|
||||
|
|
@ -94,17 +89,39 @@
|
|||
// CHECK-SAME: {{^}}, gfx1152
|
||||
// CHECK-SAME: {{^}}, gfx1153
|
||||
// CHECK-SAME: {{^}}, gfx1154
|
||||
// CHECK-SAME: {{^}}, gfx11-7-generic
|
||||
// CHECK-SAME: {{^}}, gfx1170
|
||||
// CHECK-SAME: {{^}}, gfx1171
|
||||
// CHECK-SAME: {{^}}, gfx1172
|
||||
// CHECK-SAME: {{^}}, gfx12-generic
|
||||
// CHECK-SAME: {{^}}, gfx1200
|
||||
// CHECK-SAME: {{^}}, gfx1201
|
||||
// CHECK-SAME: {{^}}, gfx12-5-generic
|
||||
// CHECK-SAME: {{^}}, gfx1250
|
||||
// CHECK-SAME: {{^}}, gfx1251
|
||||
// CHECK-SAME: {{^}}, gfx13-generic
|
||||
// CHECK-SAME: {{^}}, gfx1310
|
||||
// CHECK-SAME: {{^}}, amdgcnspirv
|
||||
// CHECK-SAME: {{^}}, gfx9-generic
|
||||
// CHECK-SAME: {{^}}, gfx9-4-generic
|
||||
// CHECK-SAME: {{^}}, gfx10-1-generic
|
||||
// CHECK-SAME: {{^}}, gfx10-3-generic
|
||||
// CHECK-SAME: {{^}}, gfx11-generic
|
||||
// CHECK-SAME: {{^}}, gfx11-7-generic
|
||||
// CHECK-SAME: {{^}}, gfx12-generic
|
||||
// CHECK-SAME: {{^}}, gfx12-5-generic
|
||||
// CHECK-SAME: {{^}}, gfx13-generic
|
||||
// CHECK-SAME: {{^}}, tahiti
|
||||
// CHECK-SAME: {{^}}, pitcairn
|
||||
// CHECK-SAME: {{^}}, verde
|
||||
// CHECK-SAME: {{^}}, hainan
|
||||
// CHECK-SAME: {{^}}, oland
|
||||
// CHECK-SAME: {{^}}, kaveri
|
||||
// CHECK-SAME: {{^}}, hawaii
|
||||
// CHECK-SAME: {{^}}, kabini
|
||||
// CHECK-SAME: {{^}}, mullins
|
||||
// CHECK-SAME: {{^}}, bonaire
|
||||
// CHECK-SAME: {{^}}, carrizo
|
||||
// CHECK-SAME: {{^}}, iceland
|
||||
// CHECK-SAME: {{^}}, tonga
|
||||
// CHECK-SAME: {{^}}, fiji
|
||||
// CHECK-SAME: {{^}}, polaris10
|
||||
// CHECK-SAME: {{^}}, polaris11
|
||||
// CHECK-SAME: {{^}}, tongapro
|
||||
// CHECK-SAME: {{^}}, stoney
|
||||
// CHECK-SAME: {{$}}
|
||||
|
|
|
|||
|
|
@ -11,26 +11,49 @@
|
|||
|
||||
using namespace clang;
|
||||
|
||||
TEST(OffloadArchTest, basic) {
|
||||
EXPECT_TRUE(IsNVIDIAOffloadArch(OffloadArch::SM_20));
|
||||
EXPECT_TRUE(IsNVIDIAOffloadArch(OffloadArch::SM_120a));
|
||||
EXPECT_FALSE(IsNVIDIAOffloadArch(OffloadArch::GFX600));
|
||||
static OffloadArch parse(llvm::StringRef S) { return StringToOffloadArch(S); }
|
||||
|
||||
EXPECT_FALSE(IsAMDOffloadArch(OffloadArch::SM_120a));
|
||||
EXPECT_TRUE(IsAMDOffloadArch(OffloadArch::GFX600));
|
||||
EXPECT_TRUE(IsAMDOffloadArch(OffloadArch::GFX1201));
|
||||
EXPECT_TRUE(IsAMDOffloadArch(OffloadArch::GFX12_GENERIC));
|
||||
EXPECT_TRUE(IsAMDOffloadArch(OffloadArch::AMDGCNSPIRV));
|
||||
EXPECT_FALSE(IsAMDOffloadArch(OffloadArch::GRANITERAPIDS));
|
||||
TEST(OffloadArchTest, VendorClassification) {
|
||||
EXPECT_TRUE(IsNVIDIAOffloadArch(parse("sm_20")));
|
||||
EXPECT_TRUE(IsNVIDIAOffloadArch(parse("sm_120a")));
|
||||
EXPECT_FALSE(IsNVIDIAOffloadArch(parse("gfx600")));
|
||||
|
||||
EXPECT_TRUE(IsIntelOffloadArch(OffloadArch::GRANITERAPIDS));
|
||||
EXPECT_TRUE(IsIntelCPUOffloadArch(OffloadArch::GRANITERAPIDS));
|
||||
EXPECT_FALSE(IsIntelGPUOffloadArch(OffloadArch::GRANITERAPIDS));
|
||||
EXPECT_TRUE(IsIntelOffloadArch(OffloadArch::BMG_G21));
|
||||
EXPECT_FALSE(IsIntelCPUOffloadArch(OffloadArch::BMG_G21));
|
||||
EXPECT_TRUE(IsIntelGPUOffloadArch(OffloadArch::BMG_G21));
|
||||
EXPECT_FALSE(IsAMDOffloadArch(parse("sm_120a")));
|
||||
EXPECT_TRUE(IsAMDOffloadArch(parse("gfx600")));
|
||||
EXPECT_TRUE(IsAMDOffloadArch(parse("gfx1201")));
|
||||
EXPECT_TRUE(IsAMDOffloadArch(parse("gfx12-generic")));
|
||||
EXPECT_TRUE(IsAMDOffloadArch(parse("amdgcnspirv")));
|
||||
EXPECT_FALSE(IsAMDOffloadArch(parse("graniterapids")));
|
||||
|
||||
EXPECT_FALSE(IsNVIDIAOffloadArch(OffloadArch::Generic));
|
||||
EXPECT_FALSE(IsAMDOffloadArch(OffloadArch::Generic));
|
||||
EXPECT_FALSE(IsIntelOffloadArch(OffloadArch::Generic));
|
||||
EXPECT_TRUE(IsIntelOffloadArch(parse("graniterapids")));
|
||||
EXPECT_TRUE(IsIntelCPUOffloadArch(parse("graniterapids")));
|
||||
EXPECT_FALSE(IsIntelGPUOffloadArch(parse("graniterapids")));
|
||||
EXPECT_TRUE(IsIntelOffloadArch(parse("bmg_g21")));
|
||||
EXPECT_FALSE(IsIntelCPUOffloadArch(parse("bmg_g21")));
|
||||
EXPECT_TRUE(IsIntelGPUOffloadArch(parse("bmg_g21")));
|
||||
|
||||
EXPECT_FALSE(IsNVIDIAOffloadArch(parse("generic")));
|
||||
EXPECT_FALSE(IsAMDOffloadArch(parse("generic")));
|
||||
EXPECT_FALSE(IsIntelOffloadArch(parse("generic")));
|
||||
}
|
||||
|
||||
TEST(OffloadArchTest, Unknown) {
|
||||
EXPECT_TRUE(parse("not-a-real-arch").isUnknown());
|
||||
EXPECT_TRUE(parse("").isUnused());
|
||||
}
|
||||
|
||||
// Names must round-trip through parse -> string.
|
||||
TEST(OffloadArchTest, RoundTrip) {
|
||||
for (const char *Name :
|
||||
{"sm_52", "sm_90a", "gfx906", "gfx1201", "gfx12-generic", "amdgcnspirv",
|
||||
"graniterapids", "bmg_g21", "generic"}) {
|
||||
OffloadArch A = parse(Name);
|
||||
EXPECT_FALSE(A.isUnknown()) << Name;
|
||||
EXPECT_STREQ(OffloadArchToString(A), Name);
|
||||
}
|
||||
}
|
||||
|
||||
TEST(OffloadArchTest, Defaults) {
|
||||
EXPECT_STREQ(OffloadArchToString(OffloadArch::CudaDefault()), "sm_52");
|
||||
EXPECT_STREQ(OffloadArchToString(OffloadArch::HIPDefault()), "gfx906");
|
||||
}
|
||||
|
|
|
|||
|
|
@ -31,7 +31,7 @@ class Triple;
|
|||
namespace AMDGPU {
|
||||
|
||||
/// GPU kinds supported by the AMDGPU target.
|
||||
enum GPUKind : uint32_t {
|
||||
enum GPUKind : uint8_t {
|
||||
// Not specified processor.
|
||||
GK_NONE = 0,
|
||||
|
||||
|
|
|
|||
|
|
@ -17,11 +17,15 @@ namespace llvm {
|
|||
namespace NVPTX {
|
||||
|
||||
/// GPU kinds supported by the NVPTX target.
|
||||
enum GPUKind : uint32_t {
|
||||
enum GPUKind : uint8_t {
|
||||
GK_NONE = 0,
|
||||
#define NVPTX_GPU(NAME, KIND, VIRTUAL, SM_ID, MIN_VER, MAX_VER, SUFFIX) \
|
||||
GK_##KIND,
|
||||
#include "llvm/TargetParser/NVPTXTargetParser.def"
|
||||
|
||||
// Alias for the last GPUKind. Keep in sync with the final .def row.
|
||||
// FIXME: Should be generated once the GPU list moves to TableGen.
|
||||
GK_LAST = GK_SM_121f,
|
||||
};
|
||||
|
||||
/// Suffix class of an NVPTX architecture name. Enumerator spellings match the
|
||||
|
|
|
|||
Loading…
Reference in a new issue