3c3a18e239
OffloadArch was a flat enum that hand-duplicated every AMDGPU and NVPTX target, plus a few edge cases. This was yet another place that needed updating every time a new target is added, which should now be avoided. Replace with a tagged union-like scheme. Co-authored-by: Claude (Claude-Opus-4.8) <noreply@anthropic.com>
118 lines
4 KiB
C++
118 lines
4 KiB
C++
//===----------------------------------------------------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "clang/Basic/OffloadArch.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/StringRef.h"
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#include "llvm/TargetParser/AMDGPUTargetParser.h"
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#include "llvm/TargetParser/NVPTXTargetParser.h"
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#include "llvm/TargetParser/Triple.h"
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namespace clang {
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OffloadArch OffloadArch::CudaDefault() {
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return getNVPTX(llvm::NVPTX::parseArch("sm_52"));
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}
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OffloadArch OffloadArch::HIPDefault() {
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return getAMDGPU(llvm::AMDGPU::parseArchAMDGCN("gfx906"));
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}
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const char *OffloadArchToString(OffloadArch A) {
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switch (A.targetArch()) {
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case OffloadArch::TargetArch::Unused:
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return "";
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case OffloadArch::TargetArch::Unknown:
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return "unknown";
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case OffloadArch::TargetArch::NVPTX:
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return llvm::NVPTX::getArchName(A.nvptxKind()).data();
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case OffloadArch::TargetArch::AMDGPU:
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return llvm::AMDGPU::getArchNameAMDGCN(A.amdgpuKind()).data();
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case OffloadArch::TargetArch::SPIRV:
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return "amdgcnspirv";
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case OffloadArch::TargetArch::IntelCPU:
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return "graniterapids";
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case OffloadArch::TargetArch::IntelGPU:
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return "bmg_g21";
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case OffloadArch::TargetArch::Generic:
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return "generic";
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}
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return "unknown";
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}
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const char *OffloadArchToVirtualArchString(OffloadArch A) {
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switch (A.targetArch()) {
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case OffloadArch::TargetArch::NVPTX:
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return llvm::NVPTX::getVirtualArch(A.nvptxKind()).data();
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case OffloadArch::TargetArch::AMDGPU:
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case OffloadArch::TargetArch::SPIRV:
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return "compute_amdgcn";
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case OffloadArch::TargetArch::Unknown:
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return "unknown";
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case OffloadArch::TargetArch::Unused:
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case OffloadArch::TargetArch::IntelCPU:
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case OffloadArch::TargetArch::IntelGPU:
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case OffloadArch::TargetArch::Generic:
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return "";
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}
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return "unknown";
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}
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OffloadArch StringToOffloadArch(llvm::StringRef S) {
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// The empty string denotes the "unused" architecture.
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if (S.empty())
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return OffloadArch::getUnused();
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// Non-GPU-table pseudo/sentinel architectures.
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if (S == "amdgcnspirv")
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return OffloadArch::getSPIRV();
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if (S == "generic")
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return OffloadArch::getGeneric();
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if (S == "graniterapids")
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return OffloadArch::getIntel(OffloadArch::TargetArch::IntelCPU,
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OffloadArch::IntelArch::GRANITERAPIDS);
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if (S == "bmg_g21")
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return OffloadArch::getIntel(OffloadArch::TargetArch::IntelGPU,
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OffloadArch::IntelArch::BMG_G21);
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// Otherwise defer to the vendor TargetParser GPU lists.
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if (llvm::NVPTX::GPUKind NV = llvm::NVPTX::parseArch(S))
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return OffloadArch::getNVPTX(NV);
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if (llvm::AMDGPU::GPUKind AK = llvm::AMDGPU::parseArchAMDGCN(S))
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return OffloadArch::getAMDGPU(AK);
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return OffloadArch::getUnknown();
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}
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void fillValidOffloadArchList(llvm::SmallVectorImpl<llvm::StringRef> &Values) {
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#define NVPTX_GPU(NAME, KIND, VIRTUAL, SM_ID, MIN_VER, MAX_VER, SUFFIX) \
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Values.push_back(NAME);
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#include "llvm/TargetParser/NVPTXTargetParser.def"
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llvm::AMDGPU::fillValidArchListAMDGCN(Values, llvm::Triple::NoSubArch);
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}
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llvm::Triple OffloadArchToTriple(const llvm::Triple &DefaultToolchainTriple,
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OffloadArch ID) {
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if (ID.isSPIRV())
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return llvm::Triple(llvm::Triple::spirv64, llvm::Triple::NoSubArch,
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llvm::Triple::AMD, llvm::Triple::AMDHSA);
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if (ID.isNVPTX()) {
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llvm::Triple::ArchType Arch = DefaultToolchainTriple.isArch64Bit()
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? llvm::Triple::nvptx64
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: llvm::Triple::nvptx;
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return llvm::Triple(Arch, llvm::Triple::NoSubArch, llvm::Triple::NVIDIA,
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llvm::Triple::CUDA);
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}
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if (ID.isAMDGPU())
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return llvm::Triple("amdgcn-amd-amdhsa");
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return {};
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}
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} // namespace clang
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