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Atomics
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[AArch64] fix 128-bit Sequentially Consistent load (#206936)
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2026-07-09 10:16:48 +01:00 |
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GlobalISel
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[spr] initial version
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2026-08-01 20:25:42 +00:00 |
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sve2p3-intrinsics
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[clang][AArch64][SVE2p3][SME2p3] Add intrinsics for v9.7a shift operations (#186087)
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2026-04-28 13:48:48 +01:00 |
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2s-complement-asm.ll
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16bit-float-promotion-with-nofp.ll
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128bit_load_store.ll
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a55-fuse-address.mir
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a57-csel.ll
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aarch-multipart.ll
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aarch64-2014-08-11-MachineCombinerCrash.ll
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aarch64-2014-12-02-combine-soften.ll
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aarch64-a57-fp-load-balancing.ll
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aarch64-address-type-promotion-assertion.ll
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aarch64-address-type-promotion.ll
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aarch64-addv.ll
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aarch64-avoid-illegal-extract-subvector.ll
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aarch64-be-bv.ll
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aarch64-bf16-dotprod-intrinsics.ll
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aarch64-bf16-ldst-intrinsics.ll
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[LLVM][CodeGen] Remove +bf16 for ARM/AArch64 tests that don't strictly need the feature flag. (#204199)
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2026-06-23 12:29:11 +01:00 |
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aarch64-bif-gen.ll
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aarch64-bit-gen.ll
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aarch64-bitwisenot-fold.ll
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aarch64-bswap-ext.ll
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aarch64-checkMergeStoreCandidatesForDependencies.ll
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aarch64-codegen-prepare-atp.ll
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aarch64-combine-add-sub-mul.ll
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aarch64-combine-add-zext.ll
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aarch64-combine-fmul-fsub.mir
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aarch64-combine-gather-lanes-limit-size.mir
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aarch64-combine-gather-lanes-with-call.mir
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aarch64-combine-gather-lanes.mir
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aarch64-condopt-chaining.mir
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[AArch64] ConditionOptimizer: replace intra-block scan with map-based algorithm (#190455)
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2026-04-30 12:40:44 +01:00 |
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aarch64-condopt-cross-block-different-regs.mir
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aarch64-condopt-nzcvdef.mir
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aarch64-condopt-select-instrs.mir
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[AArch64] ConditionOptimizer: widen intra-block path to all select instructions (#195266)
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2026-05-07 19:39:02 +01:00 |
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aarch64-condopt-unsigned.mir
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aarch64-DAGCombine-findBetterNeighborChains-crash.ll
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aarch64-dup-dot-crash.ll
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aarch64-dup-ext-crash.ll
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aarch64-dup-ext-scalable.ll
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aarch64-dup-ext-vectortype-crash.ll
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aarch64-dup-ext.ll
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[AArch64][GlobalISel] Lower unmerge to extract_subvector (#195046)
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2026-05-05 17:39:07 +01:00 |
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aarch64-dup-extract-scalable.ll
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aarch64-dynamic-stack-layout.ll
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aarch64-f16f32dot-intrinsics.ll
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[AArch64] Add intrinsic support for Fdot instr. (#189987)
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2026-06-02 12:17:02 +01:00 |
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aarch64-fastcc-stackup.ll
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Revert "[AArch64][GlobalISel] Do not run the Localizer at -O0 (#177359)" (#193781)
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2026-04-23 16:38:44 +01:00 |
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aarch64-fix-cortex-a53-835769.ll
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aarch64-fixup-statepoint-regs-crash.ll
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aarch64-fmuladd.ll
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[AArch64] Don't call fma/fmaf for @llvm.fmuladd.f64/f32 in softfp (#205356)
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2026-06-25 11:48:02 +01:00 |
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aarch64-fold-lslfast.ll
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aarch64-gep-opt.ll
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aarch64-histcnt-dag-combine-hang.ll
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aarch64-icmp-opt.ll
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aarch64-inline-asm-bitcast-crash.ll
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[AArch64] Lower i16/f16 bitcast via vector operations. (#196341)
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2026-05-15 15:17:48 +00:00 |
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aarch64-insert-subvector-undef.ll
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aarch64-interleaved-access-w-undef.ll
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aarch64-interleaved-ld-combine.ll
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aarch64-isel-csinc-type.ll
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aarch64-isel-csinc.ll
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aarch64-isel-umin.ll
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[AArch64] Regenerate aarch64-isel-umin.ll. NFC (#198337)
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2026-05-18 17:23:26 +01:00 |
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aarch64-known-bits-hadd.ll
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[GlobalISel] Add G_UAVGFLOOR/G_UAVGCEIL/G_SAVGFLOOR/G_SAVGCEIL to computeKnownBits (#209171)
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2026-07-14 12:12:23 +01:00 |
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aarch64-large-stack-spbump.mir
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[CodeGen] Rename prologpeilog to prolog-epilog (#207870)
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2026-07-06 18:26:05 -07:00 |
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aarch64-ldst-modified-baseReg.mir
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aarch64-ldst-no-premature-sp-pop.mir
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aarch64-ldst-opt-instr-ref.mir
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aarch64-ldst-subsuperReg-no-ldp.mir
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aarch64-load-ext.ll
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aarch64-loop-gep-opt.ll
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aarch64-lsr-bfi.ll
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aarch64-matmul-fp16.ll
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aarch64-matmul-fp32.ll
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aarch64-matmul.ll
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aarch64-matrix-umull-smull.ll
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[AArch64][GlobalISel] Fold G_SHUFFLE to single-element TBL with zero elements. (#200938)
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2026-07-11 08:12:13 +01:00 |
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aarch64-mcpu-oryon-runtime-unroll.ll
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aarch64-minmaxv.ll
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[LLVM][CodeGen][SVE] Extend NEON->SVE splat imm isel to cover 64-bit vectors. (#209833)
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2026-07-22 11:01:27 +01:00 |
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aarch64-mixed-ptr-sizes.ll
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aarch64-mops-consecutive.ll
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aarch64-mops-mte.ll
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aarch64-mops.ll
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[GlobalISel] Fix volatile flag handling in memmove legalizer (#206025)
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2026-07-23 16:27:42 +00:00 |
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aarch64-mov-debug-locs.mir
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aarch64-mull-masks.ll
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[AArch64] Generate umaddl and smaddl from disjoint or (#200198)
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2026-06-01 07:09:56 +00:00 |
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aarch64-mulv.ll
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[AArch64][GlobalISel] Improve multiplication with multiple registers (#197943)
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2026-05-16 20:47:25 +02:00 |
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aarch64-named-reg-w18.ll
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aarch64-named-reg-x18.ll
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aarch64-neon-faminmax.ll
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aarch64-neon-vector-insert-uaddlv.ll
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Revert "[AArch64] Run cleanup one final time after peephole (#199711)" (#205633)
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2026-06-24 19:28:07 +01:00 |
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aarch64-p2align-max-bytes-neoverse.ll
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aarch64-p2align-max-bytes.ll
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aarch64-pmull2.ll
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aarch64-post-coalescer.mir
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aarch64-pseudo-probe-tail-call.ll
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[PseudoProbe] Preserve pseudoprobe for tailcall pseudo instrs (#197246)
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2026-06-02 08:50:08 -07:00 |
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aarch64-reassociate-accumulators-sve.ll
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[NFC][LLVM][Tests] Replace instances of @llvm.aarch64.sve.ptrue.nxv16i1(i32 31) with splat (i1 true). (#204113)
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2026-06-16 12:44:06 +01:00 |
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aarch64-reassociate-accumulators.ll
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aarch64-saturating-arithmetic.ll
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aarch64-scal-to-vec-bitcast-insert.ll
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aarch64-scalarize-vec-load-ext.ll
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aarch64-sched-store.ll
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aarch64-signedreturnaddress.ll
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aarch64-smax-constantfold.ll
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aarch64-sme-stubs.ll
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[compiler-rt] Don't provide __arm_sme_state for baremetal targets (#191434)
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2026-04-20 10:00:18 +01:00 |
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aarch64-sme-za-call-lowering.ll
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Revert "[AArch64] Fix definition of system register move instructions" (#201137)
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2026-06-02 16:44:37 +01:00 |
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aarch64-sme2-asm.ll
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[AMDGPU][NFC] Update MIR tests to use symbolic INLINEASM operands (#186839)
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2026-04-17 12:23:56 +01:00 |
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aarch64-smov-gen.ll
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aarch64-smull.ll
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[LLVM][CodeGen][SVE] Extend NEON->SVE splat imm isel to cover 64-bit vectors. (#209833)
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2026-07-22 11:01:27 +01:00 |
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aarch64-split-logic-bitmask-immediate.ll
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aarch64-stp-cluster.ll
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aarch64-sve-and-combine-crash.ll
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aarch64-sve-asm-negative.ll
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[CodeGen][NFC] Remove contractions in error messages (#195308)
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2026-05-01 11:23:24 -07:00 |
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aarch64-sve-asm.ll
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[NFC][LLVM][Tests] Replace instances of @llvm.aarch64.sve.ptrue.nxv16i1(i32 31) with splat (i1 true). (#204113)
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2026-06-16 12:44:06 +01:00 |
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aarch64-sve-fill-spill-pair.ll
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aarch64-sve-ldst-one.ll
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aarch64-sve-setcc-promote-nxv8i8-crash.ll
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aarch64-sve2-faminmax.ll
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aarch64-swp-ws-live-intervals-1.mir
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aarch64-swp-ws-live-intervals.mir
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aarch64-sys-intrinsic.ll
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[AArch64][llvm] Remove support for FEAT_MPAMv2_VID (#193191)
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2026-04-24 12:01:32 +01:00 |
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aarch64-sysreg128.ll
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Revert "[AArch64] Fix definition of system register move instructions" (#201137)
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2026-06-02 16:44:37 +01:00 |
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aarch64-tail-dup-size.ll
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aarch64-tbz.ll
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[GISel] Disable opt_brcond_by_inverting_cond combine at O0 (#193417)
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2026-04-24 09:11:23 +01:00 |
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aarch64-tensorflow-isel-regression.ll
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aarch64-tls-flags.ll
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aarch64-tryBitfieldInsertOpFromOr-crash.ll
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aarch64-unroll-and-jam.ll
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aarch64-uzp1-combine.ll
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aarch64-v1f32-arg.ll
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aarch64-vcvtfp2fxs-combine.ll
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aarch64-vector-pcs.mir
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[CodeGen] Rename prologpeilog to prolog-epilog (#207870)
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2026-07-06 18:26:05 -07:00 |
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aarch64-vectorcombine-invalid-extract-index-crash.ll
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aarch64-vuzp.ll
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aarch64-wide-mul.ll
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aarch64-wide-shuffle.ll
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aarch64-za-clobber.ll
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[AMDGPU][NFC] Update MIR tests to use symbolic INLINEASM operands (#186839)
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2026-04-17 12:23:56 +01:00 |
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aarch64_be-global-const.ll
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aarch64_be-shuffle-vector.ll
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[AArch64] Use dup (lane mov) over ext for high-half extract (#195010)
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2026-05-11 07:31:59 +00:00 |
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aarch64_f16_be.ll
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aarch64_fnmadd.ll
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aarch64_tree_tests.ll
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aarch64_win64cc_vararg.ll
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aarch64st1.mir
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abd-combine.ll
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[AArch64] Use dup (lane mov) over ext for high-half extract (#195010)
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2026-05-11 07:31:59 +00:00 |
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abds-neg.ll
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abds.ll
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abdu-neg.ll
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abdu.ll
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abs.ll
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active_lane_mask.ll
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[AArch64] Tighten conditions for expanding GET_ACTIVE_LANE_MASK (#208962)
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2026-07-14 10:20:24 -07:00 |
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adc.ll
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[AArch64][GlobalISel] Normalize and cleanup some test checks. NFC (#195016)
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2026-04-30 07:35:34 +01:00 |
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add-extract.ll
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[AArch64] Use dup (lane mov) over ext for high-half extract (#195010)
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2026-05-11 07:31:59 +00:00 |
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add-i256.ll
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add-negative.ll
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add-to-sub-imm.ll
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[AArch64] Prefer (sub x, -c) over (add x, c) if -c is cheaper. (#211020)
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2026-07-23 09:13:41 +01:00 |
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add.ll
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[AArch64][GlobalISel] Fold buildvector of bitcast (#141553)
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2026-05-16 16:30:15 +01:00 |
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addcarry-crash.ll
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addg_subg.mir
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[CodeGen] Rename prologpeilog to prolog-epilog (#207870)
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2026-07-06 18:26:05 -07:00 |
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addimm-mulimm.ll
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addp-shuffle.ll
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[AArch64] Additional Tablegen patterns for shuffle(zext(...)) and shuffle(sext(...)) to uaddlp (#195120)
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2026-05-11 20:58:51 +05:30 |
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addr-of-ret-addr.ll
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addrsig-macho.ll
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[DebugInfo] Verify DISubprogram has a type (#194556)
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2026-05-04 11:32:19 +01:00 |
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adds_cmn.ll
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addsub-24bit-imm.mir
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addsub-constant-folding.ll
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addsub-shifted-reg-cheap-as-move.ll
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addsub-shifted.ll
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addsub.ll
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addsub_ext.ll
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addtruncshift.ll
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aes.ll
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alias_mask.ll
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[SDAG] Specify unsigned compares for loop.dependence.{war|raw} masks (#197437)
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2026-07-22 10:12:01 +01:00 |
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alias_mask_i128.ll
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[IR] Remove pointer arguments from loop.dependence.{war|raw}.mask (#188248)
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2026-04-24 07:21:11 +01:00 |
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alias_mask_nosve.ll
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[IR] Remove pointer arguments from loop.dependence.{war|raw}.mask (#188248)
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2026-04-24 07:21:11 +01:00 |
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alias_mask_scalable.ll
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[SDAG] Specify unsigned compares for loop.dependence.{war|raw} masks (#197437)
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2026-07-22 10:12:01 +01:00 |
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alias_mask_scalable_nosve2.ll
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[SDAG] Specify unsigned compares for loop.dependence.{war|raw} masks (#197437)
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2026-07-22 10:12:01 +01:00 |
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align-down.ll
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alloca-load-store-scalable-array.ll
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alloca-load-store-scalable-struct.ll
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alloca-oversized.ll
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alloca.ll
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allow-check.ll
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ampere1-sched-add.mir
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analyze-branch.ll
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analyzecmp.ll
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and-mask-removal.ll
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[AArch64][SelectionDAG] Generate subs+csel for usub.sat (#193203)
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2026-04-28 09:20:29 +05:30 |
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and-mask-variable.ll
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and-sink.ll
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and_xor_shift.ll
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[AArch64] Add tests for and+xor+shift. NFC (#200250)
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2026-05-28 20:03:23 +01:00 |
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andandshift.ll
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andcompare.ll
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andorbrcompare.ll
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[AArch64][ISel] Enable profile-aware branch condition merging (#201486)
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2026-06-24 16:22:51 +01:00 |
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andorxor.ll
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[AArch64][GlobalISel] Fold buildvector of bitcast (#141553)
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2026-05-16 16:30:15 +01:00 |
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apple-latest-cpu.ll
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apply-disjoint-flag-in-dagcombine.ll
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apply-terminal-rule.mir
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arc-contract-claim-rv.ll
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arg_promotion.ll
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argument-blocks-array-of-struct.ll
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argument-blocks.ll
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arithmetic_fence.ll
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arm64-2011-03-09-CPSRSpill.ll
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arm64-2011-03-17-AsmPrinterCrash.ll
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[DebugMetadata][DwarfDebug][CodeView] Support function-local static variables in lexical block scopes (6/7) (#187927)
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2026-07-10 15:32:16 +00:00 |
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arm64-2011-03-21-Unaligned-Frame-Index.ll
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arm64-2011-04-21-CPSRBug.ll
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arm64-2011-10-18-LdStOptBug.ll
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arm64-2012-01-11-ComparisonDAGCrash.ll
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arm64-2012-05-07-DAGCombineVectorExtract.ll
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arm64-2012-05-07-MemcpyAlignBug.ll
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arm64-2012-05-09-LOADgot-bug.ll
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arm64-2012-05-22-LdStOptBug.ll
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arm64-2012-06-06-FPToUI.ll
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arm64-2012-07-11-InstrEmitterBug.ll
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arm64-2013-01-13-ffast-fcmp.ll
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arm64-2013-01-23-frem-crash.ll
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arm64-2013-01-23-sext-crash.ll
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arm64-aapcs-be.ll
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arm64-aapcs.ll
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arm64-abi-hfa-args.ll
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arm64-abi-varargs.ll
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arm64-abi.ll
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arm64-abi_align.ll
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arm64-addp.ll
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[AArch64] Extend patterns for addp to accept add-like-ors. (#193075)
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2026-04-27 19:38:28 +01:00 |
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arm64-addr-mode-folding.ll
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arm64-addr-type-promotion.ll
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arm64-addrmode.ll
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arm64-AdvSIMD-Scalar.ll
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arm64-alloc-no-stack-realign.ll
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arm64-alloca-frame-pointer-offset.ll
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arm64-andCmpBrToTBZ.ll
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arm64-ands-bad-peephole.ll
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arm64-AnInfiniteLoopInDAGCombine.ll
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arm64-anyregcc-crash.ll
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arm64-anyregcc.ll
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arm64-arith-saturating.ll
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[AArch64][GlobalISel] Add patterns for signed scalar extend intrinsics (#201617)
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2026-06-05 17:00:09 +01:00 |
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arm64-arith.ll
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arm64-arm64-dead-def-elimination-flag.ll
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arm64-assert-zext-sext.ll
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arm64-atomic-128.ll
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arm64-atomic.ll
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arm64-bcc.ll
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arm64-big-endian-bitconverts.ll
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arm64-big-endian-eh.ll
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arm64-big-endian-varargs.ll
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arm64-big-endian-vector-callee.ll
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arm64-big-endian-vector-caller.ll
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arm64-big-imm-offsets.ll
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arm64-big-stack.ll
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arm64-bitfield-extract.ll
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arm64-blockaddress.ll
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arm64-break.ll
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arm64-build-vector.ll
|
[LLVM][CodeGen] Remove +bf16 for ARM/AArch64 tests that don't strictly need the feature flag. (#204199)
|
2026-06-23 12:29:11 +01:00 |
|
arm64-builtins-linux.ll
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arm64-call-tailcalls.ll
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arm64-cast-opt.ll
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arm64-ccmp-heuristics.ll
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arm64-ccmp.ll
|
[AArch64][ISel] Enable profile-aware branch condition merging (#201486)
|
2026-06-24 16:22:51 +01:00 |
|
arm64-clrsb.ll
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arm64-coalesce-ext.ll
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arm64-coalescing-MOVi32imm.ll
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arm64-code-model-large-darwin.ll
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arm64-codegen-prepare-extload.ll
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arm64-collect-loh-garbage-crash.ll
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arm64-collect-loh-str.ll
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arm64-collect-loh.ll
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arm64-complex-ret.ll
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arm64-const-addr.ll
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arm64-constrained-fcmp-no-nans-opt.ll
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arm64-convert-v4f64.ll
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arm64-copy-phys-zero-reg.mir
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arm64-copy-tuple.ll
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arm64-crc32.ll
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arm64-crypto.ll
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arm64-cse.ll
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arm64-csel.ll
|
[AArch64][GlobalISel] Port shouldBeAdjustedToZero to GlobalISel (#195941)
|
2026-06-04 05:18:17 +00:00 |
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arm64-csldst-mmo.ll
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arm64-custom-call-saved-reg.ll
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arm64-cvt-bitcast.ll
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arm64-cvt-simd-fptoi-strictfp.ll
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arm64-cvt-simd-fptoi.ll
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arm64-cvt-simd-intrinsics.ll
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arm64-cvt-simd-round-rint-strictfp.ll
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arm64-cvt-simd-round-rint.ll
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arm64-cvt.ll
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arm64-cvtf-simd-itofp.ll
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arm64-dagcombiner-convergence.ll
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arm64-dagcombiner-dead-indexed-load.ll
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arm64-dagcombiner-load-slicing.ll
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arm64-darwin-cc.ll
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arm64-dead-def-frame-index.ll
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arm64-dead-register-def-bug.ll
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arm64-detect-vec-redux.ll
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arm64-dup.ll
|
[AArch64][GlobalISel] Fold G_SHUFFLE to single-element TBL with zero elements. (#200938)
|
2026-07-11 08:12:13 +01:00 |
|
arm64-early-ifcvt.ll
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arm64-elf-calls.ll
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arm64-elf-constpool.ll
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arm64-EXT-undef-mask.ll
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arm64-ext.ll
|
[AArch64] Use dup (lane mov) over ext for high-half extract (#195010)
|
2026-05-11 07:31:59 +00:00 |
|
arm64-extend-int-to-fp.ll
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arm64-extend.ll
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arm64-extload-knownzero.ll
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arm64-extract-insert-varidx.ll
|
[AArch64][GlobalISel] Normalize and cleanup some test checks. NFC (#195016)
|
2026-04-30 07:35:34 +01:00 |
|
arm64-extract.ll
|
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|
arm64-extract_subvector.ll
|
[AArch64] Use dup (lane mov) over ext for high-half extract (#195010)
|
2026-05-11 07:31:59 +00:00 |
|
arm64-fast-isel-addr-offset.ll
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arm64-fast-isel-alloca.ll
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arm64-fast-isel-br.ll
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arm64-fast-isel-call.ll
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arm64-fast-isel-conversion-fallback.ll
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|
arm64-fast-isel-conversion.ll
|
[AArch64][FastISel] Update arm64-fast-isel-conversion.ll check lines (NFC) (#207159)
|
2026-07-03 09:56:44 +01:00 |
|
arm64-fast-isel-crc32.ll
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arm64-fast-isel-fcmp.ll
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arm64-fast-isel-gv.ll
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arm64-fast-isel-icmp.ll
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arm64-fast-isel-indirectbr.ll
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arm64-fast-isel-intrinsic.ll
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arm64-fast-isel-materialize.ll
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arm64-fast-isel-noconvert.ll
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arm64-fast-isel-rem.ll
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arm64-fast-isel-ret.ll
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arm64-fast-isel-store.ll
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arm64-fast-isel-tag.ll
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arm64-fast-isel.ll
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arm64-fastcc-tailcall.ll
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arm64-fastisel-gep-promote-before-add.ll
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arm64-fcmp-opt.ll
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arm64-fcopysign.ll
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arm64-fixed-point-scalar-cvt-dagcombine.ll
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arm64-fma-combine-with-fpfusion.ll
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arm64-fma-combines.ll
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arm64-fmadd.ll
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arm64-fmax-safe.ll
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|
arm64-fmax.ll
|
[ValueTracking] Fix signed zero handling in minnum/maxnum matching (#210077)
|
2026-07-24 10:25:27 +02:00 |
|
arm64-fminv.ll
|
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|
arm64-fml-combines.ll
|
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arm64-fmuladd.ll
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arm64-fold-address.ll
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arm64-fold-lshr.ll
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arm64-fold-lsl.ll
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arm64-fp-contract-zero.ll
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arm64-fp-imm-size.ll
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arm64-fp-imm.ll
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arm64-fp.ll
|
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|
arm64-fp128-folding.ll
|
|
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|
arm64-fp128.ll
|
[AArch64] Fold any/sign-extend of CSET. (#207414)
|
2026-07-08 10:34:12 +01:00 |
|
arm64-fpcr.ll
|
|
|
|
arm64-fpenv.ll
|
[AArch64] Add flag to conditionally write FPMR (#203911)
|
2026-06-23 14:13:03 +01:00 |
|
arm64-frame-index.ll
|
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|
arm64-global-address.ll
|
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arm64-hello.ll
|
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arm64-hlt.ll
|
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arm64-homogeneous-prolog-epilog-bad-outline.mir
|
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arm64-homogeneous-prolog-epilog-frame-tail.ll
|
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arm64-homogeneous-prolog-epilog-no-helper.ll
|
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arm64-homogeneous-prolog-epilog-odd-csrs.ll
|
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|
arm64-homogeneous-prolog-epilog-tail-call.mir
|
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|
arm64-homogeneous-prolog-epilog.ll
|
[AArch64] Set NoPHIs for outlined functions (#209852)
|
2026-07-22 08:57:52 -07:00 |
|
arm64-i16-subreg-extract.ll
|
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|
arm64-icmp-opt.ll
|
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arm64-indexed-memory.ll
|
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|
arm64-indexed-vector-ldst-2.ll
|
|
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|
arm64-indexed-vector-ldst.ll
|
[AArch64] Change postinc index types to uint64_t (#202024)
|
2026-06-06 11:16:27 +01:00 |
|
arm64-inline-asm-error-I.ll
|
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|
arm64-inline-asm-error-J.ll
|
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arm64-inline-asm-error-K.ll
|
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arm64-inline-asm-error-L.ll
|
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arm64-inline-asm-error-M.ll
|
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arm64-inline-asm-error-N.ll
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arm64-inline-asm-zero-reg-error.ll
|
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|
arm64-inline-asm.ll
|
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|
arm64-instruction-mix-remarks.ll
|
[DebugInfo] Verify DISubprogram has a type (#194556)
|
2026-05-04 11:32:19 +01:00 |
|
arm64-int-neon.ll
|
[AArch64][GlobalISel] Add handling for scalar sqabs intrinsic (#200222)
|
2026-06-02 10:19:35 +01:00 |
|
arm64-isel-or.ll
|
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|
arm64-join-reserved.ll
|
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arm64-jumptable.ll
|
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arm64-large-frame.ll
|
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arm64-ld-from-st.ll
|
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arm64-ld1.ll
|
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arm64-ldp-aa.ll
|
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arm64-ldp-cluster.ll
|
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|
arm64-ldp.ll
|
|
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|
arm64-ldst-unscaled-pre-post.mir
|
[AArch64] Do not generate indexed addressing mode for volatile accesses (#196305)
|
2026-05-28 13:08:05 +00:00 |
|
arm64-ldur.ll
|
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|
arm64-ldxr-stxr.ll
|
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|
arm64-leaf.ll
|
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arm64-long-shift.ll
|
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|
arm64-memcpy-inline.ll
|
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arm64-memset-inline.ll
|
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arm64-memset-to-bzero-pgso.ll
|
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arm64-memset-to-bzero.ll
|
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arm64-misaligned-memcpy-inline.ll
|
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arm64-misched-basic-A53.ll
|
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arm64-misched-basic-A57.ll
|
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arm64-misched-forwarding-A53.ll
|
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arm64-misched-memdep-bug.ll
|
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|
arm64-misched-multimmo.ll
|
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|
arm64-movi.ll
|
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|
arm64-mte.ll
|
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|
arm64-mul.ll
|
[AArch64] Combine A + zext(B) * C -> A - zext(B) * -C (#198488)
|
2026-05-22 06:17:28 +00:00 |
|
arm64-named-reg-alloc.ll
|
|
|
|
arm64-named-reg-notareg.ll
|
Revert "[AArch64] Fix definition of system register move instructions" (#201137)
|
2026-06-02 16:44:37 +01:00 |
|
arm64-narrow-st-merge.ll
|
|
|
|
arm64-neg.ll
|
|
|
|
arm64-neon-2velem-high.ll
|
[AArch64] Use dup (lane mov) over ext for high-half extract (#195010)
|
2026-05-11 07:31:59 +00:00 |
|
arm64-neon-2velem.ll
|
[AArch64] Use dup (lane mov) over ext for high-half extract (#195010)
|
2026-05-11 07:31:59 +00:00 |
|
arm64-neon-3vdiff.ll
|
[AArch64] Use dup (lane mov) over ext for high-half extract (#195010)
|
2026-05-11 07:31:59 +00:00 |
|
arm64-neon-aba-abd.ll
|
[AArch64][GlobalISel] Fold G_SHUFFLE to single-element TBL with zero elements. (#200938)
|
2026-07-11 08:12:13 +01:00 |
|
arm64-neon-across.ll
|
|
|
|
arm64-neon-add-pairwise.ll
|
[AArch64] Use dup (lane mov) over ext for high-half extract (#195010)
|
2026-05-11 07:31:59 +00:00 |
|
arm64-neon-add-sub.ll
|
|
|
|
arm64-neon-copy.ll
|
[AArch64][GlobalISel] Add handling for scalar sqabs intrinsic (#200222)
|
2026-06-02 10:19:35 +01:00 |
|
arm64-neon-copyPhysReg-tuple.ll
|
|
|
|
arm64-neon-mul-div-cte.ll
|
|
|
|
arm64-neon-mul-div.ll
|
[AArch64][GlobalISel] Add support for pmul intrinsic (#198809)
|
2026-05-28 17:11:25 +01:00 |
|
arm64-neon-scalar-by-elem-mul.ll
|
|
|
|
arm64-neon-select_cc.ll
|
|
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|
arm64-neon-simd-ldst-one.ll
|
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|
arm64-neon-simd-shift.ll
|
|
|
|
arm64-neon-simd-vget.ll
|
[AArch64] Use dup (lane mov) over ext for high-half extract (#195010)
|
2026-05-11 07:31:59 +00:00 |
|
arm64-neon-st-lane-aa.ll
|
|
|
|
arm64-neon-v1i1-setcc.ll
|
[AArch64] Fold any/sign-extend of CSET. (#207414)
|
2026-07-08 10:34:12 +01:00 |
|
arm64-neon-v8.1a.ll
|
|
|
|
arm64-neon-vector-list-spill.ll
|
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|
arm64-neon-vector-shuffle-extract.ll
|
|
|
|
arm64-non-pow2-ldst.ll
|
|
|
|
arm64-nvcast.ll
|
|
|
|
arm64-opt-remarks-lazy-bfi.ll
|
[spr] initial version
|
2026-08-01 20:25:42 +00:00 |
|
arm64-patchpoint-scratch-regs.ll
|
|
|
|
arm64-patchpoint.ll
|
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|
|
arm64-pic-local-symbol.ll
|
|
|
|
arm64-platform-reg.ll
|
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|
arm64-popcnt.ll
|
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|
|
arm64-prefetch-addrmode.ll
|
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|
arm64-prefetch-ir.ll
|
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|
arm64-prefetch-new.ll
|
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|
arm64-prefetch.ll
|
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|
arm64-preserve-all.ll
|
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|
arm64-preserve-most.ll
|
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|
arm64-promote-const-complex-initializers.ll
|
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|
arm64-promote-const.ll
|
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|
arm64-raddhn-combine.ll
|
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|
arm64-redzone.ll
|
|
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|
arm64-reg-copy-noneon.ll
|
|
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|
arm64-register-offset-addressing.ll
|
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|
arm64-register-pairing.ll
|
|
|
|
arm64-regress-f128csel-flags.ll
|
|
|
|
arm64-regress-interphase-shift.ll
|
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|
arm64-regress-opt-cmp-signed.mir
|
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|
arm64-regress-opt-cmp.mir
|
|
|
|
arm64-reserve-call-saved-reg.ll
|
|
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|
arm64-reserved-arg-reg-call-error.ll
|
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|
arm64-return-vector.ll
|
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|
arm64-returnaddr.ll
|
|
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|
arm64-rev.ll
|
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|
arm64-rounding.ll
|
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|
arm64-saddlp1d-uaddlp1d.mir
|
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|
arm64-scaled_iv.ll
|
|
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|
arm64-scvt.ll
|
|
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|
arm64-setcc-int-to-fp-combine.ll
|
|
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|
arm64-setcc-swap-infloop.ll
|
|
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|
arm64-shifted-sext.ll
|
|
|
|
arm64-shrink-v1i64.ll
|
|
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|
arm64-shrink-wrapping.ll
|
|
|
|
arm64-simd-scalar-to-vector.ll
|
|
|
|
arm64-simplest-elf.ll
|
|
|
|
arm64-sincos.ll
|
|
|
|
arm64-sitofp-combine-chains.ll
|
|
|
|
arm64-sli-sri-opt.ll
|
|
|
|
arm64-smaxv.ll
|
|
|
|
arm64-sminv.ll
|
|
|
|
arm64-spill-lr.ll
|
|
|
|
arm64-spill-remarks-treshold-hotness.ll
|
|
|
|
arm64-spill-remarks.ll
|
|
|
|
arm64-spill.ll
|
|
|
|
arm64-sqshl-uqshl-i64Contant.ll
|
|
|
|
arm64-srl-and.ll
|
|
|
|
arm64-st1.ll
|
|
|
|
arm64-stack-no-frame.ll
|
|
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|
arm64-stackmap-nops.ll
|
|
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|
arm64-stackmap.ll
|
|
|
|
arm64-stackpointer.ll
|
|
|
|
arm64-stacksave.ll
|
|
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|
arm64-storebytesmerge.ll
|
|
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|
arm64-stp-aa.ll
|
|
|
|
arm64-stp.ll
|
|
|
|
arm64-strict-align.ll
|
|
|
|
arm64-stur.ll
|
[AArch64] Add tablegen patterns for store of high-half. (#190320)
|
2026-04-13 17:24:14 +01:00 |
|
arm64-subsections.ll
|
|
|
|
arm64-subvector-extend.ll
|
|
|
|
arm64-summary-remarks.ll
|
[DebugInfo] Verify DISubprogram has a type (#194556)
|
2026-05-04 11:32:19 +01:00 |
|
arm64-swizzle-tbl-i16-layout.ll
|
|
|
|
arm64-tbl.ll
|
|
|
|
arm64-this-return.ll
|
[AArch64][GISel] Update and regenerate arm64-this-return.ll (#191515)
|
2026-04-10 21:32:58 +01:00 |
|
arm64-tls-darwin.ll
|
|
|
|
arm64-tls-dynamic-together.ll
|
|
|
|
arm64-tls-dynamics.ll
|
[PAC][clang] Fix ptrauth module flags behavior (#204226)
|
2026-07-13 19:07:24 +00:00 |
|
arm64-tls-initial-exec.ll
|
|
|
|
arm64-tls-local-exec.ll
|
|
|
|
arm64-trap.ll
|
|
|
|
arm64-triv-disjoint-mem-access.ll
|
|
|
|
arm64-trn.ll
|
|
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|
arm64-trunc-store.ll
|
|
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|
arm64-umaxv.ll
|
|
|
|
arm64-uminv.ll
|
|
|
|
arm64-umov.ll
|
|
|
|
arm64-unaligned_ldst.ll
|
|
|
|
arm64-uzp.ll
|
|
|
|
arm64-uzp2-combine.ll
|
|
|
|
arm64-vaargs.ll
|
|
|
|
arm64-vabs.ll
|
[AArch64] Use dup (lane mov) over ext for high-half extract (#195010)
|
2026-05-11 07:31:59 +00:00 |
|
arm64-vadd.ll
|
[AArch64] Use dup (lane mov) over ext for high-half extract (#195010)
|
2026-05-11 07:31:59 +00:00 |
|
arm64-vaddlv.ll
|
|
|
|
arm64-vaddv.ll
|
|
|
|
arm64-variadic-aapcs.ll
|
|
|
|
arm64-vbitwise.ll
|
|
|
|
arm64-vcmp.ll
|
|
|
|
arm64-vcnt.ll
|
[AArch64][GlobalISel] Add handling for cls intrinsic (#200440)
|
2026-06-03 14:00:37 +01:00 |
|
arm64-vcombine.ll
|
|
|
|
arm64-vcvt-fptoi.ll
|
|
|
|
arm64-vcvt.ll
|
|
|
|
arm64-vcvt_f.ll
|
[GlobalISel] Improve bf16 converts with fast-math flags. (#200741)
|
2026-07-11 11:08:49 +01:00 |
|
arm64-vcvt_f32_su32.ll
|
[AArch64] Remove aarch64_neon_vcvtfp2hf and aarch64_neon_vcvthf2fp (#203903)
|
2026-06-16 13:53:31 +01:00 |
|
arm64-vcvt_n.ll
|
|
|
|
arm64-vcvt_su32_f32.ll
|
|
|
|
arm64-vcvtxd_f32_f64.ll
|
|
|
|
arm64-vecCmpBr.ll
|
|
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|
arm64-vecFold.ll
|
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|
arm64-vector-ext.ll
|
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|
arm64-vector-imm.ll
|
|
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|
arm64-vector-insertion.ll
|
|
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|
arm64-vector-ldst.ll
|
|
|
|
arm64-vext.ll
|
|
|
|
arm64-vext_reverse.ll
|
|
|
|
arm64-vhadd.ll
|
[AArch64][GlobalISel] Add pre-legalizer combines for AVGFLOOR and AVGCEIL (#192866)
|
2026-05-18 19:25:57 +01:00 |
|
arm64-vhsub.ll
|
|
|
|
arm64-virtual_base.ll
|
|
|
|
arm64-vmax.ll
|
|
|
|
arm64-vminmaxnm.ll
|
|
|
|
arm64-vmovn.ll
|
|
|
|
arm64-vmul.ll
|
[AArch64][GlobalISel] Add support for scalar sqdmulh intrinsic (#198749)
|
2026-05-20 16:58:39 +01:00 |
|
arm64-volatile.ll
|
|
|
|
arm64-vqadd.ll
|
|
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|
arm64-vqsub.ll
|
|
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|
arm64-vselect.ll
|
|
|
|
arm64-vsetcc_fp.ll
|
|
|
|
arm64-vshift.ll
|
[AArch64] Use dup (lane mov) over ext for high-half extract (#195010)
|
2026-05-11 07:31:59 +00:00 |
|
arm64-vshr.ll
|
|
|
|
arm64-vshuffle.ll
|
|
|
|
arm64-vsqrt.ll
|
|
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|
arm64-vsra.ll
|
|
|
|
arm64-vsub.ll
|
|
|
|
arm64-weak-reference.ll
|
|
|
|
arm64-windows-calls.ll
|
|
|
|
arm64-windows-tailcall.ll
|
|
|
|
arm64-xaluo.ll
|
|
|
|
arm64-zero-cycle-regmove-fpr.ll
|
[AArch64] Align ZCM/ZCZ test strictness(NFC) (#200645)
|
2026-06-05 13:35:37 +03:00 |
|
arm64-zero-cycle-regmove-fpr8.mir
|
[AArch64] Align ZCM/ZCZ test strictness(NFC) (#200645)
|
2026-06-05 13:35:37 +03:00 |
|
arm64-zero-cycle-regmove-gpr.ll
|
[AArch64] Align ZCM/ZCZ test strictness(NFC) (#200645)
|
2026-06-05 13:35:37 +03:00 |
|
arm64-zero-cycle-zeroing-fpr.ll
|
[AArch64] Add -global-isel runlines to ZCZ tests(NFC) (#200797)
|
2026-06-08 15:09:04 +03:00 |
|
arm64-zero-cycle-zeroing-gpr.ll
|
[AArch64] Add -global-isel runlines to ZCZ tests(NFC) (#200797)
|
2026-06-08 15:09:04 +03:00 |
|
arm64-zeroreg.ll
|
|
|
|
arm64-zext.ll
|
|
|
|
arm64-zextload-unscaled.ll
|
|
|
|
arm64-zip.ll
|
[AArch64][GlobalISel] Add more shuffle test coverage. NFC (#207907)
|
2026-07-07 07:45:00 +01:00 |
|
arm64_32-addrs.ll
|
|
|
|
arm64_32-atomics.ll
|
|
|
|
arm64_32-fastisel.ll
|
|
|
|
arm64_32-frame-pointers.ll
|
|
|
|
arm64_32-gep-sink.ll
|
|
|
|
arm64_32-indexed-memory.ll
|
|
|
|
arm64_32-memcpy.ll
|
|
|
|
arm64_32-neon.ll
|
|
|
|
arm64_32-null.ll
|
|
|
|
arm64_32-pointer-extend.ll
|
|
|
|
arm64_32-stack-pointers.ll
|
|
|
|
arm64_32-tls.ll
|
|
|
|
arm64_32-va.ll
|
|
|
|
arm64_32.ll
|
[AArch64][ISel] Enable profile-aware branch condition merging (#201486)
|
2026-06-24 16:22:51 +01:00 |
|
arm64e-tail-call-autib.ll
|
[llvm][AArch64] Eliminate redundant mov's sandwiching aut's in tail calls (#211105)
|
2026-07-23 09:02:51 -07:00 |
|
arm64ec-alias.ll
|
|
|
|
arm64ec-available-externally.ll
|
|
|
|
arm64ec-builtins.ll
|
|
|
|
arm64ec-dllimport.ll
|
|
|
|
arm64ec-dont-call.ll
|
|
|
|
arm64ec-eh.ll
|
|
|
|
arm64ec-empty-name.ll
|
|
|
|
arm64ec-entry-thunks-local-linkage.ll
|
|
|
|
arm64ec-entry-thunks.ll
|
[Arm64EC] Add support for fp128 (#206980)
|
2026-07-02 09:07:37 +00:00 |
|
arm64ec-exit-thunks.ll
|
[CodeGen][ARM64EC] Copy first four arguments to FP registers in vararg exit thunks (#209581)
|
2026-07-16 10:55:52 +02:00 |
|
arm64ec-hybrid-patchable.ll
|
Reland [AArch64] Copy x4/x5 vararg payload into the x64 stack in Arm64EC exit thunks (#208453)
|
2026-07-13 12:34:35 +00:00 |
|
arm64ec-indirect-call.ll
|
[aarch64] Mix the frame pointer with the stack cookie when protecting the stack (#197346)
|
2026-07-01 15:33:56 +08:00 |
|
arm64ec-reservedregs.ll
|
|
|
|
arm64ec-symbols.ll
|
|
|
|
arm64ec-varargs.ll
|
|
|
|
asm-large-immediate.ll
|
|
|
|
asm-ld1-wrong-constraint.ll
|
[CodeGen][NFC] Remove contractions in error messages (#195308)
|
2026-05-01 11:23:24 -07:00 |
|
asm-print-comments.ll
|
|
|
|
asm-srcloc.ll
|
|
|
|
assertion-rc-mismatch.ll
|
|
|
|
atomic-ops-ldapr.ll
|
|
|
|
atomic-ops-lse.ll
|
|
|
|
atomic-ops-not-barriers.ll
|
|
|
|
atomic-ops.ll
|
|
|
|
atomic-oversize.ll
|
|
|
|
atomicrmw-cond-sub-clamp.ll
|
|
|
|
atomicrmw-fadd.ll
|
[AArch64] Lower i16/f16 bitcast via vector operations. (#196341)
|
2026-05-15 15:17:48 +00:00 |
|
atomicrmw-fmax.ll
|
[AArch64] Lower i16/f16 bitcast via vector operations. (#196341)
|
2026-05-15 15:17:48 +00:00 |
|
atomicrmw-fmin.ll
|
[AArch64] Lower i16/f16 bitcast via vector operations. (#196341)
|
2026-05-15 15:17:48 +00:00 |
|
atomicrmw-fsub.ll
|
[AArch64] Lower i16/f16 bitcast via vector operations. (#196341)
|
2026-05-15 15:17:48 +00:00 |
|
atomicrmw-O0.ll
|
|
|
|
atomicrmw-uinc-udec-wrap.ll
|
|
|
|
atomicrmw-xchg-fp.ll
|
[AArch64] Lower i16/f16 bitcast via vector operations. (#196341)
|
2026-05-15 15:17:48 +00:00 |
|
autoupgrade-aarch64-neon-addp-float.ll
|
|
|
|
avg.ll
|
|
|
|
avoid-free-ext-promotion.ll
|
Reapply [SimplifyCFG] Extend jump-threading to allow live local defs (#197850)
|
2026-05-22 15:18:01 -05:00 |
|
avoid-ld4.ll
|
[AArch64] Avoid factor-4 deinterleaved loads feeding uitofp (#210894)
|
2026-07-31 05:58:19 +01:00 |
|
avoid-pre-trunc.ll
|
|
|
|
avoid-zero-copy.mir
|
|
|
|
basic-block-sections-cold.ll
|
|
|
|
basic-block-sections-unsafe.ll
|
|
|
|
basic-pic.ll
|
[PAC][clang] Fix ptrauth module flags behavior (#204226)
|
2026-07-13 19:07:24 +00:00 |
|
bcax.ll
|
|
|
|
bcmp-inline-small.ll
|
|
|
|
bcmp.ll
|
|
|
|
bf16-convert-intrinsics.ll
|
|
|
|
bf16-imm.ll
|
|
|
|
bf16-instructions.ll
|
[AArch64][GlobalISel] Legalization for bf16 fptosi.sat/fptoui.sat (#209378)
|
2026-07-14 06:27:03 +00:00 |
|
bf16-select.ll
|
[LLVM][CodeGen] Remove +bf16 for ARM/AArch64 tests that don't strictly need the feature flag. (#204199)
|
2026-06-23 12:29:11 +01:00 |
|
bf16-shuffle.ll
|
[AArch64][GlobalISel] Add more shuffle test coverage. NFC (#207907)
|
2026-07-07 07:45:00 +01:00 |
|
bf16-v4-instructions.ll
|
[AArch64][GlobalISel] Legalization for bf16 fptosi.sat/fptoui.sat (#209378)
|
2026-07-14 06:27:03 +00:00 |
|
bf16-v8-instructions.ll
|
[LLVM][CodeGen][SVE] Extend NEON->SVE splat imm isel to include min/max operations. (#211228)
|
2026-07-24 11:28:09 +01:00 |
|
bf16-vector-bitcast.ll
|
[LLVM][CodeGen] Remove +bf16 for ARM/AArch64 tests that don't strictly need the feature flag. (#204199)
|
2026-06-23 12:29:11 +01:00 |
|
bf16-vector-shuffle.ll
|
[LLVM][CodeGen] Remove +bf16 for ARM/AArch64 tests that don't strictly need the feature flag. (#204199)
|
2026-06-23 12:29:11 +01:00 |
|
bf16.ll
|
[LLVM][CodeGen] Remove +bf16 for ARM/AArch64 tests that don't strictly need the feature flag. (#204199)
|
2026-06-23 12:29:11 +01:00 |
|
bf16_fast_math.ll
|
|
|
|
bfis-in-loop.ll
|
|
|
|
bics.ll
|
|
|
|
big-callframe.ll
|
|
|
|
bisect-post-ra-machine-sink.mir
|
|
|
|
bit-test.ll
|
|
|
|
bitcast-extend.ll
|
[AArch64][GlobalISel] Fold buildvector of bitcast (#141553)
|
2026-05-16 16:30:15 +01:00 |
|
bitcast-promote-widen.ll
|
|
|
|
bitcast-v2i8.ll
|
|
|
|
bitcast.ll
|
[AArch64][GlobalISel] Fold buildvector of bitcast (#141553)
|
2026-05-16 16:30:15 +01:00 |
|
bitcast_truncstore.ll
|
|
|
|
bitcnt-i256.ll
|
|
|
|
bitfield-extract.ll
|
|
|
|
bitfield-insert-0.ll
|
|
|
|
bitfield-insert.ll
|
[DAG] Fold any-extend(and(trunc(x), C)) -> and(x, C) (#200052)
|
2026-06-03 17:48:40 +02:00 |
|
bitfield.ll
|
|
|
|
bitreverse.ll
|
[AArch64][Isel] For fixed length vectors use sve for bitreverse when available (#196025)
|
2026-05-12 08:19:56 +05:30 |
|
block-placement-optimize-branches.ll
|
|
|
|
blockaddress.ll
|
|
|
|
blr-bti-preserves-operands.mir
|
|
|
|
bool-ext-inc.ll
|
[AArch64][GlobalISel] Normalize and cleanup test check lines. NFC (#195234)
|
2026-05-01 09:27:32 +01:00 |
|
bool-loads.ll
|
|
|
|
bool-vector-bitcast-compare.ll
|
[AArch64] Optimize lowering of i1 vector reduction (#187912)
|
2026-04-28 19:58:44 +01:00 |
|
br-cond-merging-cbz-tbnz.ll
|
[AArch64][ISel] Enable profile-aware branch condition merging (#201486)
|
2026-06-24 16:22:51 +01:00 |
|
br-cond-merging-fccmp.ll
|
[AArch64][ISel] Enable profile-aware branch condition merging (#201486)
|
2026-06-24 16:22:51 +01:00 |
|
br-cond-merging-loaded-operands.ll
|
[AArch64] Don't merge branch conditions that both compare memory loads (#206504)
|
2026-07-09 13:43:38 +01:00 |
|
br-cond-not-merge.ll
|
[AArch64][ISel] Enable profile-aware branch condition merging (#201486)
|
2026-06-24 16:22:51 +01:00 |
|
br-to-eh-lpad.ll
|
|
|
|
br-undef-cond.ll
|
|
|
|
branch-cond-split-fcmp.ll
|
[AArch64] Fold CSET + BR_CC into a conditional branch (#207398)
|
2026-07-14 08:07:35 +01:00 |
|
branch-folder-hoist-disable.mir
|
[CodeGen][BranchFolding] Add options to control common hoisting and block reordering (#205704)
|
2026-07-09 19:51:57 -07:00 |
|
branch-folder-merge-mmos.ll
|
|
|
|
branch-folder-oneinst.mir
|
|
|
|
branch-folder-reorder-disable.mir
|
[CodeGen][BranchFolding] Add options to control common hoisting and block reordering (#205704)
|
2026-07-09 19:51:57 -07:00 |
|
branch-on-bool.ll
|
|
|
|
branch-relax-alignment.ll
|
|
|
|
branch-relax-asm.ll
|
|
|
|
branch-relax-b.ll
|
|
|
|
branch-relax-bcc.ll
|
|
|
|
branch-relax-block-size.mir
|
|
|
|
branch-relax-cbz.ll
|
|
|
|
branch-relax-cross-section.mir
|
[AArch64][CodeGen] Fix trampoline basic block offset (#202716)
|
2026-07-21 19:18:58 +02:00 |
|
branch-relax-tbz.mir
|
[AArch64][CodeGen] Fix trampoline basic block offset (#202716)
|
2026-07-21 19:18:58 +02:00 |
|
branch-relax-xray.ll
|
|
|
|
branch-target-enforcement-indirect-calls.ll
|
|
|
|
breg.ll
|
|
|
|
bsl.ll
|
[LLVM][CodeGen][SVE] Extend NEON->SVE splat imm isel to cover 64-bit vectors. (#209833)
|
2026-07-22 11:01:27 +01:00 |
|
bsp_implicit_ops.mir
|
|
|
|
bswap-known-bits.ll
|
[DAG] Fold any-extend(and(trunc(x), C)) -> and(x, C) (#200052)
|
2026-06-03 17:48:40 +02:00 |
|
bswap.ll
|
[AArch64][GlobalISel] Lower unmerge to extract_subvector (#195046)
|
2026-05-05 17:39:07 +01:00 |
|
bti-branch-relaxation.ll
|
|
|
|
bti-ehpad.ll
|
|
|
|
bti-linkage.ll
|
|
|
|
build-attributes-all.ll
|
|
|
|
build-attributes-bti.ll
|
|
|
|
build-attributes-gcs.ll
|
|
|
|
build-attributes-pac.ll
|
|
|
|
build-attributes-pauthabi.ll
|
[PAC][clang] Fix ptrauth module flags behavior (#204226)
|
2026-07-13 19:07:24 +00:00 |
|
build-one-lane.ll
|
|
|
|
build-pair-isel.ll
|
|
|
|
build-vector-dup-simd-nnan.ll
|
|
|
|
build-vector-dup-simd.ll
|
|
|
|
build-vector-extract.ll
|
[AArch64] Use EXT for byte shuffles with leading zeros (#193466)
|
2026-05-08 15:25:55 +05:30 |
|
build-vector-reconstructshuffle.ll
|
[AArch64] Fix ReconstructShuffle for known vscale>1 (#205099)
|
2026-07-03 15:05:41 +01:00 |
|
build-vector-to-extract-subvec-crash.ll
|
|
|
|
build-vector-two-dup.ll
|
[AArch64][GlobalISel] Add more shuffle test coverage. NFC (#207907)
|
2026-07-07 07:45:00 +01:00 |
|
byval-type.ll
|
|
|
|
call-rv-marker.ll
|
[AArch64][GlobalISel] Normalize and cleanup test check lines. NFC (#195234)
|
2026-05-01 09:27:32 +01:00 |
|
callbr-asm-label-bti.ll
|
|
|
|
callbr-asm-label.ll
|
|
|
|
callbr-asm-obj-file.ll
|
|
|
|
callbr-asm-outputs-indirect-isel.ll
|
[AMDGPU][NFC] Update MIR tests to use symbolic INLINEASM operands (#186839)
|
2026-04-17 12:23:56 +01:00 |
|
callee-save.ll
|
|
|
|
calleetypeid-directcall-mismatched.ll
|
[clang][llvm]Uncorrelate CFI and Callgraph related type metadata annotations (#204266)
|
2026-06-30 18:47:04 -07:00 |
|
callsite-emit-calleetypeid-tailcall.ll
|
[clang][llvm]Uncorrelate CFI and Callgraph related type metadata annotations (#204266)
|
2026-06-30 18:47:04 -07:00 |
|
callsite-emit-calleetypeid.ll
|
[clang][llvm]Uncorrelate CFI and Callgraph related type metadata annotations (#204266)
|
2026-06-30 18:47:04 -07:00 |
|
cbz_wzr.mir
|
[NewPM] Port AArch64RedundantCondBranch to the new pass manager (#190897)
|
2026-04-17 16:45:08 -07:00 |
|
ccmp-cse.ll
|
|
|
|
ccmp-look-through-copy.mir
|
[NewPM] Adds a port for AArch64ConditionalComparesPass (#192755)
|
2026-04-18 18:59:11 +00:00 |
|
ccmp-successor-probs.mir
|
[NewPM] Adds a port for AArch64ConditionalComparesPass (#192755)
|
2026-04-18 18:59:11 +00:00 |
|
cfguard-arm64ec.ll
|
|
|
|
cfguard-checks.ll
|
Revert "[AArch64][GlobalISel] Do not run the Localizer at -O0 (#177359)" (#193781)
|
2026-04-23 16:38:44 +01:00 |
|
cfguard-module-flag.ll
|
[win] Add a flag to control the Control Flow Guard mechanism on Windows (#176276)
|
2026-04-14 08:56:47 -07:00 |
|
cfi-fixup-multi-block-prologue.mir
|
[CodeGen][NewPM] Port cfi-fixup to new pass manager (#203692)
|
2026-06-15 13:58:21 +08:00 |
|
cfi-fixup-multi-section.mir
|
[CodeGen][NewPM] Port cfi-fixup to new pass manager (#203692)
|
2026-06-15 13:58:21 +08:00 |
|
cfi-fixup.ll
|
|
|
|
cfi-fixup.mir
|
[CodeGen][NewPM] Port cfi-fixup to new pass manager (#203692)
|
2026-06-15 13:58:21 +08:00 |
|
cfi-sync-async.ll
|
|
|
|
cfi_restore.mir
|
[CodeGen] Rename prologpeilog to prolog-epilog (#207870)
|
2026-07-06 18:26:05 -07:00 |
|
cfinv-def-nzcv.mir
|
|
|
|
cfinv-use-nzcv.mir
|
|
|
|
cgdata-global-hash.ll
|
|
|
|
cgdata-merge-crash.ll
|
|
|
|
cgdata-merge-gvar-nsconst.ll
|
|
|
|
cgdata-merge-gvar-objc.ll
|
|
|
|
cgdata-merge-gvar-string.ll
|
|
|
|
cgdata-merge-local.ll
|
|
|
|
cgdata-merge-no-params.ll
|
|
|
|
cgdata-merge-preserve-entry-count.ll
|
|
|
|
cgdata-no-merge-attached-call-garget.ll
|
|
|
|
cgdata-no-merge-unnamed.ll
|
|
|
|
cgdata-outline-gvar.ll
|
|
|
|
cgdata-outlined-name.ll
|
|
|
|
cgdata-read-double-outline.ll
|
|
|
|
cgdata-read-lto-outline.ll
|
|
|
|
cgdata-read-priority.ll
|
|
|
|
cgdata-read-single-outline-suffix.ll
|
|
|
|
cgdata-read-single-outline.ll
|
|
|
|
cgdata-write-outline.ll
|
|
|
|
cgp-trivial-phi-node.ll
|
|
|
|
cgp-usubo.ll
|
[DAGCombiner] Reconstruct borrow chain from icmp pattern for USUBO_CARRY (#193707)
|
2026-04-30 15:04:52 +02:00 |
|
cheap-as-a-move.ll
|
|
|
|
check-sign-bit-before-extension.ll
|
|
|
|
chkstk.ll
|
[CodeGen] Rename prologpeilog to prolog-epilog (#207870)
|
2026-07-06 18:26:05 -07:00 |
|
clear-dead-implicit-def-impdef.ll
|
|
|
|
clear-dead-implicit-def-impdef.mir
|
|
|
|
clmul-fixed.ll
|
[AArch64] Mark FIXED_REGS register class as non-allocatable (#212250)
|
2026-07-29 12:06:05 +01:00 |
|
clmul-scalable.ll
|
[ISel] Improve clmul fallback implementation for i32 and i64 (#203727)
|
2026-06-18 17:52:38 +00:00 |
|
clmul.ll
|
[AArch64] Mark FIXED_REGS register class as non-allocatable (#212250)
|
2026-07-29 12:06:05 +01:00 |
|
cls.ll
|
|
|
|
cluster-frame-index.mir
|
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|
cmp-bool.ll
|
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|
cmp-chains.ll
|
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|
cmp-const-max.ll
|
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|
cmp-frameindex.ll
|
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|
cmp-i256.ll
|
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|
cmp-select-sign.ll
|
|
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|
cmp-to-cmn.ll
|
[AArch64][GlobalISel] Port shouldBeAdjustedToZero to GlobalISel (#195941)
|
2026-06-04 05:18:17 +00:00 |
|
cmpbr-branch-relaxation.mir
|
|
|
|
cmpbr-early-ifcvt.mir
|
|
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|
cmpbr-reg-imm-at-bounds.ll
|
|
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|
cmpbr-reg-imm.ll
|
|
|
|
cmpbr-reg-reg.ll
|
|
|
|
cmpbr-zext-sext.ll
|
|
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|
cmpwithshort.ll
|
|
|
|
cmpxchg-idioms.ll
|
|
|
|
cmpxchg-lse-even-regs.ll
|
|
|
|
cmpxchg-O0.ll
|
|
|
|
cmtst-neg-and-one.ll
|
[AArch64] Match vector neg(and X, 1) as CMTST (#194833)
|
2026-05-06 14:28:17 +01:00 |
|
coalescer-drop-subreg-to-reg-imm-ops.mir
|
|
|
|
code-layout-opt.ll
|
[AArch64] New pass for code layout optimizations. (#184434)
|
2026-05-10 23:23:45 +03:00 |
|
code-model-large.ll
|
|
|
|
code-model-tiny-abs.ll
|
|
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combine-and-like.ll
|
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|
combine-andintoload.ll
|
|
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|
combine-comparisons-by-cse.ll
|
[AArch64] Select CMP WZR, reg, shift #amount (#197424)
|
2026-05-21 09:19:52 +02:00 |
|
combine-max-min.ll
|
[GIsel] import min/max rewrites (#188267)
|
2026-06-11 17:58:49 +01:00 |
|
combine-mul.ll
|
|
|
|
combine-sdiv.ll
|
|
|
|
combine-storetomstore.ll
|
[LLVM][CodeGen][SVE] Extend NEON->SVE splat imm isel to cover 64-bit vectors. (#209833)
|
2026-07-22 11:01:27 +01:00 |
|
combine_andor_with_cmps.ll
|
|
|
|
commandline-metadata.ll
|
|
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|
compare-branch.ll
|
|
|
|
compiler-ident.ll
|
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|
complex-copy-noneon.ll
|
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|
complex-deinterleaving-add-mull-fixed-contract.ll
|
|
|
|
complex-deinterleaving-add-mull-fixed-fast.ll
|
|
|
|
complex-deinterleaving-add-mull-scalable-contract.ll
|
[AArch64][SVE] Add more MOVPRFX pseudos for SVE immediate instructions. (#192491)
|
2026-04-20 14:55:54 +01:00 |
|
complex-deinterleaving-add-mull-scalable-fast.ll
|
|
|
|
complex-deinterleaving-cdot.ll
|
|
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|
complex-deinterleaving-crash.ll
|
|
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|
complex-deinterleaving-f16-add-scalable.ll
|
|
|
|
complex-deinterleaving-f16-add.ll
|
|
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|
complex-deinterleaving-f16-mul-scalable.ll
|
|
|
|
complex-deinterleaving-f16-mul.ll
|
|
|
|
complex-deinterleaving-f32-add-scalable.ll
|
|
|
|
complex-deinterleaving-f32-add.ll
|
[LLVM][ComplexDeinterleaving] Update identifyDeinterleave to support all forms of zero. (#200400)
|
2026-06-02 13:38:30 +01:00 |
|
complex-deinterleaving-f32-mul-scalable.ll
|
|
|
|
complex-deinterleaving-f32-mul.ll
|
|
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|
complex-deinterleaving-f64-add-scalable.ll
|
|
|
|
complex-deinterleaving-f64-add.ll
|
|
|
|
complex-deinterleaving-f64-mul-scalable.ll
|
|
|
|
complex-deinterleaving-f64-mul.ll
|
|
|
|
complex-deinterleaving-i8-add-scalable.ll
|
|
|
|
complex-deinterleaving-i16-add-scalable.ll
|
|
|
|
complex-deinterleaving-i16-mul-scalable.ll
|
|
|
|
complex-deinterleaving-i32-add-scalable.ll
|
|
|
|
complex-deinterleaving-i32-mul-scalable.ll
|
|
|
|
complex-deinterleaving-i64-add-scalable.ll
|
|
|
|
complex-deinterleaving-i64-mul-scalable.ll
|
|
|
|
complex-deinterleaving-mixed-cases.ll
|
[AArch64] Use dup (lane mov) over ext for high-half extract (#195010)
|
2026-05-11 07:31:59 +00:00 |
|
complex-deinterleaving-multiuses.ll
|
[AArch64] Use dup (lane mov) over ext for high-half extract (#195010)
|
2026-05-11 07:31:59 +00:00 |
|
complex-deinterleaving-opt-crash-178671.ll
|
|
|
|
complex-deinterleaving-opt-crash.ll
|
|
|
|
complex-deinterleaving-reassoc-duplicates.ll
|
[ComplexDeinterleaving] Preserve duplicate reassoc addends in identifyReassocNodes (#205578)
|
2026-06-25 16:31:45 +01:00 |
|
complex-deinterleaving-reductions-predicated-scalable.ll
|
[LV][NFC] Rename PreferPredicateOverEpilogue to TailFoldingPolicy (#191803)
|
2026-04-20 16:29:51 +01:00 |
|
complex-deinterleaving-reductions-scalable.ll
|
|
|
|
complex-deinterleaving-reductions.ll
|
|
|
|
complex-deinterleaving-splat-scalable.ll
|
[LLVM][Constants] Remove the option to disable vector ConstantFP support. (#197427)
|
2026-05-14 11:45:37 +01:00 |
|
complex-deinterleaving-splat.ll
|
|
|
|
complex-deinterleaving-symmetric-fixed.ll
|
|
|
|
complex-deinterleaving-symmetric-scalable.ll
|
|
|
|
complex-deinterleaving-uniform-cases.ll
|
[AArch64] Keep MMO when converting gather lane to LDRSui. (#197522)
|
2026-05-14 07:59:48 +01:00 |
|
complex-deinterleaving-unrolled-cdot.ll
|
|
|
|
complex-fp-to-int.ll
|
|
|
|
complex-int-to-fp.ll
|
|
|
|
compute-call-frame-size-unreachable-pass.ll
|
|
|
|
concat-vector-add-combine.ll
|
|
|
|
concat-vector.ll
|
[AArch64] Keep MMO when converting gather lane to LDRSui. (#197522)
|
2026-05-14 07:59:48 +01:00 |
|
concat_vector-scalar-combine.ll
|
[AArch64] Regenerate concat_vector-scalar-combine.ll. NFC (#196370)
|
2026-05-07 18:05:31 +01:00 |
|
concat_vector-truncate-combine.ll
|
|
|
|
concat_vector-truncated-scalar-combine.ll
|
|
|
|
concatbinop.ll
|
|
|
|
cond-br-tuning-instr-ref.mir
|
|
|
|
cond-br-tuning.ll
|
|
|
|
cond-sel-value-prop.ll
|
|
|
|
cond-sel.ll
|
|
|
|
consecutive-stores-of-faddv.ll
|
|
|
|
const-isel.ll
|
|
|
|
const-shift-of-constmasked.ll
|
|
|
|
const-vector-big-endian.ll
|
|
|
|
constant-pool-partition.ll
|
|
|
|
consthoist-gep.ll
|
|
|
|
convert-highly-predictable-select-to-branch.ll
|
|
|
|
convertphitype.ll
|
[AsmWriter] Change the output syntax of floating-point literals. (#190649)
|
2026-05-07 13:16:14 -04:00 |
|
copyprop.ll
|
|
|
|
copyprop.mir
|
|
|
|
cpa-globalisel.ll
|
[GISel] Disable opt_brcond_by_inverting_cond combine at O0 (#193417)
|
2026-04-24 09:11:23 +01:00 |
|
cpa-selectiondag.ll
|
|
|
|
cpus.ll
|
[AArch64] Add initial support for -mcpu=rigel. (#208017)
|
2026-07-09 14:18:25 +01:00 |
|
csel-andor-onebit.ll
|
|
|
|
csel-cmp-cse.ll
|
|
|
|
csel-subs-swapped.ll
|
|
|
|
csel-zero-float.ll
|
|
|
|
csinc-cmp-removal.mir
|
|
|
|
csr-copy-hint.mir
|
|
|
|
csr-split.ll
|
|
|
|
ctlo.ll
|
|
|
|
ctlz.ll
|
[AArch64][GlobalISel] Fold buildvector of bitcast (#141553)
|
2026-05-16 16:30:15 +01:00 |
|
ctlz_zero_undef.ll
|
|
|
|
ctpop-nonean.ll
|
|
|
|
ctpop.ll
|
[AArch64][GlobalISel] Fold buildvector of bitcast (#141553)
|
2026-05-16 16:30:15 +01:00 |
|
cttz-of-bool-vector-bitcast.ll
|
[AArch64] Lower cttz(bitcast <Nxi1> to iN) with shrn-based compressed movemask (#199081)
|
2026-07-02 18:14:02 -07:00 |
|
cttz.ll
|
[AArch64][GlobalISel] Fold buildvector of bitcast (#141553)
|
2026-05-16 16:30:15 +01:00 |
|
custom-sections.ll
|
|
|
|
cvt-fp-int-fp.ll
|
|
|
|
cxx-tlscc.ll
|
|
|
|
dag-combine-concat-vectors.ll
|
[AArch64][CodeGen] Split wide active lane mask into smaller masks if preferred (#202909)
|
2026-07-10 14:39:13 +01:00 |
|
dag-combine-freeze.ll
|
|
|
|
dag-combine-insert-subvector.ll
|
|
|
|
dag-combine-invaraints.ll
|
|
|
|
dag-combine-lifetime-end-store-typesize.ll
|
|
|
|
dag-combine-mul-shl.ll
|
|
|
|
dag-combine-select.ll
|
|
|
|
dag-combine-setcc.ll
|
[AArch64] Use ADDP tree for v16i8 to i16 bitmask extraction (#199812)
|
2026-05-31 10:05:50 +00:00 |
|
dag-combine-trunc-build-vec.ll
|
|
|
|
dag-maps-huge-region.ll
|
[MachineScheduler] Rework dag-maps-huge-region (#200945)
|
2026-06-04 07:31:20 -07:00 |
|
dag-numsignbits.ll
|
|
|
|
dag-ReplaceAllUsesOfValuesWith.ll
|
[DAG] Reassociate (add (add X, Y), X) --> add(add(X, X), Y) (#162242)
|
2026-04-21 12:53:33 +00:00 |
|
DAGCombine_vscale.ll
|
|
|
|
darwinpcs-tail.ll
|
|
|
|
dbg-assign-tag-offset-mix-loc.ll
|
|
|
|
dbg-assign-tag-offset.ll
|
|
|
|
dbg-declare-swift-async.ll
|
|
|
|
dbg-declare-tag-offset.ll
|
|
|
|
dbg-value-swift-async-non-entry-block.ll
|
|
|
|
dbg-value-swift-async.ll
|
|
|
|
dbg-value-tag-offset.ll
|
|
|
|
deactivation-symbols.ll
|
|
|
|
debug-info-sve-dbg-declare.mir
|
[CodeGen] Rename prologpeilog to prolog-epilog (#207870)
|
2026-07-06 18:26:05 -07:00 |
|
debug-info-sve-dbg-value.mir
|
[CodeGen] Rename prologpeilog to prolog-epilog (#207870)
|
2026-07-06 18:26:05 -07:00 |
|
debug-info-sve-pair.mir
|
|
|
|
debugtrap.ll
|
|
|
|
directcond.ll
|
|
|
|
div-i256.ll
|
[AArch64][DAG] Port adde and sube combine to AArch64 (#202227)
|
2026-07-08 10:26:13 +01:00 |
|
div-rem-pair-recomposition-signed.ll
|
|
|
|
div-rem-pair-recomposition-unsigned.ll
|
|
|
|
div_minsize.ll
|
|
|
|
divrem.ll
|
|
|
|
dllexport.ll
|
|
|
|
dllimport.ll
|
|
|
|
dont-shrink-wrap-stack-mayloadorstore.mir
|
|
|
|
dont-take-over-the-world.ll
|
|
|
|
double_reduct.ll
|
[AArch64] Use dup (lane mov) over ext for high-half extract (#195010)
|
2026-05-11 07:31:59 +00:00 |
|
dp-3source.ll
|
[AArch64][GlobalISel] Improve multiplication with multiple registers (#197943)
|
2026-05-16 20:47:25 +02:00 |
|
dp1.ll
|
|
|
|
dp2.ll
|
|
|
|
dso_local_equivalent.ll
|
|
|
|
dump-reserved-cycles.mir
|
|
|
|
dump-schedule-trace.mir
|
|
|
|
dup-ext-load-combine.ll
|
|
|
|
dup.ll
|
[AArch64] Fix DUP-of-extload combine to ignore chain uses (#201351)
|
2026-06-04 09:43:53 +03:00 |
|
duplane-index-patfrags.ll
|
|
|
|
dwarf-cfi.ll
|
|
|
|
dwarf-eh-prepare-dbg.ll
|
|
|
|
dynamic-regmask-preserve-none.ll
|
|
|
|
early-ifcvt-likely-predictable.mir
|
|
|
|
early-ifcvt-load-to-cond-br.mir
|
|
|
|
early-ifcvt-on-double-killed-reg.mir
|
|
|
|
early-ifcvt-regclass-mismatch.mir
|
|
|
|
early-ifcvt-remarks.mir
|
|
|
|
early-ifcvt-same-value.mir
|
|
|
|
eh_recoverfp.ll
|
|
|
|
ehcontguard.ll
|
|
|
|
elf-globals-pic.ll
|
[PAC][clang] Fix ptrauth module flags behavior (#204226)
|
2026-07-13 19:07:24 +00:00 |
|
elf-globals-static.ll
|
|
|
|
elf-preemption.ll
|
|
|
|
elim-dead-mi.mir
|
|
|
|
eliminate-trunc.ll
|
|
|
|
emit-prologue-clobber-verification.mir
|
[CodeGen] Rename prologpeilog to prolog-epilog (#207870)
|
2026-07-06 18:26:05 -07:00 |
|
emit_fneg_with_non_register_operand.mir
|
[AMDGPU][NFC] Update MIR tests to use symbolic INLINEASM operands (#186839)
|
2026-04-17 12:23:56 +01:00 |
|
emutls.ll
|
|
|
|
emutls_alias.ll
|
|
|
|
emutls_generic.ll
|
|
|
|
eon.ll
|
|
|
|
eor3.ll
|
|
|
|
exception-handling-windows-elf.ll
|
|
|
|
execute-only-empty.ll
|
|
|
|
execute-only-section.ll
|
|
|
|
exp10-libcall-names.ll
|
|
|
|
expand-blr-rvmarker-pseudo.mir
|
|
|
|
expand-constructive-zzi.mir
|
|
|
|
expand-form-transposed-tuple.mir
|
[AArch64] Expand FORM_TRANSPOSED_REG_TUPLE to copies before regalloc (#207205)
|
2026-07-09 09:01:56 +01:00 |
|
expand-load-got-pseudo.mir
|
|
|
|
expand-movi-renamable.mir
|
|
|
|
expand-select.ll
|
|
|
|
expand-sme-pseudos.mir
|
Revert "[AArch64] Fix definition of system register move instructions" (#201137)
|
2026-06-02 16:44:37 +01:00 |
|
expand-subs-pseudo.mir
|
|
|
|
expand-vector-rot.ll
|
[LegalizeTypes] Improve promotion of variable rotates. (#208610)
|
2026-07-13 11:09:40 -07:00 |
|
ext-narrow-index.ll
|
[AArch64] Optimize vector slide shuffles with zeros to use shift instructions (#185170)
|
2026-06-12 16:55:08 +01:00 |
|
extbinopload.ll
|
|
|
|
extend-bool-vector-load.ll
|
[AArch64] Lower extends of boolean vector loads via scalar load (#203394)
|
2026-06-22 08:06:46 +01:00 |
|
extend_inreg_of_concat_subvectors.ll
|
[AArch64][GlobalISel] Fold G_SHUFFLE to single-element TBL with zero elements. (#200938)
|
2026-07-11 08:12:13 +01:00 |
|
extend_vecreduce_add.ll
|
|
|
|
extern-weak.ll
|
[PAC][clang] Fix ptrauth module flags behavior (#204226)
|
2026-07-13 19:07:24 +00:00 |
|
extra-callee-save.mir
|
[CodeGen] Rename prologpeilog to prolog-epilog (#207870)
|
2026-07-06 18:26:05 -07:00 |
|
extract-bits.ll
|
|
|
|
extract-insert.ll
|
|
|
|
extract-lowbits.ll
|
|
|
|
extract-sext-zext.ll
|
|
|
|
extract-subvec-combine.ll
|
[AArch64] Use dup (lane mov) over ext for high-half extract (#195010)
|
2026-05-11 07:31:59 +00:00 |
|
extract-vector-cmp.ll
|
[AArch64] Fold any/sign-extend of CSET. (#207414)
|
2026-07-08 10:34:12 +01:00 |
|
extract-vector-elt-sve.ll
|
[AArch64] Hint regalloc to choose distinct predicate for MATCH/CMP (#190139)
|
2026-04-14 09:40:50 +01:00 |
|
extract-vector-elt.ll
|
[AArch64][GlobalISel] Add legalisation for G_INSERT_SUBVECTOR (#205349)
|
2026-07-02 08:50:30 +01:00 |
|
extract.ll
|
|
|
|
extractvector-of-load.mir
|
|
|
|
extractvector-oob-load.mir
|
|
|
|
f16-imm.ll
|
|
|
|
f16-instructions.ll
|
[AArch64] Lower i16/f16 bitcast via vector operations. (#196341)
|
2026-05-15 15:17:48 +00:00 |
|
f16-neon-intrinsics.ll
|
|
|
|
f16f32dot-fixed-length-fdot.ll
|
[AArch64] Use dup (lane mov) over ext for high-half extract (#195010)
|
2026-05-11 07:31:59 +00:00 |
|
fabd-no-neon.ll
|
|
|
|
fabs-combine.ll
|
|
|
|
fabs-fp128.ll
|
Revert "[AArch64] Run cleanup one final time after peephole (#199711)" (#205633)
|
2026-06-24 19:28:07 +01:00 |
|
fabs.ll
|
[AArch64] Fixup f16->bf16 in intrinsic defs. NFC (#200244)
|
2026-05-28 19:51:23 +01:00 |
|
fadd-combines.ll
|
[AArch64][GlobalISel] Match G_DUP with undef elements (#195237)
|
2026-05-05 08:33:22 +01:00 |
|
faddp-half.ll
|
|
|
|
faddp.ll
|
[AArch64] Extend testing of add-like-ors. NFC (#193071)
|
2026-04-20 21:11:08 +01:00 |
|
faddsub.ll
|
[AArch64] Use dup (lane mov) over ext for high-half extract (#195010)
|
2026-05-11 07:31:59 +00:00 |
|
faddv-fp16.ll
|
|
|
|
faddv.ll
|
|
|
|
falkor-hwpf-fix.ll
|
|
|
|
falkor-hwpf-fix.mir
|
|
|
|
falkor-hwpf.ll
|
|
|
|
fast-isel-address-extends.ll
|
|
|
|
fast-isel-addressing-modes.ll
|
|
|
|
fast-isel-assume.ll
|
|
|
|
fast-isel-atomic-fallback.ll
|
[RegAllocFast] Eliminate dead copies (#196056)
|
2026-05-15 16:47:07 +01:00 |
|
fast-isel-atomic.ll
|
|
|
|
fast-isel-branch-cond-mask.ll
|
|
|
|
fast-isel-branch-cond-split.ll
|
[CodeGenPrepare] Use recomputed split-branch weights. (#199822)
|
2026-05-27 21:51:12 +00:00 |
|
fast-isel-branch_weights.ll
|
|
|
|
fast-isel-call-return.ll
|
|
|
|
fast-isel-call-struct-return-fallback.ll
|
|
|
|
fast-isel-call-struct-return.ll
|
|
|
|
fast-isel-cbz.ll
|
|
|
|
fast-isel-cmp-branch.ll
|
|
|
|
fast-isel-cmp-vec.ll
|
|
|
|
fast-isel-cmpxchg.ll
|
|
|
|
fast-isel-const-float.ll
|
[AArch64][GlobalISel] Normalize and cleanup test check lines. NFC (#195234)
|
2026-05-01 09:27:32 +01:00 |
|
fast-isel-dbg.ll
|
[DebugInfo] Verify DISubprogram has a type (#194556)
|
2026-05-04 11:32:19 +01:00 |
|
fast-isel-erase.ll
|
|
|
|
fast-isel-folded-shift.ll
|
|
|
|
fast-isel-folding.ll
|
|
|
|
fast-isel-fpimm.ll
|
|
|
|
fast-isel-gep.ll
|
|
|
|
fast-isel-int-ext.ll
|
[AArch64][FastISel] Update arm64-fast-isel-int-ext.ll check lines (NFC) (#207996)
|
2026-07-09 09:17:22 +01:00 |
|
fast-isel-int-ext2.ll
|
|
|
|
fast-isel-int-ext3.ll
|
|
|
|
fast-isel-int-ext4.ll
|
|
|
|
fast-isel-int-ext5.ll
|
|
|
|
fast-isel-intrinsic.ll
|
|
|
|
fast-isel-logic-op.ll
|
|
|
|
fast-isel-memcpy.ll
|
|
|
|
fast-isel-mul.ll
|
|
|
|
fast-isel-runtime-libcall.ll
|
|
|
|
fast-isel-sdiv.ll
|
|
|
|
fast-isel-select.ll
|
|
|
|
fast-isel-shift.ll
|
|
|
|
fast-isel-sp-adjust.ll
|
|
|
|
fast-isel-sqrt.ll
|
|
|
|
fast-isel-switch-phi.ll
|
|
|
|
fast-isel-tail-call.ll
|
|
|
|
fast-isel-tbz.ll
|
|
|
|
fast-isel-trunc.ll
|
|
|
|
fast-isel-vector-arithmetic.ll
|
|
|
|
fast-isel-vret.ll
|
|
|
|
fast-regalloc-empty-bb-with-liveins.mir
|
|
|
|
fastcc-reserved.ll
|
|
|
|
fastcc.ll
|
|
|
|
fastisel-debugvalue-undef.ll
|
|
|
|
fcmp-fp128.ll
|
[AArch64][GlobalISel] Normalize and cleanup some test checks. NFC (#195016)
|
2026-04-30 07:35:34 +01:00 |
|
fcmp.ll
|
[AArch64] Fold any/sign-extend of CSET. (#207414)
|
2026-07-08 10:34:12 +01:00 |
|
fcopysign-noneon.ll
|
|
|
|
fcopysign.ll
|
[AArch64] Use dup (lane mov) over ext for high-half extract (#195010)
|
2026-05-11 07:31:59 +00:00 |
|
fcsel-zero.ll
|
|
|
|
fcvt-fixed.ll
|
|
|
|
fcvt-i256.ll
|
[AArch64][ISel] Enable profile-aware branch condition merging (#201486)
|
2026-06-24 16:22:51 +01:00 |
|
fcvt-int.ll
|
|
|
|
fcvt.ll
|
[AArch64] Use dup (lane mov) over ext for high-half extract (#195010)
|
2026-05-11 07:31:59 +00:00 |
|
fcvt_combine.ll
|
[AArch64][GlobalISel] Match G_DUP with undef elements (#195237)
|
2026-05-05 08:33:22 +01:00 |
|
fdiv-combine.ll
|
|
|
|
fdiv-const.ll
|
|
|
|
fdiv.ll
|
[AArch64] Use dup (lane mov) over ext for high-half extract (#195010)
|
2026-05-11 07:31:59 +00:00 |
|
fence-singlethread.ll
|
|
|
|
fexplog.ll
|
|
|
|
fixed-expanding-load.ll
|
[AArch64] Lower masked.expandload intrinsic using SVE2p2/SME2p2 EXPAND (#190999)
|
2026-04-20 11:06:34 +01:00 |
|
fixed-length-bf16-arith.ll
|
[AArch64] Fixup f16->bf16 in intrinsic defs. NFC (#200244)
|
2026-05-28 19:51:23 +01:00 |
|
fixed-point-conv-vec-pat.ll
|
|
|
|
fixed-vector-deinterleave.ll
|
[AArch64] Add combine for interleave deinterleave (#208414)
|
2026-07-20 09:39:13 +01:00 |
|
fixed-vector-interleave.ll
|
[AArch64] Add combine for interleave deinterleave (#208414)
|
2026-07-20 09:39:13 +01:00 |
|
fixed_masked_deinterleaved_loads.ll
|
[AArch64] Use ADDP tree for v16i8 to i16 bitmask extraction (#199812)
|
2026-05-31 10:05:50 +00:00 |
|
fixed_masked_interleaved_stores.ll
|
[AArch64] Use ADDP tree for v16i8 to i16 bitmask extraction (#199812)
|
2026-05-31 10:05:50 +00:00 |
|
fjcvtzs.ll
|
|
|
|
fjcvtzs.mir
|
|
|
|
flags-multiuse.ll
|
|
|
|
float-conv-elim.ll
|
|
|
|
floatdp_1source.ll
|
|
|
|
floatdp_2source.ll
|
|
|
|
fma-fneg-combine.ll
|
|
|
|
fmaximum-legalization.ll
|
[CodeGen] Fix legalization of minimum/maximum (#206097)
|
2026-06-29 12:16:26 +02:00 |
|
fmaximumnum-fminimumnum-select.ll
|
[AArch64] Fix swapped operands in tryFoldCselToFMaxMin (#203230)
|
2026-06-17 21:35:00 +01:00 |
|
fminimummaximum.ll
|
[AArch64] Use dup (lane mov) over ext for high-half extract (#195010)
|
2026-05-11 07:31:59 +00:00 |
|
fminmax.ll
|
[AArch64] Use dup (lane mov) over ext for high-half extract (#195010)
|
2026-05-11 07:31:59 +00:00 |
|
fminp-fmaxp.ll
|
|
|
|
fmla.ll
|
[AArch64] Use dup (lane mov) over ext for high-half extract (#195010)
|
2026-05-11 07:31:59 +00:00 |
|
fmlal-loreg.ll
|
[AArch64] Remove assembler-only register classes (#211527)
|
2026-07-30 08:43:53 +01:00 |
|
fmov-imm-licm.ll
|
|
|
|
fmul.ll
|
[AArch64] Use dup (lane mov) over ext for high-half extract (#195010)
|
2026-05-11 07:31:59 +00:00 |
|
fneg.ll
|
[AArch64][GlobalISel] Add BF16 fabs and fneg (#198655)
|
2026-05-27 17:55:51 +01:00 |
|
fnmul.ll
|
|
|
|
fold-constants.ll
|
|
|
|
fold-csel-cttz-and.ll
|
|
|
|
fold-global-offsets.ll
|
[AArch64][GlobalISel] Normalize and cleanup test check lines. NFC (#195234)
|
2026-05-01 09:27:32 +01:00 |
|
fold-int-pow2-with-fmul-or-fdiv.ll
|
|
|
|
fold-sext-in-reg-predicate-fixed-length.ll
|
[DAGCombiner] Fold extract_vector(get_active_lane_mask(),0) to get_active_lane_mask (#208978)
|
2026-07-14 18:11:40 +00:00 |
|
force-enable-intervals.mir
|
|
|
|
fp-cond-sel.ll
|
|
|
|
fp-const-fold.ll
|
|
|
|
fp-conversion-to-tbl.ll
|
[AArch64] Optimize vector slide shuffles with zeros to use shift instructions (#185170)
|
2026-06-12 16:55:08 +01:00 |
|
fp-dp3.ll
|
|
|
|
fp-fcanonicalize.ll
|
|
|
|
fp-intrinsics-fp16.ll
|
|
|
|
fp-intrinsics-vector.ll
|
|
|
|
fp-intrinsics.ll
|
|
|
|
fp-maximumnum-minimumnum.ll
|
[AArch64] Keep MMO when converting gather lane to LDRSui. (#197522)
|
2026-05-14 07:59:48 +01:00 |
|
fp-to-int-to-fp.ll
|
[SelectionDAG] Remove the remaining NoSignedZerosFPMath use (#201535)
|
2026-06-05 11:48:05 +00:00 |
|
fp-veclib-expansion.ll
|
|
|
|
fp8-neon-fdot.ll
|
|
|
|
fp8-neon-fmla.ll
|
|
|
|
fp8-sme2-cvtn.ll
|
|
|
|
fp8-sve-cvt-cvtlt.ll
|
|
|
|
fp8-sve-cvtn.ll
|
|
|
|
fp8-sve-fdot.ll
|
|
|
|
fp8-sve-fmla.ll
|
|
|
|
fp16-fmla.ll
|
|
|
|
fp16-v4-instructions.ll
|
[AArch64][DAG] Use getSetCCResultType in PromoteSETCC (#198320)
|
2026-05-26 17:46:31 +01:00 |
|
fp16-v8-instructions.ll
|
|
|
|
fp16-v16-instructions.ll
|
|
|
|
fp16-vector-bitcast.ll
|
|
|
|
fp16-vector-load-store.ll
|
|
|
|
fp16-vector-nvcast.ll
|
|
|
|
fp16-vector-shuffle.ll
|
[AArch64] Lower i16/f16 bitcast via vector operations. (#196341)
|
2026-05-15 15:17:48 +00:00 |
|
fp16_fast_math.ll
|
|
|
|
fp16_intrinsic_lane.ll
|
|
|
|
fp16_intrinsic_scalar_1op.ll
|
|
|
|
fp16_intrinsic_scalar_2op.ll
|
|
|
|
fp16_intrinsic_scalar_3op.ll
|
|
|
|
fp16_intrinsic_vector_1op.ll
|
|
|
|
fp16_intrinsic_vector_2op.ll
|
|
|
|
fp16_intrinsic_vector_3op.ll
|
|
|
|
fp128-folding.ll
|
|
|
|
fpclamptosat.ll
|
|
|
|
fpclamptosat_vec.ll
|
[AArch64][GlobalISel] Port shouldBeAdjustedToZero to GlobalISel (#195941)
|
2026-06-04 05:18:17 +00:00 |
|
fpconv-vector-op-scalarize.ll
|
|
|
|
fpenv.ll
|
|
|
|
fpext.ll
|
[AArch64] Use dup (lane mov) over ext for high-half extract (#195010)
|
2026-05-11 07:31:59 +00:00 |
|
fpimm.ll
|
|
|
|
fpmode.ll
|
[AArch64][GlobalISel] Normalize and cleanup test check lines. NFC (#195234)
|
2026-05-01 09:27:32 +01:00 |
|
fpow.ll
|
|
|
|
fpowi.ll
|
|
|
|
fprcvt-cvtf.ll
|
|
|
|
fptoi-nan-guard-fold.ll
|
[DAGCombiner] Fold NaN-guard fptosi/fptoui select to saturating variant (#201435)
|
2026-07-21 10:40:53 -04:00 |
|
fptoi.ll
|
[AArch64] Use dup (lane mov) over ext for high-half extract (#195010)
|
2026-05-11 07:31:59 +00:00 |
|
fptosi-sat-scalar.ll
|
[AArch64][GlobalISel] Port shouldBeAdjustedToZero to GlobalISel (#195941)
|
2026-06-04 05:18:17 +00:00 |
|
fptosi-sat-vector.ll
|
[AArch64] Use dup (lane mov) over ext for high-half extract (#195010)
|
2026-05-11 07:31:59 +00:00 |
|
fptosi-strictfp.ll
|
|
|
|
fptoui-sat-scalar.ll
|
|
|
|
fptoui-sat-vector.ll
|
[AArch64] Use dup (lane mov) over ext for high-half extract (#195010)
|
2026-05-11 07:31:59 +00:00 |
|
fptouint-i8-zext.ll
|
|
|
|
fptrunc.ll
|
|
|
|
frameaddr.ll
|
|
|
|
framelayout-fp-csr.ll
|
|
|
|
framelayout-fpr128-csr.ll
|
[AArch64] Stop determineCalleeSaves double counting registers with saved supers (#208521)
|
2026-07-10 15:30:48 +01:00 |
|
framelayout-fpr128-spill.mir
|
[AArch64] Stop determineCalleeSaves double counting registers with saved supers (#208521)
|
2026-07-10 15:30:48 +01:00 |
|
framelayout-frame-record.mir
|
[CodeGen] Rename prologpeilog to prolog-epilog (#207870)
|
2026-07-06 18:26:05 -07:00 |
|
framelayout-offset-immediate-change.mir
|
[CodeGen] Rename prologpeilog to prolog-epilog (#207870)
|
2026-07-06 18:26:05 -07:00 |
|
framelayout-scavengingslot-stack-hazard.mir
|
[CodeGen] Rename prologpeilog to prolog-epilog (#207870)
|
2026-07-06 18:26:05 -07:00 |
|
framelayout-scavengingslot.mir
|
[CodeGen] Rename prologpeilog to prolog-epilog (#207870)
|
2026-07-06 18:26:05 -07:00 |
|
framelayout-split-sve.mir
|
[CodeGen] Rename prologpeilog to prolog-epilog (#207870)
|
2026-07-06 18:26:05 -07:00 |
|
framelayout-sve-basepointer.mir
|
[CodeGen] Rename prologpeilog to prolog-epilog (#207870)
|
2026-07-06 18:26:05 -07:00 |
|
framelayout-sve-calleesaves-fix.mir
|
[CodeGen] Rename prologpeilog to prolog-epilog (#207870)
|
2026-07-06 18:26:05 -07:00 |
|
framelayout-sve-fixed-width-access.mir
|
[CodeGen] Rename prologpeilog to prolog-epilog (#207870)
|
2026-07-06 18:26:05 -07:00 |
|
framelayout-sve-scavengingslot.mir
|
[CodeGen] Rename prologpeilog to prolog-epilog (#207870)
|
2026-07-06 18:26:05 -07:00 |
|
framelayout-sve-win.mir
|
[CodeGen] Rename prologpeilog to prolog-epilog (#207870)
|
2026-07-06 18:26:05 -07:00 |
|
framelayout-sve.mir
|
[CodeGen] Rename prologpeilog to prolog-epilog (#207870)
|
2026-07-06 18:26:05 -07:00 |
|
framelayout-unaligned-fp.ll
|
|
|
|
free-zext.ll
|
|
|
|
freeze-load-zext-copytoreg.ll
|
[SelectionDAG] Look through FREEZE in getCopyToRegs when checking isZExtFree (#195285)
|
2026-05-04 11:16:00 -07:00 |
|
freeze.ll
|
[AArch64] Use dup (lane mov) over ext for high-half extract (#195010)
|
2026-05-11 07:31:59 +00:00 |
|
frem-power2.ll
|
|
|
|
frem.ll
|
|
|
|
frexp-arm64ec.ll
|
|
|
|
frintn.ll
|
|
|
|
fsh-combiner-disabled.ll
|
|
|
|
fsh.ll
|
[LegalizeTypes] Improve promotion of variable rotates. (#208610)
|
2026-07-13 11:09:40 -07:00 |
|
fsincos.ll
|
|
|
|
fsqrt.ll
|
[AArch64] Use dup (lane mov) over ext for high-half extract (#195010)
|
2026-05-11 07:31:59 +00:00 |
|
ftrunc.ll
|
[SelectionDAG] Remove the remaining NoSignedZerosFPMath use (#201535)
|
2026-06-05 11:48:05 +00:00 |
|
func-argpassing.ll
|
|
|
|
func-calls.ll
|
|
|
|
func-sanitizer.ll
|
|
|
|
funclet-local-stack-size.ll
|
|
|
|
funclet-match-add-sub-stack.ll
|
|
|
|
funcptr_cast.ll
|
|
|
|
function-info-noredzone-present.ll
|
|
|
|
function-subtarget-features.ll
|
|
|
|
funnel-shift-rot.ll
|
[LegalizeTypes] Improve promotion of variable rotates. (#208610)
|
2026-07-13 11:09:40 -07:00 |
|
funnel-shift.ll
|
|
|
|
fuse-addr-mode.mir
|
|
|
|
gcs-intrinsics.ll
|
|
|
|
gep-nullptr.ll
|
|
|
|
get-active-lane-mask-extract-nosve.ll
|
[AArch64][CodeGen] Split wide active lane mask into smaller masks if preferred (#202909)
|
2026-07-10 14:39:13 +01:00 |
|
get-active-lane-mask-extract.ll
|
[DAGCombiner] Fold extract_vector(get_active_lane_mask(),0) to get_active_lane_mask (#208978)
|
2026-07-14 18:11:40 +00:00 |
|
get_vector_length.ll
|
|
|
|
ghc-cc.ll
|
|
|
|
global-alignment.ll
|
|
|
|
global-merge-1.ll
|
|
|
|
global-merge-2.ll
|
|
|
|
global-merge-3.ll
|
|
|
|
global-merge-4.ll
|
|
|
|
global-merge-external.ll
|
|
|
|
global-merge-group-by-use.ll
|
|
|
|
global-merge-hidden-minsize.ll
|
|
|
|
global-merge-ignore-single-use-minsize.ll
|
|
|
|
global-merge-ignore-single-use.ll
|
|
|
|
global-merge-minsize.ll
|
|
|
|
global-merge-profile-sections.ll
|
[PGO][AMDGPU] Add uniformity-aware offload profile format and instrumentation (#190708)
|
2026-06-29 08:30:45 -07:00 |
|
global-merge.ll
|
|
|
|
got-abuse.ll
|
[PAC][clang] Fix ptrauth module flags behavior (#204226)
|
2026-07-13 19:07:24 +00:00 |
|
gpr_cttz.ll
|
|
|
|
graalcc.ll
|
|
|
|
hadd-combine-scalar.ll
|
[AArch64] Add more scalar testing for hadd patterns. NFC (#193313)
|
2026-04-21 21:39:03 +01:00 |
|
hadd-combine.ll
|
[AArch64][GlobalISel] Add pre-legalizer combines for AVGFLOOR and AVGCEIL (#192866)
|
2026-05-18 19:25:57 +01:00 |
|
half-precision-signof-no-assert.ll
|
|
|
|
half.ll
|
[AArch64] Lower i16/f16 bitcast via vector operations. (#196341)
|
2026-05-15 15:17:48 +00:00 |
|
hardened-br-jump-table.ll
|
|
|
|
highextractbitcast.ll
|
[AArch64] Use dup (lane mov) over ext for high-half extract (#195010)
|
2026-05-11 07:31:59 +00:00 |
|
hints.ll
|
|
|
|
hoist-and-by-const-from-lshr-in-eqcmp-zero.ll
|
[AArch64][GlobalISel] Match G_DUP with undef elements (#195237)
|
2026-05-05 08:33:22 +01:00 |
|
hoist-and-by-const-from-shl-in-eqcmp-zero.ll
|
[AArch64][GlobalISel] Match G_DUP with undef elements (#195237)
|
2026-05-05 08:33:22 +01:00 |
|
hwasan-check-memaccess-fixedshadow.ll
|
|
|
|
hwasan-check-memaccess.ll
|
|
|
|
hwasan-prefer-fp.ll
|
|
|
|
hwasan-zero-ptr.ll
|
|
|
|
i1-contents.ll
|
|
|
|
i128-align.ll
|
|
|
|
i128-cmp.ll
|
[AArch64] Recombine SETCCCARRY for legalized unsigned compares (#204504)
|
2026-06-24 16:45:18 +01:00 |
|
i128-fast-isel-fallback.ll
|
|
|
|
i128-imm-compare-ccmp.ll
|
[AArch64] optimize lowering for icmp on i128 when RHS is an immediate (#181822)
|
2026-07-06 17:20:43 +01:00 |
|
i128-math.ll
|
|
|
|
i128_volatile_load_store.ll
|
|
|
|
i128_with_overflow.ll
|
|
|
|
i256-math.ll
|
|
|
|
iabs.ll
|
|
|
|
icmp-cst.ll
|
|
|
|
icmp-or-load.ll
|
|
|
|
icmp-shift-opt.ll
|
|
|
|
icmp-ult-eq-fold.ll
|
|
|
|
icmp.ll
|
[SDAG] Freeze condition in select of load fold (#208683)
|
2026-07-10 16:08:02 +02:00 |
|
ifcvt-select.ll
|
|
|
|
ifunc-asm.ll
|
|
|
|
ignore-signed-zero.ll
|
|
|
|
illegal-float-ops.ll
|
|
|
|
illegal-floating-point-vector-compares.ll
|
[AArch64] Optimize lowering of i1 vector reduction (#187912)
|
2026-04-28 19:58:44 +01:00 |
|
ilp32-tlsdesc.ll
|
|
|
|
ilp32-va.ll
|
|
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|
imm-splat-ops.ll
|
[LLVM][CodeGen][SVE] Extend NEON->SVE splat imm isel to include min/max operations. (#211228)
|
2026-07-24 11:28:09 +01:00 |
|
immcost.ll
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implicit-def-remat-requires-impdef-check.mir
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implicit-def-subreg-to-reg-regression.ll
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implicit-def-with-impdef-greedy-assert.mir
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implicit-null-check.ll
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implicit-sret.ll
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implicitly-set-zero-high-64-bits.ll
|
[AArch64][GlobalISel] Add more shuffle test coverage. NFC (#207907)
|
2026-07-07 07:45:00 +01:00 |
|
inc-of-add.ll
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init-array.ll
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init-undef.mir
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inline-asm-blockaddress.ll
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inline-asm-clobber-arm64ec.ll
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inline-asm-clobber-base-frame-pointer.ll
|
|
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|
inline-asm-clobber-x29-x30.ll
|
[AArch64] Fix handling of x29/x30 in inline assembly clobbers (#167783)
|
2026-05-17 20:47:33 +02:00 |
|
inline-asm-clobber.ll
|
|
|
|
inline-asm-constraints-bad-sve.ll
|
[CodeGen][NFC] Remove contractions in error messages (#195308)
|
2026-05-01 11:23:24 -07:00 |
|
inline-asm-constraints-badI.ll
|
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inline-asm-constraints-badK.ll
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inline-asm-constraints-badK2.ll
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inline-asm-constraints-badL.ll
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inline-asm-flag-output.ll
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inline-asm-globaladdress.ll
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inline-asm-i-constraint-i1.ll
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inline-asm-multilevel-gep.ll
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inline-asm-nop-reg.ll
|
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inline-asm-prepare.ll
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inline-asm-speculation.ll
|
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inlineasm-illegal-type.ll
|
[CodeGen][NFC] Remove contractions in error messages (#195308)
|
2026-05-01 11:23:24 -07:00 |
|
inlineasm-ldr-pseudo.ll
|
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inlineasm-output-template.ll
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inlineasm-S-constraint.ll
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inlineasm-Uc-constraint.ll
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inlineasm-X-allocation.ll
|
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inlineasm-X-constraint.ll
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insert-extend.ll
|
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insert-subvector-res-legalization.ll
|
|
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insert-subvector.ll
|
[AArch64][GlobalISel] Add more shuffle test coverage. NFC (#207907)
|
2026-07-07 07:45:00 +01:00 |
|
insertextract.ll
|
[AArch64] Use dup (lane mov) over ext for high-half extract (#195010)
|
2026-05-11 07:31:59 +00:00 |
|
insertshuffleload.ll
|
[AArch64][GlobalISel] Add more shuffle test coverage. NFC (#207907)
|
2026-07-07 07:45:00 +01:00 |
|
instr-ref-ldv.ll
|
[DebugInfo] Verify DISubprogram has a type (#194556)
|
2026-05-04 11:32:19 +01:00 |
|
int-to-fp-no-neon.ll
|
|
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|
interleaved-load-combine-pr90695.ll
|
|
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|
interleaved-store-noninbounds-gep.ll
|
[AArch64] Fix hasNearbyPairedStore to handle non-inbounds GEPs (#199137)
|
2026-05-26 15:33:18 -07:00 |
|
intrinsic-cttz-elts-sve.ll
|
[LegalizeTypes] Don't pad cttz_elts_zero_poison with ones when widening op (#206705)
|
2026-06-30 15:15:59 +00:00 |
|
intrinsic-cttz-elts.ll
|
|
|
|
intrinsic-vector-match-sve2.ll
|
[LLVM][CodeGen][SVE] Add isel patterns for predicate "and a, (op b, c)" sequences. (#206751)
|
2026-07-02 11:45:40 +01:00 |
|
intrinsics-memory-barrier.ll
|
|
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inttoptr_debug_value.ll
|
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irg-nomem.mir
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irg.ll
|
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irg_sp_tagp.ll
|
[AArch64] Optimise materialisation of large stack offset calculations (#201856)
|
2026-06-24 15:02:00 +01:00 |
|
is_fpclass-bfloat.ll
|
|
|
|
is_fpclass.ll
|
[IR] Make semantics of strictfp consistent v2 (#211769)
|
2026-07-24 18:02:54 +00:00 |
|
isinf.ll
|
[AArch64] optimize lowering for icmp on i128 when RHS is an immediate (#181822)
|
2026-07-06 17:20:43 +01:00 |
|
issue-171032.ll
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Issue57251.ll
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itofp-bf16.ll
|
[AArch64][GlobalISel] Clean up and extend BF16 tests. NFC (#196175) (#196255)
|
2026-05-07 08:48:49 +01:00 |
|
itofp.ll
|
[AArch64] Use dup (lane mov) over ext for high-half extract (#195010)
|
2026-05-11 07:31:59 +00:00 |
|
jti-correct-datatype.mir
|
|
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|
jump-table-32.ll
|
|
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|
jump-table-compress.mir
|
[AMDGPU][NFC] Update MIR tests to use symbolic INLINEASM operands (#186839)
|
2026-04-17 12:23:56 +01:00 |
|
jump-table-duplicate.mir
|
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jump-table-exynos.ll
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jump-table-partition.ll
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jump-table.ll
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kcfi-bti.ll
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kcfi-patchable-function-prefix.ll
|
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kcfi.ll
|
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known-fpclass-splat-vector.ll
|
|
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|
known-never-nan.ll
|
[GISel] Use GISelValueTracking in isKnownNeverNaN (#190542)
|
2026-04-13 13:42:12 +00:00 |
|
knownpow2-trunc-orzero.ll
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lack-of-signed-truncation-check.ll
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|
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landingpad-ifcvt.ll
|
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large-consts.ll
|
|
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|
large-eh-encoding.ll
|
[MC][CodeGen] Add --large-eh-encoding flag for x86_64 & Aarch64 ELF (#174508)
|
2026-07-13 15:42:42 -07:00 |
|
large-offset-ldr-merge.mir
|
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large-stack-cmp.ll
|
|
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|
large-stack-offset-calcs.mir
|
[CodeGen] Rename prologpeilog to prolog-epilog (#207870)
|
2026-07-06 18:26:05 -07:00 |
|
large-stack.ll
|
Revert "[AArch64][GlobalISel] Do not run the Localizer at -O0 (#177359)" (#193781)
|
2026-04-23 16:38:44 +01:00 |
|
large_shift.ll
|
|
|
|
late-taildup-computed-goto.ll
|
[spr] initial version
|
2026-08-01 20:25:42 +00:00 |
|
latency.ll
|
|
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|
ld1postmul.ll
|
|
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|
ld1st1_post_mmo.ll
|
[AArch64] Copy MMO in ld1 / st1 post index selection. (#199023)
|
2026-06-01 07:35:16 +01:00 |
|
ldexp-arm64ec.ll
|
[X86][AArch64][SPIRV] add more tests for ldexp/frexp (#208462)
|
2026-07-09 17:59:19 +00:00 |
|
ldexp.ll
|
[GlobalISel] Improve bf16 converts with fast-math flags. (#200741)
|
2026-07-11 11:08:49 +01:00 |
|
ldp-stp-control-features.ll
|
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ldp-stp-scaled-unscaled-pairs.ll
|
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ldp-stp-unknown-size.mir
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ldradr.ll
|
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ldrpre-ldr-merge.mir
|
|
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|
ldst-implicitop.mir
|
|
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|
ldst-miflags.mir
|
[AArch64] Do not generate indexed addressing mode for volatile accesses (#196305)
|
2026-05-28 13:08:05 +00:00 |
|
ldst-nopreidx-sp-redzone.mir
|
|
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ldst-opt-aa.mir
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ldst-opt-after-block-placement.ll
|
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ldst-opt-mte-with-dbg.mir
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ldst-opt-mte.mir
|
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ldst-opt-non-imm-offset.mir
|
|
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ldst-opt-umov-fpr-store.mir
|
[AArch64] Protect against mismatching sizes in UMOV combine. (#202116)
|
2026-06-09 14:45:36 +01:00 |
|
ldst-opt-zr-clobber.mir
|
|
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|
ldst-opt.ll
|
[NFC][AArch64] Regenerate ldst-opt.ll checks to use update_llc_test_checks (#193712)
|
2026-04-23 11:34:14 +00:00 |
|
ldst-opt.mir
|
[AArch64] Do not generate indexed addressing mode for volatile accesses (#196305)
|
2026-05-28 13:08:05 +00:00 |
|
ldst-paired-aliasing.ll
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ldst-prepost-uses.ll
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ldst-regoffset.ll
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ldst-unscaledimm.ll
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ldst-unsignedimm.ll
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ldst-zero.ll
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ldst_update_cfpath.mir
|
[AArch64] Do not generate indexed addressing mode for volatile accesses (#196305)
|
2026-05-28 13:08:05 +00:00 |
|
legalize-bug-bogus-cpu.ll
|
|
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licm-regclass-copy.mir
|
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lifetime-poison.ll
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|
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lit.local.cfg
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literal_pools_float.ll
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|
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literal_pools_float_apple.ll
|
|
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|
live-debugvalues-sve.mir
|
[CodeGen] Rename prologpeilog to prolog-epilog (#207870)
|
2026-07-06 18:26:05 -07:00 |
|
live-interval-analysis.mir
|
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llrint-conv-fp16.ll
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|
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llrint-conv.ll
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llround-conv-fp16.ll
|
|
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llround-conv.ll
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|
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llvm-ir-to-intrinsic.ll
|
[AArch64][SVE] Add more MOVPRFX pseudos for SVE immediate instructions. (#192491)
|
2026-04-20 14:55:54 +01:00 |
|
llvm-masked-gather-legal-for-sve.ll
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|
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|
llvm-masked-scatter-legal-for-sve.ll
|
|
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llvm.exp10.ll
|
|
|
|
llvm.frexp.ll
|
[X86][AArch64][SPIRV] add more tests for ldexp/frexp (#208462)
|
2026-07-09 17:59:19 +00:00 |
|
llvm.modf.ll
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|
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llvm.sincos-fmf.ll
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llvm.sincos.ll
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llvm.sincospi.error.ll
|
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llvm.sincospi.ll
|
|
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|
load-combine-big-endian.ll
|
|
|
|
load-combine-masked.ll
|
[DAGCombiner] Teach MatchLoadCombine to look through AND masks (#200247)
|
2026-07-21 13:18:30 +00:00 |
|
load-combine.ll
|
|
|
|
load-insert-undef.ll
|
[LLVM][CodeGen] Remove +bf16 for ARM/AArch64 tests that don't strictly need the feature flag. (#204199)
|
2026-06-23 12:29:11 +01:00 |
|
load-insert-zero.ll
|
[LLVM][CodeGen] Remove +bf16 for ARM/AArch64 tests that don't strictly need the feature flag. (#204199)
|
2026-06-23 12:29:11 +01:00 |
|
load-store-forwarding.ll
|
[DAGCombiner] Teach reduceLoadWidth to look past ISD:FREEZE (#189317)
|
2026-04-30 09:37:39 -07:00 |
|
load-zext-bitcast.ll
|
[AArch64] Lower i16/f16 bitcast via vector operations. (#196341)
|
2026-05-15 15:17:48 +00:00 |
|
load.ll
|
|
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|
local-bounds-single-trap.ll
|
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local-sym-storage-class.ll
|
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local_vars.ll
|
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logic-reassociate.ll
|
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logic-shift.ll
|
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logical-imm.ll
|
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logical-op-with-not.ll
|
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logical_shifted_reg.ll
|
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loh-adrp-add-ldr-clobber.mir
|
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loh-use-between-adrp-add.mir
|
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loh.mir
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loop-micro-op-buffer-size-t99.ll
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loop-sink-limit.mir
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loop-sink.mir
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lower-ptrmask-arm64_32.ll
|
|
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lower-ptrmask.ll
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|
lower-range-metadata-func-call.ll
|
[Verifier] Only accept noundef metadata on loads and update metadata tests (#204922)
|
2026-06-20 18:16:02 +02:00 |
|
lowerMUL-newload.ll
|
|
|
|
lr-reserved-for-ra-live-in.ll
|
[CodeGen] Rename prologpeilog to prolog-epilog (#207870)
|
2026-07-06 18:26:05 -07:00 |
|
lrint-conv-fp16-win.ll
|
|
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lrint-conv-fp16.ll
|
|
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lrint-conv-win.ll
|
|
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|
lrint-conv.ll
|
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lround-conv-fp16-win.ll
|
|
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lround-conv-fp16.ll
|
|
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|
lround-conv-win.ll
|
|
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|
lround-conv.ll
|
|
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|
ls64-inline-asm.ll
|
|
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|
ls64-intrinsics.ll
|
|
|
|
lshr-trunc-lshr.ll
|
|
|
|
lslfast.ll
|
|
|
|
luti-with-sme2.ll
|
[LLVM][CodeGen] Remove +bf16 for ARM/AArch64 tests that don't strictly need the feature flag. (#204199)
|
2026-06-23 12:29:11 +01:00 |
|
machine-combiner-copy.ll
|
|
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machine-combiner-eor.mir
|
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machine-combiner-fmul-dup.mir
|
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machine-combiner-instr-fmf.mir
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machine-combiner-madd.ll
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machine-combiner-maddimm.mir
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machine-combiner-reassociate-accumulators.mir
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machine-combiner-reassociate-ops-in-different-blocks.mir
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machine-combiner-reassociate.mir
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machine-combiner-subadd.ll
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machine-combiner-subadd2.mir
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machine-combiner-subregs.mir
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machine-combiner-transient.ll
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machine-combiner.ll
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machine-combiner.mir
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machine-copy-prop.ll
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machine-copy-remove.ll
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machine-copy-remove.mir
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machine-cp-backward-uses.mir
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machine-cp-clobbers.mir
|
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machine-cp-constant-reg.mir
|
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machine-cp-spill-chain-across-call.mir
|
[MCP] Fix bug in spill copy elimination folding chain across a call. (#206858)
|
2026-07-06 12:13:33 +02:00 |
|
machine-cp-sub-reg.mir
|
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|
machine-cse-profitable-check.ll
|
|
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machine-dead-copy.mir
|
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|
machine-latecleanup-inlineasm.mir
|
[AMDGPU][NFC] Update MIR tests to use symbolic INLINEASM operands (#186839)
|
2026-04-17 12:23:56 +01:00 |
|
machine-licm-hoist-load.ll
|
|
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|
machine-licm-sink-instr.ll
|
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machine-licm-sub-loop.ll
|
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machine-outliner-2fixup-blr-terminator.mir
|
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machine-outliner-adrp-got-split.mir
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machine-outliner-all-stack.mir
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machine-outliner-bad-adrp.mir
|
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machine-outliner-bad-register.mir
|
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machine-outliner-bti.mir
|
[CodeGen] Rename prologpeilog to prolog-epilog (#207870)
|
2026-07-06 18:26:05 -07:00 |
|
machine-outliner-bundle-debuginfo.mir
|
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machine-outliner-bundle.mir
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machine-outliner-calls.mir
|
[CodeGen] Rename prologpeilog to prolog-epilog (#207870)
|
2026-07-06 18:26:05 -07:00 |
|
machine-outliner-cfi-tail-some.mir
|
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machine-outliner-cfi-tail.mir
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machine-outliner-cfi.mir
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machine-outliner-compatible-candidates.mir
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machine-outliner-create-lr-livein.mir
|
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machine-outliner-default.mir
|
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machine-outliner-drop-stack.mir
|
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machine-outliner-flags.ll
|
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machine-outliner-function-annotate.mir
|
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machine-outliner-inline-asm-adrp.mir
|
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machine-outliner-iterative-2.mir
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machine-outliner-iterative.mir
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machine-outliner-labels.mir
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machine-outliner-leaf-descendants.ll
|
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machine-outliner-loh.ll
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machine-outliner-loh.mir
|
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machine-outliner-mapper-debug-output.mir
|
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machine-outliner-mapper-stats.mir
|
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machine-outliner-mapping-stats.mir
|
|
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|
machine-outliner-no-noreturn-no-stack.mir
|
[CodeGen] Rename prologpeilog to prolog-epilog (#207870)
|
2026-07-06 18:26:05 -07:00 |
|
machine-outliner-noredzone.ll
|
|
|
|
machine-outliner-noreturn-no-stack.mir
|
[CodeGen] Rename prologpeilog to prolog-epilog (#207870)
|
2026-07-06 18:26:05 -07:00 |
|
machine-outliner-noreturn-save-lr.mir
|
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machine-outliner-only-unsafe-ranges.mir
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machine-outliner-ordering.mir
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machine-outliner-outline-bti.ll
|
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machine-outliner-overlap.mir
|
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machine-outliner-patchable.ll
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machine-outliner-patchable.mir
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machine-outliner-pgo.ll
|
|
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machine-outliner-regsave.mir
|
[CodeGen] Rename prologpeilog to prolog-epilog (#207870)
|
2026-07-06 18:26:05 -07:00 |
|
machine-outliner-remarks.ll
|
|
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machine-outliner-retaddr-sign-cfi.ll
|
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machine-outliner-retaddr-sign-diff-scope-same-key.ll
|
|
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machine-outliner-retaddr-sign-non-leaf.ll
|
|
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machine-outliner-retaddr-sign-regsave.mir
|
[CodeGen] Rename prologpeilog to prolog-epilog (#207870)
|
2026-07-06 18:26:05 -07:00 |
|
machine-outliner-retaddr-sign-same-scope-diff-key.ll
|
|
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machine-outliner-retaddr-sign-same-scope-same-key-a.ll
|
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machine-outliner-retaddr-sign-same-scope-same-key-b.ll
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machine-outliner-retaddr-sign-sp-mod.ll
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machine-outliner-retaddr-sign-sp-mod.mir
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machine-outliner-retaddr-sign-subtarget.ll
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machine-outliner-retaddr-sign-thunk.ll
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machine-outliner-retaddr-sign-v8-3.ll
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machine-outliner-safe-range-in-middle.mir
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machine-outliner-side-effect-2.mir
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machine-outliner-side-effect.mir
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machine-outliner-size-info.mir
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[CodeGen] Rename prologpeilog to prolog-epilog (#207870)
|
2026-07-06 18:26:05 -07:00 |
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machine-outliner-sort-per-priority.ll
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machine-outliner-sort-per-priority.mir
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machine-outliner-tail.ll
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machine-outliner-threshold.mir
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machine-outliner-throw.ll
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machine-outliner-throw2.ll
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machine-outliner-thunk.ll
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machine-outliner-unsafe-range-at-beginning.mir
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machine-outliner-unsafe-range-at-end.mir
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machine-outliner-unsafe-stack-call.mir
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machine-outliner.ll
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machine-outliner.mir
|
[CodeGen] Rename prologpeilog to prolog-epilog (#207870)
|
2026-07-06 18:26:05 -07:00 |
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machine-scheduler.mir
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machine-sink-cache-invalidation.ll
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machine-sink-getmemoperandwithoffset.mir
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machine-sink-kill-flags.ll
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machine-sink-zr.mir
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machine-sme-abi-find-insert-pt.mir
|
Revert "[AArch64] Fix definition of system register move instructions" (#201137)
|
2026-06-02 16:44:37 +01:00 |
|
machine-sme-abi-skip-debug-inst.mir
|
Revert "[AArch64] Fix definition of system register move instructions" (#201137)
|
2026-06-02 16:44:37 +01:00 |
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machine-zero-copy-remove.mir
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machine_cse.ll
|
[AArch64][ISel] Enable profile-aware branch condition merging (#201486)
|
2026-06-24 16:22:51 +01:00 |
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machine_cse_illegal_hoist.ll
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machine_cse_impdef_killflags.ll
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macho-global-symbols.ll
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macho-none.ll
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macho-trap.ll
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macro-fusion-addsub-2reg-const1.mir
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macro-fusion-cluster-conflict.mir
|
[MacroFusion] Early return when insts already clustered (#191710)
|
2026-04-16 08:50:56 +03:00 |
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macro-fusion-last.mir
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macro-fusion.ll
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madd-combiner.ll
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masked-integer-compare.ll
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masked-sdiv-fixed-length.ll
|
[LLVM][CodeGen][SVE] Add custom lowering for ISD::MASKED_SDIV/UDIV. (#191164)
|
2026-04-17 13:42:19 +01:00 |
|
masked-sdiv-scalable.ll
|
[LLVM][CodeGen][SVE] Add custom lowering for ISD::MASKED_SDIV/UDIV. (#191164)
|
2026-04-17 13:42:19 +01:00 |
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masked-srem-fixed-length.ll
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masked-srem-scalable.ll
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masked-udiv-fixed-length.ll
|
[LLVM][CodeGen][SVE] Add custom lowering for ISD::MASKED_SDIV/UDIV. (#191164)
|
2026-04-17 13:42:19 +01:00 |
|
masked-udiv-scalable.ll
|
[LLVM][CodeGen][SVE] Add custom lowering for ISD::MASKED_SDIV/UDIV. (#191164)
|
2026-04-17 13:42:19 +01:00 |
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masked-urem-fixed-length.ll
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masked-urem-scalable.ll
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mattr-all.ll
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mature-mc-support.ll
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max-jump-table.ll
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max-stores-per-mem-ops.ll
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memcmp.ll
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memcpy-f128.ll
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memcpy-scoped-aa.ll
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memmove-inline.ll
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memset-inline.ll
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memset-vs-memset-inline.ll
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memset.ll
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memsize-remarks.ll
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memtag-compact-unwind.ll
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memtag-loop-nzcv.ll
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memtag-merge-writeback.mir
|
[AArch64] Do not generate indexed addressing mode for volatile accesses (#196305)
|
2026-05-28 13:08:05 +00:00 |
|
memtag-stg-loop-reg-pressure.mir
|
[CodeGen] Rename prologpeilog to prolog-epilog (#207870)
|
2026-07-06 18:26:05 -07:00 |
|
merge-loads-feeding-as-shuffleops.ll
|
[SelectionDAG] Merge consecutive loads feeding as shuffle operands (#207303)
|
2026-07-21 10:12:04 +00:00 |
|
merge-scoped-aa-store.ll
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merge-store-dependency.ll
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merge-store.ll
|
[AArch64] Add tablegen patterns for store of high-half. (#190320)
|
2026-04-13 17:24:14 +01:00 |
|
merge-trunc-store.ll
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mergestores_noimplicitfloat.ll
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midpoint-int.ll
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min-jump-table.ll
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min-max-combine.ll
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min-max.ll
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mingw-refptr.ll
|
[aarch64] Mix the frame pointer with the stack cookie when protecting the stack (#197346)
|
2026-07-01 15:33:56 +08:00 |
|
minmax-of-minmax.ll
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|
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|
minmax.ll
|
[AArch64][GlobalISel] More test updates for vector select. NFC (#197023)
|
2026-05-11 20:58:04 +01:00 |
|
mir-yaml-has-streaming-mode-changes.ll
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misched-branch-targets.mir
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misched-bundle.mir
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misched-cutoff.mir
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misched-detail-resource-booking-01.mir
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misched-detail-resource-booking-02.mir
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misched-fuse-cset.ll
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misched-fusion-addadrp.ll
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misched-fusion-addr-tune.ll
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misched-fusion-addr.ll
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misched-fusion-aes-post-ra.mir
|
[AArch64][MacroFusion] Fuse only tied AES pairs post-RA (#201610)
|
2026-06-08 22:40:43 +03:00 |
|
misched-fusion-aes.ll
|
[AArch64][MacroFusion] Fuse only tied AES pairs post-RA (#201610)
|
2026-06-08 22:40:43 +03:00 |
|
misched-fusion-apple-sme-compute.mir
|
[AArch64] Relax SDep requirement for AppleSMECompute clustering (#212603)
|
2026-07-30 14:32:53 +03:00 |
|
misched-fusion-arith-bcc.ll
|
[AArch64] Split misched-fusion.ll per feature(NFC) (#203576)
|
2026-06-15 21:58:55 +03:00 |
|
misched-fusion-arith-bcc.mir
|
[AArch64] Split misched-fusion.ll per feature(NFC) (#203576)
|
2026-06-15 21:58:55 +03:00 |
|
misched-fusion-arith-cbz.ll
|
[AArch64] Add missing TB(N)Z achors to arith+CBZ clustering (#207725)
|
2026-07-09 12:48:26 +03:00 |
|
misched-fusion-arith-cbz.mir
|
[AArch64] Add missing TB(N)Z achors to arith+CBZ clustering (#207725)
|
2026-07-09 12:48:26 +03:00 |
|
misched-fusion-arith-logic.mir
|
|
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|
misched-fusion-cmp-bcc.ll
|
[GISel] Disable opt_brcond_by_inverting_cond combine at O0 (#193417)
|
2026-04-24 09:11:23 +01:00 |
|
misched-fusion-cmp.mir
|
[AMDGPU][NFC] Update MIR tests to use symbolic INLINEASM operands (#186839)
|
2026-04-17 12:23:56 +01:00 |
|
misched-fusion-crypto-eor.mir
|
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|
misched-fusion-csel.ll
|
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|
misched-fusion-fcsel.ll
|
|
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|
misched-fusion-fmin-fmax-post-ra.mir
|
[AArch64] Add FMIN/FMAX clustering (#210906)
|
2026-07-25 16:39:55 +03:00 |
|
misched-fusion-fmin-fmax-pre-ra.mir
|
[AArch64] Add FMIN/FMAX clustering (#210906)
|
2026-07-25 16:39:55 +03:00 |
|
misched-fusion-fmin-fmax.ll
|
[AArch64] Add FMIN/FMAX clustering (#210906)
|
2026-07-25 16:39:55 +03:00 |
|
misched-fusion-lit.ll
|
|
|
|
misched-fusion-no-raw-dependency.mir
|
[MacroFusion] Restrict pairs to have SDep::Data dependency only (#203793)
|
2026-06-16 11:02:36 +03:00 |
|
misched-move-imm.mir
|
|
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|
misched-predicate-virtreg.mir
|
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misched-push-form-transposed-tuple-to-users.mir
|
[AArch64] Expand FORM_TRANSPOSED_REG_TUPLE to copies before regalloc (#207205)
|
2026-07-09 09:01:56 +01:00 |
|
misched-reg-pressure-limits.mir
|
[AArch64] Mark FIXED_REGS register class as non-allocatable (#212250)
|
2026-07-29 12:06:05 +01:00 |
|
misched-sort-resource-in-trace.mir
|
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misched-stp.ll
|
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mla_mls_merge.ll
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mlicm-csr-mask.mir
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mlicm-implicit-defs.mir
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mlicm-stack-write-check.mir
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mops-mmo-size.ll
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mops-register-alias.ll
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movi64_sve.ll
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movid-no-neon.ll
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movimm-expand-ldst.ll
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movimm-expand-ldst.mir
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movimm-wzr.mir
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movw-consts.ll
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|
movw-shift-encoding.ll
|
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mul-cmp.ll
|
|
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|
mul-const-addressing-mode.ll
|
[AArch64] Decompose constant multiplies used only by memory addresses (#194584)
|
2026-05-16 13:09:38 -07:00 |
|
mul-i128-overflow.ll
|
|
|
|
mul-i256.ll
|
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|
mul-lohi.ll
|
|
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|
mul.ll
|
[AArch64][GlobalISel] Improve multiplication with multiple registers (#197943)
|
2026-05-16 20:47:25 +02:00 |
|
mul_by_elt.ll
|
|
|
|
mul_pow2.ll
|
[GIsel] Add combine (sub a, (mul x, C)) -> (add a, (mul x, -C)) (#194282)
|
2026-05-04 10:50:27 -07:00 |
|
mulcmle.ll
|
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|
mulhu-srl-promoted-ops.ll
|
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|
multi-vector-load-size.ll
|
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|
multi-vector-store-size.ll
|
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|
naked-fn-with-frame-pointer.ll
|
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|
named-vector-shuffle-reverse-neon.ll
|
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|
named-vector-shuffle-reverse-sve.ll
|
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|
named-vector-shuffles-neon.ll
|
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named-vector-shuffles-sve.ll
|
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neg-abs.ll
|
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|
neg-imm.ll
|
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|
neg-selects.ll
|
|
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|
neg-sign-masked-and.ll
|
[AArch64] Reassociate neg (and X, M) with an all-0/1's mask M (#207671)
|
2026-07-10 17:53:31 +03:00 |
|
neon-abd.ll
|
[AArch64] Use dup (lane mov) over ext for high-half extract (#195010)
|
2026-05-11 07:31:59 +00:00 |
|
neon-addlv.ll
|
|
|
|
neon-anyof-splat.ll
|
[AArch64][GlobalISel] More test updates for vector select. NFC (#197023)
|
2026-05-11 20:58:04 +01:00 |
|
neon-bitcast.ll
|
|
|
|
neon-bitselect.ll
|
|
|
|
neon-bitwise-instructions.ll
|
[AArch64][GlobalISel] Fold G_SHUFFLE to single-element TBL with zero elements. (#200938)
|
2026-07-11 08:12:13 +01:00 |
|
neon-compare-instructions.ll
|
|
|
|
neon-diagnostics.ll
|
|
|
|
neon-dot-product.ll
|
|
|
|
neon-dotpattern.ll
|
|
|
|
neon-dotreduce.ll
|
[AArch64] Mark FIXED_REGS register class as non-allocatable (#212250)
|
2026-07-29 12:06:05 +01:00 |
|
neon-extadd-extract.ll
|
|
|
|
neon-extadd.ll
|
[AArch64] Mark FIXED_REGS register class as non-allocatable (#212250)
|
2026-07-29 12:06:05 +01:00 |
|
neon-extmul.ll
|
|
|
|
neon-extract.ll
|
|
|
|
neon-extractbitcast-mir.ll
|
[AArch64] Lower i16/f16 bitcast via vector operations. (#196341)
|
2026-05-15 15:17:48 +00:00 |
|
neon-extracttruncate.ll
|
[AArch64][GlobalISel] Add more shuffle test coverage. NFC (#207907)
|
2026-07-07 07:45:00 +01:00 |
|
neon-famin-famax.ll
|
|
|
|
neon-fma-FMF.ll
|
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|
neon-fma.ll
|
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|
neon-fp8-cvt.ll
|
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|
neon-fp8-fscale.ll
|
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|
neon-fp16fml.ll
|
|
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|
neon-fpextend_f16.ll
|
|
|
|
neon-fpround_f128.ll
|
|
|
|
neon-idiv.ll
|
|
|
|
neon-inline-asm-16-bit-fp.ll
|
|
|
|
neon-ins-trunc-elt.ll
|
|
|
|
neon-insert-sve-elt.ll
|
|
|
|
neon-insextbitcast.ll
|
[AArch64] Lower i16/f16 bitcast via vector operations. (#196341)
|
2026-05-15 15:17:48 +00:00 |
|
neon-lowhalf128-optimisation.ll
|
|
|
|
neon-luti.ll
|
[LLVM][CodeGen] Remove +bf16 for ARM/AArch64 tests that don't strictly need the feature flag. (#204199)
|
2026-06-23 12:29:11 +01:00 |
|
neon-matmul-f16.ll
|
[AArch64][clang][llvm] Add ACLE Armv9.7 matrix multiply-accumulate intrinsics (#193017)
|
2026-04-27 15:40:50 +01:00 |
|
neon-matmul-f16f32mm.ll
|
[AArch64][clang][llvm] Add ACLE Armv9.7 matrix multiply-accumulate intrinsics (#193017)
|
2026-04-27 15:40:50 +01:00 |
|
neon-mla-mls.ll
|
|
|
|
neon-mov.ll
|
[LLVM][Constants] Remove the option to disable vector ConstantFP support. (#197427)
|
2026-05-14 11:45:37 +01:00 |
|
neon-mul-shl.ll
|
|
|
|
neon-or-combine.ll
|
|
|
|
neon-partial-reduce-dot-product.ll
|
[AArch64] Lower SUMLA via two udot products on plain dotprod targets. (#199761)
|
2026-05-28 13:26:48 +00:00 |
|
neon-perm.ll
|
[AArch64][GlobalISel] Lower unmerge to extract_subvector (#195046)
|
2026-05-05 17:39:07 +01:00 |
|
neon-reverseshuffle.ll
|
|
|
|
neon-rshrn.ll
|
[AArch64] Add disjoint or tests for rshrn and raddhn. NFC (#194252)
|
2026-04-26 19:02:06 +01:00 |
|
neon-saba.ll
|
[AArch64] Use add_like for SABD and UABA (#194421)
|
2026-05-01 14:09:13 +00:00 |
|
neon-sad.ll
|
|
|
|
neon-scalar-by-elem-fma.ll
|
|
|
|
neon-scalar-copy.ll
|
[AArch64] Use dup (lane mov) over ext for high-half extract (#195010)
|
2026-05-11 07:31:59 +00:00 |
|
neon-scalar-vcvtfp2fx.ll
|
[AArch64][SelectionDAG] Avoid cross-bank copy for NEON vcvtfp2fx result (#210275)
|
2026-07-30 11:20:58 +01:00 |
|
neon-scalarize-histogram.ll
|
|
|
|
neon-sha3.ll
|
|
|
|
neon-shift-left-long.ll
|
[AArch64] Use dup (lane mov) over ext for high-half extract (#195010)
|
2026-05-11 07:31:59 +00:00 |
|
neon-shift-neg.ll
|
|
|
|
neon-shuffle-vector-tbl.ll
|
[AArch64][GlobalISel] Add more shuffle test coverage. NFC (#207907)
|
2026-07-07 07:45:00 +01:00 |
|
neon-sm4-sm3.ll
|
|
|
|
neon-stepvector.ll
|
|
|
|
neon-truncstore.ll
|
|
|
|
neon-vcadd.ll
|
|
|
|
neon-vcmla.ll
|
|
|
|
neon-vector-splat.ll
|
|
|
|
neon-vmull-high-p8.ll
|
|
|
|
neon-vmull-high-p64.ll
|
|
|
|
neon-wide-splat.ll
|
[AArch64][GlobalISel] Fold G_SHUFFLE to single-element TBL with zero elements. (#200938)
|
2026-07-11 08:12:13 +01:00 |
|
neon-widen-shuffle.ll
|
[AArch64][GlobalISel] Fold G_SHUFFLE to single-element TBL with zero elements. (#200938)
|
2026-07-11 08:12:13 +01:00 |
|
neon_rbit.ll
|
|
|
|
nest-register.ll
|
|
|
|
nested-iv-regalloc.mir
|
[MIR] Serialize/Deserialize MachineInstr::LRSplit flag (#197362)
|
2026-07-06 18:53:16 +02:00 |
|
new-load-requires-renaming-in-mssa.ll
|
|
|
|
no-fp-asm-clobbers-crash.ll
|
|
|
|
no-promote-scalabale-const-to-global.ll
|
|
|
|
no-quad-ldp-stp.ll
|
|
|
|
no-reorder-cfi-merge-back-load.mir
|
[AArch64] Do not generate indexed addressing mode for volatile accesses (#196305)
|
2026-05-28 13:08:05 +00:00 |
|
no-reorder-cfi-merge-back-store.mir
|
|
|
|
no-reorder-cfi-merge-fwd-load.mir
|
[AArch64] Do not generate indexed addressing mode for volatile accesses (#196305)
|
2026-05-28 13:08:05 +00:00 |
|
no-reorder-cfi-merge-fwd.mir
|
|
|
|
no-reorder-cfi-no-merge.mir
|
|
|
|
no-reorder-cfi.ll
|
|
|
|
no-stack-arg-probe.ll
|
|
|
|
no-sve-no-neon.ll
|
|
|
|
no-tail-call-bzero-from-memset.ll
|
|
|
|
no-xzr-liveins.mir
|
[CodeGen] Rename prologpeilog to prolog-epilog (#207870)
|
2026-07-06 18:26:05 -07:00 |
|
no_cfi.ll
|
|
|
|
nofpclass.ll
|
|
|
|
nomerge.ll
|
|
|
|
nonlazybind.ll
|
|
|
|
nontemporal-load-interleaved.ll
|
|
|
|
nontemporal-load.ll
|
[AArch64] Use dup (lane mov) over ext for high-half extract (#195010)
|
2026-05-11 07:31:59 +00:00 |
|
nontemporal-store-interleaved-optsize.ll
|
|
|
|
nontemporal-store-interleaved.ll
|
|
|
|
nontemporal-store-optsize.ll
|
|
|
|
nontemporal-store.ll
|
[AArch64] Keep MMO when converting gather lane to LDRSui. (#197522)
|
2026-05-14 07:59:48 +01:00 |
|
note-gnu-property-elf-pauthabi.ll
|
[PAC][clang] Fix ptrauth module flags behavior (#204226)
|
2026-07-13 19:07:24 +00:00 |
|
note-gnu-property-gcs.ll
|
|
|
|
note-gnu-property-pac-bti-0.ll
|
|
|
|
note-gnu-property-pac-bti-1.ll
|
|
|
|
note-gnu-property-pac-bti-2.ll
|
|
|
|
note-gnu-property-pac-bti-3.ll
|
|
|
|
note-gnu-property-pac-bti-4.ll
|
|
|
|
null-mctargetstreamer.ll
|
|
|
|
nzcv-save.ll
|
|
|
|
O0-pipeline.ll
|
[AArch64][GlobalISel] Drop unused value tracking from O0 pre-legalizer combiner (NFC) (#194826)
|
2026-05-01 05:31:10 +01:00 |
|
O3-pipeline.ll
|
add extra cycle analyses from MachineLICM not preserving CI
|
2026-08-01 20:26:56 +00:00 |
|
optimize-cond-branch.ll
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optimize-imm.ll
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optimize_combine_large_shifts.ll
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or-combine.ll
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outlining-with-streaming-mode-changes.ll
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overeager_mla_fusing.ll
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overflow.ll
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overlapping-copy-bundle-cycle.mir
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overlapping-copy-bundle.mir
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p2align-zero-fillvalue.ll
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pacbti-llvm-generated-funcs-1.ll
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pacbti-llvm-generated-funcs-2.ll
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pacbti-module-attrs.ll
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paired-load.ll
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parity.ll
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partial-pipeline-execution.ll
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partial-reduction-add-predicated.ll
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partial-reduction-add.ll
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partial-reduction-sub-fp.ll
|
[AArch64] Use fp16 FNEG and FABS for bf16. (#198653)
|
2026-05-20 19:19:25 +01:00 |
|
partial-reduction-sub.ll
|
[ISel][AArch64] Add CodeGen support for partial sub reductions. (#186809)
|
2026-04-23 11:34:15 +01:00 |
|
patchable-function-entry-bti.ll
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patchable-function-entry-empty.mir
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patchable-function-entry.ll
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pauth-lr-tail-call-fpdiff.ll
|
[llvm][AArch64] Fix the location of PAuth_LR AUT CFI (#211702)
|
2026-07-24 06:33:33 -07:00 |
|
pauthlr-prologue-duplication.mir
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PBQP-chain.ll
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PBQP-coalesce-benefit.ll
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PBQP-csr.ll
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PBQP.ll
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pcsections.ll
|
[GISel] Disable opt_brcond_by_inverting_cond combine at O0 (#193417)
|
2026-04-24 09:11:23 +01:00 |
|
pdep.ll
|
[ISel] Introduce llvm.pext and llvm.pdep intrinsics (#200570)
|
2026-06-16 11:05:41 +00:00 |
|
peephole-and-tst.ll
|
[AArch64][ISel] Enable profile-aware branch condition merging (#201486)
|
2026-06-24 16:22:51 +01:00 |
|
peephole-csel.ll
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peephole-csel.mir
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peephole-insert-subreg.mir
|
[AArch64] Clear kill flags from visitINSvi64lane (#209096)
|
2026-07-13 08:16:43 +01:00 |
|
peephole-insvigpr.mir
|
[AArch64] Clear kill flags from visitINSvi64lane (#209096)
|
2026-07-13 08:16:43 +01:00 |
|
peephole-movd.mir
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peephole-opt-analyzeCompare-subreg-use.mir
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peephole-opt-check-cflags.mir
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peephole-orr.mir
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peephole-substitute-cmp-adcs.mir
|
[AArch64] Add final missing instructions to sForm (#167518)
|
2026-06-23 19:28:12 -07:00 |
|
peephole-sxtw.mir
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perm-tb-with-sme2.ll
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pext.ll
|
[ISel] Introduce llvm.pext and llvm.pdep intrinsics (#200570)
|
2026-06-16 11:05:41 +00:00 |
|
phi-dbg.ll
|
Revert "[AArch64][GlobalISel] Do not run the Localizer at -O0 (#177359)" (#193781)
|
2026-04-23 16:38:44 +01:00 |
|
phi.ll
|
[AArch64][GlobalISel] Lower unmerge to extract_subvector (#195046)
|
2026-05-05 17:39:07 +01:00 |
|
PHIElimination-crash.mir
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PHIElimination-debugloc.mir
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pic-eh-stubs.ll
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pie.ll
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pmull-ldr-merge.ll
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popcount.ll
|
Revert "[AArch64][GlobalISel] Do not run the Localizer at -O0 (#177359)" (#193781)
|
2026-04-23 16:38:44 +01:00 |
|
popcount_vmask.ll
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post-ra-machine-sink.mir
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postra-mi-sched.ll
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pow.75.ll
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pow.ll
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powi-arm64ec.ll
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|
powi-ldexp-promote-libcall-error.ll
|
[SelectionDAG] Promote FPOWI/FLDEXP exponents where possible, and raise an error otherwise (#200621)
|
2026-06-09 08:05:22 -07:00 |
|
powi-windows.ll
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powi.ll
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pr-cf624b2.ll
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pr27816.ll
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pr33172.ll
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pr40091.ll
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pr48188.ll
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pr49781.ll
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pr51476.ll
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pr51516.mir
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pr53315-returned-i128.ll
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pr55178.ll
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pr55201.ll
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pr55644.ll
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pr58350.ll
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pr58431.ll
|
[GIsel] Add combine (sub a, (mul x, C)) -> (add a, (mul x, -C)) (#194282)
|
2026-05-04 10:50:27 -07:00 |
|
pr58516.ll
|
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pr59891-dagcombine-deleted-freeze.ll
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pr59902.ll
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pr61111.ll
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pr61549.ll
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pr66603.ll
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pr72777.ll
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pr79100.ll
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pr86717.ll
|
[DAGCombiner] Fold sub nuw C, x -> xor x, C when C is a mask (#192692)
|
2026-04-17 22:05:34 +01:00 |
|
pr88966.ll
|
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|
pr90936.ll
|
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pr92062.ll
|
Revert "[AArch64][GlobalISel] Do not run the Localizer at -O0 (#177359)" (#193781)
|
2026-04-23 16:38:44 +01:00 |
|
pr96366.ll
|
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pr135776.ll
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pr135821.ll
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pr142314.ll
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pr148949.ll
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pr157118.ll
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pr157252.mir
|
[CodeGen] Rename prologpeilog to prolog-epilog (#207870)
|
2026-07-06 18:26:05 -07:00 |
|
pr161013.ll
|
[DAG] Add Srl combine for extracting last element of BUILD_VECTOR (#181412)
|
2026-04-21 12:28:48 +01:00 |
|
pr161289.ll
|
|
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|
pr161420.ll
|
|
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|
pr164181.ll
|
[Test] Fix loop exit conditions to prevent trivial optimizations (#201867)
|
2026-06-05 16:19:14 +00:00 |
|
pr166870.ll
|
[BranchFolding] Fold away subsequent identical branches
|
2026-07-21 16:21:20 -07:00 |
|
pr204118.ll
|
[AArch64][GISel] Remove hard-coded operand index from FCVT renderers (#204118)
|
2026-06-22 09:33:29 +01:00 |
|
pre-indexed-addrmode-with-constant-offset.ll
|
|
|
|
predicate-as-counter-phi.ll
|
[AArch64] Use PNR rather than PPR register class for aarch64svcount (#202394)
|
2026-06-10 10:09:35 +01:00 |
|
predicated-add-sub.ll
|
|
|
|
preferred-alignment.ll
|
|
|
|
preferred-function-alignment.ll
|
[MC,CodeGen] Update .prefalign for symbol-based preferred alignment (#184032)
|
2026-04-11 06:16:43 +00:00 |
|
prefixdata.ll
|
|
|
|
preserve-all-large-csr.ll
|
[AArch64] Fix miscompilation due to integer overflow in immediate offset for stack store/load instructions with preserve_all (#207026)
|
2026-07-11 14:11:08 +01:00 |
|
preserve.ll
|
[CodeGen] Rename prologpeilog to prolog-epilog (#207870)
|
2026-07-06 18:26:05 -07:00 |
|
preserve_mostcc.ll
|
|
|
|
preserve_nonecc.ll
|
|
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|
preserve_nonecc_call.ll
|
|
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|
preserve_nonecc_musttail.ll
|
|
|
|
preserve_nonecc_swift.ll
|
|
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|
preserve_nonecc_varargs_aapcs.ll
|
|
|
|
preserve_nonecc_varargs_darwin.ll
|
|
|
|
preserve_nonecc_varargs_win64.ll
|
|
|
|
print-pipeline-passes.ll
|
[PowerPC][AIX] Support #pragma comment copyright for AIX (#178184)
|
2026-06-19 06:13:33 +05:30 |
|
prologue-epilogue-remarks.mir
|
[CodeGen] Rename prologpeilog to prolog-epilog (#207870)
|
2026-07-06 18:26:05 -07:00 |
|
ptradd.ll
|
[AArch64] Use dup (lane mov) over ext for high-half extract (#195010)
|
2026-05-11 07:31:59 +00:00 |
|
ptrauth-arm64-tls-dynamics.ll
|
|
|
|
ptrauth-basic-pic.ll
|
|
|
|
ptrauth-bti-call.ll
|
|
|
|
ptrauth-call-rv-marker.ll
|
|
|
|
ptrauth-call.ll
|
|
|
|
ptrauth-constant-in-code.ll
|
|
|
|
ptrauth-elf-globals-pic.ll
|
|
|
|
ptrauth-elf-got-function-symbols.ll
|
[PAC][clang] Fix ptrauth module flags behavior (#204226)
|
2026-07-13 19:07:24 +00:00 |
|
ptrauth-extern-weak.ll
|
|
|
|
ptrauth-fpac.ll
|
|
|
|
ptrauth-global-no-pic.ll
|
|
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|
ptrauth-got-abuse.ll
|
|
|
|
ptrauth-indirectbr.ll
|
|
|
|
ptrauth-init-fini-autoupgrade.ll
|
[AArch64][PAC] Handle signing of init/fini pointers in AsmPrinter (#193087)
|
2026-07-14 00:01:53 +00:00 |
|
ptrauth-init-fini.ll
|
[AArch64][PAC] Handle signing of init/fini pointers in AsmPrinter (#193087)
|
2026-07-14 00:01:53 +00:00 |
|
ptrauth-intrinsic-auth-resign-relative-load.ll
|
|
|
|
ptrauth-intrinsic-auth-resign-with-blend.ll
|
[AArch64][PAC] Rework the expansion of AUT/AUTPAC pseudos (#169699)
|
2026-07-18 15:18:44 +03:00 |
|
ptrauth-intrinsic-auth-resign.ll
|
|
|
|
ptrauth-intrinsic-auth-with-pc-and-resign.ll
|
[arm64e] Add a builtin + intrinsic for arm64e PAuth_LR: __builtin_ptr_auth_auth_with_pc_and_resign (#202742)
|
2026-07-08 13:21:02 -07:00 |
|
ptrauth-intrinsic-blend.ll
|
|
|
|
ptrauth-intrinsic-sign-generic.ll
|
|
|
|
ptrauth-intrinsic-sign.ll
|
|
|
|
ptrauth-intrinsic-strip.ll
|
|
|
|
ptrauth-invoke.ll
|
|
|
|
ptrauth-irelative.ll
|
|
|
|
ptrauth-isel.ll
|
[AArch64][PAC] Reset killed operand flag in custom inserter of PAC pseudo (#158699)
|
2026-07-08 22:24:26 +03:00 |
|
ptrauth-isel.mir
|
[AArch64][PAC] Reset killed operand flag in custom inserter of PAC pseudo (#158699)
|
2026-07-08 22:24:26 +03:00 |
|
ptrauth-reloc.ll
|
|
|
|
ptrauth-ret-trap.ll
|
|
|
|
ptrauth-ret.ll
|
|
|
|
ptrauth-sign-personality.ll
|
|
|
|
ptrauth-tagged-globals-pic.ll
|
|
|
|
ptrauth-tail-call-global.ll
|
|
|
|
ptrauth-tail-call-regalloc.ll
|
|
|
|
ptrauth-tiny-model-pic.ll
|
|
|
|
ptrauth-tiny-model-static.ll
|
|
|
|
ptrauth-tls-darwin.ll
|
|
|
|
ptrauth-type-info-vptr-discr.ll
|
|
|
|
pull-binop-through-shift.ll
|
|
|
|
pull-conditional-binop-through-shift.ll
|
|
|
|
pull-negations-after-concat-of-truncates.ll
|
|
|
|
qmovn.ll
|
[AArch64][GISel] Regbank G_BITCAST using src regbank. (#191522)
|
2026-04-18 14:40:15 +01:00 |
|
qshrn.ll
|
|
|
|
ragreedy-csr.ll
|
[SCEV] Use SCEVPtrToAddr instead of SCEVPtrToInt in SCEV. (#180244)
|
2026-07-24 20:20:48 +01:00 |
|
ragreedy-csr2.ll
|
|
|
|
ragreedy-local-interval-cost.ll
|
DAG: Use poison in getLoad/getStore for offsets (#212066)
|
2026-07-31 06:33:58 +02:00 |
|
rand.ll
|
|
|
|
range-prefetch.ll
|
|
|
|
rax1.ll
|
|
|
|
rbit.ll
|
|
|
|
rcpc3-sve.ll
|
[AArch64] Hint regalloc to choose distinct predicate for MATCH/CMP (#190139)
|
2026-04-14 09:40:50 +01:00 |
|
rcpc3.ll
|
|
|
|
read-fp-reg.ll
|
[CodeGen] Mark read_register of allocatable physreg as live-in (#200825)
|
2026-06-03 14:57:12 -07:00 |
|
read-pc.ll
|
|
|
|
read-reg-non-entry.ll
|
[CodeGen] Mark read_register of allocatable physreg as live-in (#200825)
|
2026-06-03 14:57:12 -07:00 |
|
readcyclecounter.ll
|
|
|
|
reassocmls.ll
|
|
|
|
recp-fastmath.ll
|
|
|
|
reduce-and.ll
|
[AArch64] Use dup (lane mov) over ext for high-half extract (#195010)
|
2026-05-11 07:31:59 +00:00 |
|
reduce-load-width-freeze.ll
|
[DAGCombiner] Teach reduceLoadWidth to look past ISD:FREEZE (#189317)
|
2026-04-30 09:37:39 -07:00 |
|
reduce-or-opt.ll
|
|
|
|
reduce-or.ll
|
[AArch64] Use dup (lane mov) over ext for high-half extract (#195010)
|
2026-05-11 07:31:59 +00:00 |
|
reduce-shuffle.ll
|
|
|
|
reduce-xor.ll
|
[AArch64] Use dup (lane mov) over ext for high-half extract (#195010)
|
2026-05-11 07:31:59 +00:00 |
|
redundant-copy-elim-empty-mbb.ll
|
|
|
|
redundant-mov-from-zero-extend.ll
|
|
|
|
redundant-orrwrs-from-zero-extend.mir
|
AArch64: Fix mishandling subregister in orr peephole (#208015)
|
2026-07-10 15:14:13 +02:00 |
|
Redundantstore.ll
|
|
|
|
reg-scavenge-frame.mir
|
[CodeGen] Rename prologpeilog to prolog-epilog (#207870)
|
2026-07-06 18:26:05 -07:00 |
|
regalloc-hint-movprfx-streaming.mir
|
[AArch64][SME2] Add stridedorcontiguous pseudos for multi-vector-stores (#211551)
|
2026-07-30 16:21:59 +00:00 |
|
regalloc-hint-movprfx.mir
|
|
|
|
regalloc-last-chance-recolor-with-split.mir
|
|
|
|
regalloc-spill-weight-basic.ll
|
|
|
|
regcoal-physreg.mir
|
[NFC] Fix "is is" typos (#206288)
|
2026-07-06 18:07:45 +00:00 |
|
register-coalesce-update-subranges-remat.mir
|
|
|
|
regress-bitcast-formals.ll
|
|
|
|
regress-combine-extract-vectors.ll
|
|
|
|
regress-f128csel-flags.ll
|
|
|
|
regress-fp128-livein.ll
|
|
|
|
regress-tail-livereg.ll
|
|
|
|
regress-tblgen-chains.ll
|
|
|
|
regress-w29-reserved-with-fp.ll
|
|
|
|
relaxed-fp-atomics.ll
|
|
|
|
reloc-specifiers.mir
|
[CodeGen] Rename prologpeilog to prolog-epilog (#207870)
|
2026-07-06 18:26:05 -07:00 |
|
rem-by-const.ll
|
[AArch64][GlobalISel] Improve multiplication with multiple registers (#197943)
|
2026-05-16 20:47:25 +02:00 |
|
rem.ll
|
[AArch64] Use dup (lane mov) over ext for high-half extract (#195010)
|
2026-05-11 07:31:59 +00:00 |
|
rem_crash.ll
|
|
|
|
remat-const-float-simd.ll
|
|
|
|
remat-float0.ll
|
|
|
|
remat-fmov-vector-imm.mir
|
[AMDGPU][NFC] Update MIR tests to use symbolic INLINEASM operands (#186839)
|
2026-04-17 12:23:56 +01:00 |
|
remat.ll
|
|
|
|
replace-load-with-shrink-store-indexed-crash.ll
|
|
|
|
replace-with-veclib-armpl.ll
|
|
|
|
replace-with-veclib-libmvec-scalable.ll
|
|
|
|
replace-with-veclib-libmvec.ll
|
|
|
|
replace-with-veclib-sleef-scalable.ll
|
|
|
|
replace-with-veclib-sleef.ll
|
|
|
|
reserveXreg-for-regalloc.ll
|
|
|
|
reserveXreg.ll
|
|
|
|
returnaddr.ll
|
|
|
|
rm_redundant_cmp.ll
|
|
|
|
rmif-def-nzcv.mir
|
|
|
|
rmif-use-nzcv.mir
|
|
|
|
rotate-extract.ll
|
|
|
|
rotate.ll
|
|
|
|
round-conv.ll
|
|
|
|
round-fptosi-sat-scalar.ll
|
[AArch64][GlobalISel] Legalization for bf16 fptosi.sat/fptoui.sat (#209378)
|
2026-07-14 06:27:03 +00:00 |
|
round-fptoui-sat-scalar.ll
|
[AArch64][GlobalISel] Legalization for bf16 fptosi.sat/fptoui.sat (#209378)
|
2026-07-14 06:27:03 +00:00 |
|
rqshrn.ll
|
|
|
|
rvmarker-pseudo-expansion-and-outlining.mir
|
|
|
|
sadd_sat.ll
|
|
|
|
sadd_sat_plus.ll
|
|
|
|
sadd_sat_vec.ll
|
[AArch64][GlobalISel] Fold buildvector of bitcast (#141553)
|
2026-05-16 16:30:15 +01:00 |
|
safestack_scalar.ll
|
|
|
|
sanitize_vec_pow.ll
|
[AArch64] Sanitise pow inputs using a target DAG combine (#192958)
|
2026-04-27 09:43:55 +01:00 |
|
sat-add.ll
|
|
|
|
sat-trunc-knownbits.ll
|
|
|
|
saturating-vec-smull.ll
|
|
|
|
sbc-add-constant.ll
|
[AArch64][DAG] Port adde and sube combine to AArch64 (#202227)
|
2026-07-08 10:26:13 +01:00 |
|
sbc.ll
|
[AArch64] Extend SBC combine to handle CSET HI (#192708)
|
2026-05-01 08:59:37 +01:00 |
|
scalable-expanding-load.ll
|
[AArch64] Lower masked.expandload intrinsic using SVE2p2/SME2p2 EXPAND (#190999)
|
2026-04-20 11:06:34 +01:00 |
|
scalable-vector-promotion.ll
|
|
|
|
scalable_masked_deinterleaved_loads.ll
|
|
|
|
scalable_masked_interleaved_stores.ll
|
[AArch64] Add combine for interleave deinterleave (#208414)
|
2026-07-20 09:39:13 +01:00 |
|
scalar-mla-mls.ll
|
|
|
|
scalarize-vector-load.ll
|
|
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scavenge-large-call.ll
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sched-loop-align.ll
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sched-movprfx.ll
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sched-past-vector-ldst.ll
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sched-postidxalias.mir
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sched-print-cycle.mir
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scheduledag-constreg.mir
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scmp.ll
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scvtf-div-mul-combine.ll
|
[AArch64] Optimize vector fmul(sitofp/uitofp, 1/2^N) -> scvtf/ucvtf (#141480)
|
2026-04-26 19:04:03 +01:00 |
|
sdag-no-typesize-warnings-regandsizes.ll
|
[DebugInfo] Enforce DISubprogram type as required in LLParser (#196299)
|
2026-05-13 15:40:07 +01:00 |
|
sdag-store-merging-bug.ll
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sdiv-by-const-promoted-ops.ll
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sdivpow2.ll
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seh-extended-spills.ll
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seh-finally.ll
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seh-minimal-prologue-epilogue.ll
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seh-unreachable-loop.mir
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seh_funclet_x1.ll
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select-bitcast.ll
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select-constant-xor.ll
|
[AArch64][GlobalISel] Port shouldBeAdjustedToZero to GlobalISel (#195941)
|
2026-06-04 05:18:17 +00:00 |
|
select-to-and-zext.ll
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select-with-and-or.ll
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select_cc.ll
|
[AArch64][GlobalISel] Match G_DUP with undef elements (#195237)
|
2026-05-05 08:33:22 +01:00 |
|
select_const.ll
|
[AArch64][GlobalISel] FP Info implementation for AArch64. (#177158)
|
2026-04-20 09:38:16 +01:00 |
|
select_fmf.ll
|
[SelectionDAG] Stop forming minnum/maxnum in SDAGBuilder (#187738)
|
2026-07-27 09:54:42 +02:00 |
|
select_of_select.ll
|
[AArch64] Add a test for select-of-select with the same condition. NFC (#197903)
|
2026-05-15 11:40:14 +01:00 |
|
selectcc-to-shiftand.ll
|
|
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|
selectiondag-order.ll
|
[DebugInfo] Enforce DISubprogram type as required in LLParser (#196299)
|
2026-05-13 15:40:07 +01:00 |
|
selectopt-cast.ll
|
[SelectOpt] Preserve Profile Information (#200680)
|
2026-06-01 20:48:14 +00:00 |
|
selectopt-const.ll
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selectopt-logical.ll
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selectopt-not.ll
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selectopt.ll
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semantic-interposition-asm.ll
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semantic-interposition-memtag.ll
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seqpaircopy.mir
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seqpairspill.mir
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setcc-fsh.ll
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setcc-redundant-cmlt.ll
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setcc-takes-i32.ll
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setcc-type-mismatch.ll
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setcc_knownbits.ll
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setf8-def-nzcv.mir
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setf8-use-nzcv.mir
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setf16-def-nzcv.mir
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setf16-use-nzcv.mir
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setjmp-bti-no-enforcement.ll
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setjmp-bti-outliner.ll
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setjmp-bti.ll
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settag-merge-nonaligned-fp.ll
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settag-merge-order.ll
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settag-merge.ll
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settag-merge.mir
|
[CodeGen] Rename prologpeilog to prolog-epilog (#207870)
|
2026-07-06 18:26:05 -07:00 |
|
settag.ll
|
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sext.ll
|
[AArch64] Use dup (lane mov) over ext for high-half extract (#195010)
|
2026-05-11 07:31:59 +00:00 |
|
shadow-call-stack.ll
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shift-accumulate.ll
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shift-amount-mod.ll
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shift-by-signext.ll
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shift-const-ne-0.ll
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shift-i256.ll
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shift-logic.ll
|
[AArch64][GlobalISel] Normalize and cleanup some test checks. NFC (#195016)
|
2026-04-30 07:35:34 +01:00 |
|
shift-mod.ll
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shift.ll
|
[AArch64][GlobalISel] Lower unmerge to extract_subvector (#195046)
|
2026-05-05 17:39:07 +01:00 |
|
shift_minsize.ll
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shiftregister-from-and.ll
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shl-to-add.ll
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shr-exact-demanded-bits.ll
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shrink-constant-multiple-users.ll
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shrink-wrap-byval-inalloca-preallocated.ll
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shrink-wrap-const-pool-access.mir
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shrink-wrap-unreachable.ll
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shrink-wrap.ll
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shrink-wrapping-vla.ll
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shrinkwrap-split-restore-point.mir
|
[AMDGPU][NFC] Update MIR tests to use symbolic INLINEASM operands (#186839)
|
2026-04-17 12:23:56 +01:00 |
|
shuffle-extend.ll
|
[AArch64][GlobalISel] Add more shuffle test coverage. NFC (#207907)
|
2026-07-07 07:45:00 +01:00 |
|
shuffle-mask-legal.ll
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shuffle-select.ll
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shuffle-slide-to-shift.ll
|
[AArch64][GlobalISel] Fold G_SHUFFLE to single-element TBL with zero elements. (#200938)
|
2026-07-11 08:12:13 +01:00 |
|
shuffle-tbl34.ll
|
[AArch64][GlobalISel] Fold G_SHUFFLE to single-element TBL with zero elements. (#200938)
|
2026-07-11 08:12:13 +01:00 |
|
shuffles.ll
|
[AArch64][GlobalISel] Fold G_SHUFFLE to single-element TBL with zero elements. (#200938)
|
2026-07-11 08:12:13 +01:00 |
|
shufflevector.ll
|
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sibling-call.ll
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sign-return-address-cfi-negate-ra-state.ll
|
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sign-return-address-pauth-lr-mir.ll
|
[llvm][AArch64] Enable .cfi_set_ra_state by default for PAuth_LR (#211698)
|
2026-07-23 17:10:19 -07:00 |
|
sign-return-address-pauth-lr.ll
|
[llvm][AArch64] Add a test for -aarch64-cfi-llvm-set-ra-sign-state='s default (#211791)
|
2026-07-24 06:43:48 -07:00 |
|
sign-return-address-pauthlr-slh.ll
|
[llvm][AArch64] Enable .cfi_set_ra_state by default for PAuth_LR (#211698)
|
2026-07-23 17:10:19 -07:00 |
|
sign-return-address-tailcall.ll
|
|
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|
sign-return-address.ll
|
[MC][AArch64] Add .cfi_set_ra_state for PAuth_LR (#209949)
|
2026-07-21 14:22:36 -07:00 |
|
signbit-shift.ll
|
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signbit-test.ll
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signed-truncation-check.ll
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simple-macho.ll
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sincos-expansion.ll
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sincos-stack-slots.ll
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sink-addsub-of-const.ll
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sink-and-fold-clear-kill-flags.mir
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sink-and-fold-drop-dbg.mir
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sink-and-fold-illegal-shift.mir
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sink-and-fold-preserve-debugloc.mir
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sink-and-fold-unique-operand.mir
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sink-and-fold.ll
|
[SCEVExp] Use Builder.CreateBinOp in InsertBinOp. (#154148)
|
2026-04-25 17:08:20 +01:00 |
|
sink-copy-for-shrink-wrap.ll
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sink-fneg.ll
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sink-mul-exts.ll
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sinksplat.ll
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sitofp-to-tbl.ll
|
[Test] Fix loop exit conditions to prevent trivial optimizations (#201867)
|
2026-06-05 16:19:14 +00:00 |
|
sls-crash.ll
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|
sls-stackprotector-outliner.ll
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smax-allones.ll
|
[DAGCombiner] Fold smax(X, -1)/smin(X, 0) to bitwise shift forms (#206242)
|
2026-07-08 13:11:20 +00:00 |
|
sme-aarch64-svcount-O3.ll
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|
sme-aarch64-svcount.ll
|
[AArch64] Fold any/sign-extend of CSET. (#207414)
|
2026-07-08 10:34:12 +01:00 |
|
sme-abi-debug.ll
|
[AArch64] Do not pass debug insn to liveness analysis (#197989)
|
2026-05-15 20:20:45 +01:00 |
|
sme-abi-eh-liveins.mir
|
Revert "[AArch64] Fix definition of system register move instructions" (#201137)
|
2026-06-02 16:44:37 +01:00 |
|
sme-abi-save-call-remarks.ll
|
[AArch64][SME] Remove SelectionDAG SME ABI lowering (#190950)
|
2026-04-13 09:52:18 +01:00 |
|
sme-agnostic-za-without-sme.ll
|
|
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|
sme-agnostic-za.ll
|
[AArch64][SME] Remove SelectionDAG SME ABI lowering (#190950)
|
2026-04-13 09:52:18 +01:00 |
|
sme-avoid-coalescing-locally-streaming.ll
|
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sme-call-streaming-compatible-to-normal-fn-wihout-sme-attr.ll
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sme-callee-save-restore-pairs.ll
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sme-darwin-no-sve-vg.ll
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sme-darwin-sve-vg.ll
|
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sme-disable-gisel-fisel.ll
|
[AArch64] Fix broken SME code with GlobalISel (#191140)
|
2026-04-09 13:27:06 +01:00 |
|
sme-disable-rematerialize-with-streaming-mode-changes.ll
|
|
|
|
sme-dynamic-tls.ll
|
[AArch64][SME] Remove SelectionDAG SME ABI lowering (#190950)
|
2026-04-13 09:52:18 +01:00 |
|
sme-framelower-use-bp.ll
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sme-intrinsics-add.ll
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sme-intrinsics-loads.ll
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sme-intrinsics-mopa.ll
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sme-intrinsics-mops.ll
|
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sme-intrinsics-mova-extract.ll
|
|
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|
sme-intrinsics-mova-insert.ll
|
[AArch64] Avoid creating a new generic constant in SelectSMETileSlice (#203344)
|
2026-06-12 17:46:23 +01:00 |
|
sme-intrinsics-rdsvl.ll
|
|
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|
sme-intrinsics-state.ll
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sme-intrinsics-stores.ll
|
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sme-intrinsics-zero.ll
|
|
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|
sme-lazy-save-call.ll
|
[AArch64][SME] Remove SelectionDAG SME ABI lowering (#190950)
|
2026-04-13 09:52:18 +01:00 |
|
sme-lazy-save-windows.ll
|
[AArch64][SME] Remove SelectionDAG SME ABI lowering (#190950)
|
2026-04-13 09:52:18 +01:00 |
|
sme-lazy-sve-nzcv-live.mir
|
Revert "[AArch64] Fix definition of system register move instructions" (#201137)
|
2026-06-02 16:44:37 +01:00 |
|
sme-machine-licm-vg.mir
|
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sme-must-save-lr-for-vg.ll
|
|
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|
sme-new-za-function.ll
|
[AArch64][SME] Remove SelectionDAG SME ABI lowering (#190950)
|
2026-04-13 09:52:18 +01:00 |
|
sme-new-za-zt0-no-tail-call.ll
|
|
|
|
sme-peephole-opts.ll
|
[AArch64][SME] Elide private ZA setup when possible (#196090)
|
2026-05-08 09:31:16 +01:00 |
|
sme-pstate-sm-changing-call-disable-coalescing.ll
|
[AArch64][SVE] Add more MOVPRFX pseudos for SVE immediate instructions. (#192491)
|
2026-04-20 14:55:54 +01:00 |
|
sme-read-write-tpidr2.ll
|
|
|
|
sme-shared-za-interface.ll
|
[AArch64][SME] Remove SelectionDAG SME ABI lowering (#190950)
|
2026-04-13 09:52:18 +01:00 |
|
sme-streaming-body-streaming-compatible-interface.ll
|
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|
sme-streaming-body.ll
|
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sme-streaming-checkvl-mir.ll
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|
sme-streaming-checkvl.ll
|
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|
sme-streaming-compatible-interface.ll
|
|
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|
sme-streaming-interface-remarks.ll
|
|
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|
sme-streaming-interface.ll
|
|
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|
sme-streaming-mode-changes-unwindinfo.ll
|
|
|
|
sme-streaming-mode-changing-call-disable-stackslot-scavenging.ll
|
|
|
|
sme-streaming-mode-fpr-copy.ll
|
|
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|
sme-streaming-mode-landingpads.ll
|
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|
sme-support-routines-calling-convention.ll
|
|
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|
sme-tileslice-addrmodes.ll
|
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|
sme-toggle-pstateza.ll
|
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|
sme-vg-to-stack.ll
|
|
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|
sme-write-fpmr.ll
|
|
|
|
sme-write-vg.ll
|
|
|
|
sme-za-control-flow.ll
|
[AArch64][SME] Remove SelectionDAG SME ABI lowering (#190950)
|
2026-04-13 09:52:18 +01:00 |
|
sme-za-exceptions.ll
|
[AArch64][SME] Remove SelectionDAG SME ABI lowering (#190950)
|
2026-04-13 09:52:18 +01:00 |
|
sme-za-function-with-many-blocks.ll
|
[AArch64][SME] Remove SelectionDAG SME ABI lowering (#190950)
|
2026-04-13 09:52:18 +01:00 |
|
sme-za-lazy-save-buffer.ll
|
[AArch64][SME] Remove SelectionDAG SME ABI lowering (#190950)
|
2026-04-13 09:52:18 +01:00 |
|
sme-zt0-state.ll
|
[AArch64][SME] Elide private ZA setup when possible (#196090)
|
2026-05-08 09:31:16 +01:00 |
|
sme2-fp8-intrinsics-cvt.ll
|
|
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sme2-fp8-intrinsics-fmopa.ll
|
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sme2-fp8-intrinsics-mla.ll
|
|
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sme2-intrinsics-add-sub-za16.ll
|
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sme2-intrinsics-add.ll
|
|
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|
sme2-intrinsics-bfmul.ll
|
|
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|
sme2-intrinsics-bfscale.ll
|
|
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|
sme2-intrinsics-cvt.ll
|
|
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|
sme2-intrinsics-cvtl.ll
|
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sme2-intrinsics-cvtn.ll
|
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sme2-intrinsics-extract-mova.ll
|
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sme2-intrinsics-faminmax.ll
|
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sme2-intrinsics-fclamp.ll
|
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sme2-intrinsics-fmlas.ll
|
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sme2-intrinsics-fmlas16.ll
|
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sme2-intrinsics-fp-dots.ll
|
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sme2-intrinsics-fp8-fdot.ll
|
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sme2-intrinsics-fp8-fvdot.ll
|
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sme2-intrinsics-frint.ll
|
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sme2-intrinsics-fscale.ll
|
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sme2-intrinsics-insert-mova.ll
|
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sme2-intrinsics-int-dots.ll
|
|
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sme2-intrinsics-ld1.ll
|
|
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sme2-intrinsics-ldnt1.ll
|
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sme2-intrinsics-luti2-lane-x2.ll
|
|
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sme2-intrinsics-luti2-lane-x4.ll
|
|
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|
sme2-intrinsics-luti2-lane.ll
|
|
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sme2-intrinsics-luti4-lane-x2.ll
|
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sme2-intrinsics-luti4-lane-x4.ll
|
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sme2-intrinsics-luti4-lane.ll
|
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sme2-intrinsics-luti4.ll
|
|
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sme2-intrinsics-max.ll
|
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sme2-intrinsics-min.ll
|
|
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sme2-intrinsics-mlall.ll
|
|
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|
sme2-intrinsics-mlals.ll
|
|
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|
sme2-intrinsics-mop.ll
|
|
|
|
sme2-intrinsics-mop4-fp8.ll
|
|
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sme2-intrinsics-mop4a_1x1.ll
|
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sme2-intrinsics-mop4a_1x2.ll
|
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sme2-intrinsics-mop4a_2x1.ll
|
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sme2-intrinsics-mop4a_2x2.ll
|
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sme2-intrinsics-mopa.ll
|
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sme2-intrinsics-qcvt.ll
|
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sme2-intrinsics-qcvtn.ll
|
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sme2-intrinsics-qrshr.ll
|
|
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sme2-intrinsics-rshl.ll
|
|
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|
sme2-intrinsics-sclamp.ll
|
|
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|
sme2-intrinsics-select-sme-tileslice.ll
|
|
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|
sme2-intrinsics-sqdmulh.ll
|
|
|
|
sme2-intrinsics-sub.ll
|
|
|
|
sme2-intrinsics-tmop.ll
|
[AArch64][SME] Split FP8 FTMOPA intrinsics (#203310)
|
2026-06-15 10:23:13 +01:00 |
|
sme2-intrinsics-uclamp.ll
|
|
|
|
sme2-intrinsics-vdot.ll
|
|
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sme2-intrinsics-write-zt.ll
|
|
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sme2-intrinsics-zero-zt.ll
|
|
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|
sme2-intrinsics-zt0.ll
|
|
|
|
sme2-multivec-regalloc.mir
|
[AArch64] Expand FORM_TRANSPOSED_REG_TUPLE to copies before regalloc (#207205)
|
2026-07-09 09:01:56 +01:00 |
|
sme2p1-intrinsics-movaz.ll
|
[LLVM][Verifier] Move intrinsic signature verification to declarations (#204478)
|
2026-06-29 06:57:16 -07:00 |
|
sme2p1-intrinsics-zero.ll
|
|
|
|
sme2p2-intrinsics-fmul.ll
|
|
|
|
sme2p3-intrinsics-luti6.ll
|
[AArch64][clang][llvm] Add ACLE Armv9.7 lookup table intrinsics (#187046)
|
2026-06-12 16:47:16 +01:00 |
|
sminp-smaxp.ll
|
|
|
|
sms-acceptable-loop1.mir
|
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sms-acceptable-loop2.mir
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sms-acceptable-loop3.mir
|
|
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sms-acceptable-loop4.mir
|
|
|
|
sms-analyzeloop-remarks.mir
|
[llvm][AArch64] Add pipeliner remarks (#213157)
|
2026-07-31 07:55:27 -07:00 |
|
sms-loop-carried-fp-exceptions1.mir
|
[IR] Make semantics of strictfp consistent v2 (#211769)
|
2026-07-24 18:02:54 +00:00 |
|
sms-loop-carried-fp-exceptions2.mir
|
|
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sms-mve1.mir
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sms-mve2.mir
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sms-mve3.mir
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sms-mve4.mir
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sms-mve5.mir
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sms-mve6.mir
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sms-mve7.mir
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sms-mve8.mir
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sms-mve9.mir
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sms-mve10.mir
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sms-mve11.mir
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sms-mve12.mir
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sms-order-physreg-deps.mir
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sms-regpress.mir
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sms-schedule-remark.mir
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[llvm][AArch64] Add pipeliner remarks (#213157)
|
2026-07-31 07:55:27 -07:00 |
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sms-unacceptable-loop1.mir
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sms-unacceptable-loop2.mir
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sms-unacceptable-loop3.mir
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sms-unpipeline-insts1.mir
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sms-unpipeline-insts2.mir
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sms-unpipeline-insts3.mir
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smul_fix.ll
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[AArch64][GlobalISel] Update and cleanup s/umul.fix tests. NFC (#211232)
|
2026-07-22 12:05:54 +01:00 |
|
smul_fix_sat.ll
|
[SelectionDAG][AArch64][X86] Don't scalarize vector smul.fix.sat/umul.fix.sat (#209351)
|
2026-07-23 12:11:04 +00:00 |
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soft-float-abi.ll
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space.ll
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special-reg.ll
|
Revert "[AArch64] Fix definition of system register move instructions" (#201137)
|
2026-06-02 16:44:37 +01:00 |
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speculation-hardening-dagisel.ll
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speculation-hardening-loads.ll
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speculation-hardening-sls-blr-bti.mir
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speculation-hardening-sls-blr.mir
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speculation-hardening-sls-blra.mir
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speculation-hardening-sls.ll
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speculation-hardening-sls.mir
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speculation-hardening.ll
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speculation-hardening.mir
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spill-fold.ll
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spill-fold.mir
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spill-reload-remarks.ll
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spill-stack-realignment.mir
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[CodeGen] Rename prologpeilog to prolog-epilog (#207870)
|
2026-07-06 18:26:05 -07:00 |
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spill-undef.mir
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spillfill-sve.ll
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[LLVM][CodeGen] Remove +bf16 for ARM/AArch64 tests that don't strictly need the feature flag. (#204199)
|
2026-06-23 12:29:11 +01:00 |
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spillfill-sve.mir
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split-deadloop.mir
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split-sve-stack-frame-layout.ll
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split-vector-insert.ll
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sponentry.ll
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sqrt-fastmath.ll
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[AArch64][GlobalISel] Protect against fdiv of 1 (#184063)
|
2026-05-06 11:52:43 +01:00 |
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srem-lkk.ll
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srem-pow2.ll
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srem-seteq-illegal-types.ll
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srem-seteq-optsize.ll
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srem-seteq-vec-nonsplat.ll
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srem-seteq-vec-splat.ll
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srem-seteq.ll
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srem-vec-crash.ll
|
[GlobalISel] Add srem-by-pow2 combine to intrem_combines (#194673)
|
2026-05-13 08:17:27 -07:00 |
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srem-vector-lkk.ll
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sshl_sat.ll
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[DAG] Fold any-extend(and(trunc(x), C)) -> and(x, C) (#200052)
|
2026-06-03 17:48:40 +02:00 |
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ssub_sat.ll
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ssub_sat_plus.ll
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ssub_sat_vec.ll
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[AArch64][GlobalISel] Fold buildvector of bitcast (#141553)
|
2026-05-16 16:30:15 +01:00 |
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ssve-stack-hazard-remarks.ll
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st1-lane.ll
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[AArch64] Use dup (lane mov) over ext for high-half extract (#195010)
|
2026-05-11 07:31:59 +00:00 |
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stack-guard-reassign-sve.mir
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[CodeGen] Rename prologpeilog to prolog-epilog (#207870)
|
2026-07-06 18:26:05 -07:00 |
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stack-guard-reassign.ll
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stack-guard-reassign.mir
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[CodeGen] Rename prologpeilog to prolog-epilog (#207870)
|
2026-07-06 18:26:05 -07:00 |
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stack-guard-remat-bitcast.ll
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stack-guard-sve.ll
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[AArch64] Optimise materialisation of large stack offset calculations (#201856)
|
2026-06-24 15:02:00 +01:00 |
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stack-guard-sysreg.ll
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stack-guard-vaarg.ll
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stack-guard-width.ll
|
[AArch64] Support 4-byte stack protector with large code model. (#205956)
|
2026-07-06 13:52:50 -07:00 |
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stack-hazard-defaults.ll
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stack-hazard-windows.ll
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stack-hazard.ll
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stack-id-pei-alloc.mir
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[CodeGen] Rename prologpeilog to prolog-epilog (#207870)
|
2026-07-06 18:26:05 -07:00 |
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stack-id-stackslot-scavenging.mir
|
[CodeGen] Rename prologpeilog to prolog-epilog (#207870)
|
2026-07-06 18:26:05 -07:00 |
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stack-probing-64k.ll
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stack-probing-dynamic-no-frame-setup.ll
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stack-probing-dynamic.ll
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[AArch64] Do not generate indexed addressing mode for volatile accesses (#196305)
|
2026-05-28 13:08:05 +00:00 |
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stack-probing-last-in-block.mir
|
[CodeGen] Rename prologpeilog to prolog-epilog (#207870)
|
2026-07-06 18:26:05 -07:00 |
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stack-probing-no-scratch-reg.mir
|
[CodeGen] Rename prologpeilog to prolog-epilog (#207870)
|
2026-07-06 18:26:05 -07:00 |
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stack-probing-shrink-wrap.mir
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[CodeGen] Rename prologpeilog to prolog-epilog (#207870)
|
2026-07-06 18:26:05 -07:00 |
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stack-probing-sve.ll
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stack-probing.ll
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stack-protector-darwin-got.ll
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stack-protector-metadata.ll
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stack-protector-musttail.ll
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stack-protector-target.ll
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[aarch64] Mix the frame pointer with the stack cookie when protecting the stack (#197346)
|
2026-07-01 15:33:56 +08:00 |
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stack-protector-trap-unreachable.ll
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stack-size-section.ll
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stack-tagging-cfi.ll
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stack-tagging-dbg-assign-tag-offset.ll
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stack-tagging-dbg-declare-tag-offset.ll
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stack-tagging-dbg-value-tag-offset-nopad.ll
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stack-tagging-dbg-value-tag-offset.ll
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stack-tagging-dbg.ll
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stack-tagging-epilogue-fold.mir
|
[CodeGen] Rename prologpeilog to prolog-epilog (#207870)
|
2026-07-06 18:26:05 -07:00 |
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stack-tagging-ex-1.ll
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stack-tagging-ex-2.ll
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stack-tagging-initializer-merge.ll
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stack-tagging-loop.ll
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stack-tagging-merge-past-memcpy.mir
|
[CodeGen] Rename prologpeilog to prolog-epilog (#207870)
|
2026-07-06 18:26:05 -07:00 |
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stack-tagging-musttail.ll
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stack-tagging-prologue.ll
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stack-tagging-setjmp.ll
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stack-tagging-split-lifetime.ll
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stack-tagging-stack-coloring.ll
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stack-tagging-unchecked-ld-st.ll
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stack-tagging-untag-placement.ll
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stack-tagging.ll
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stack_guard_remat.ll
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stackaddress.ll
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stackguard-internal.ll
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stackmap-args.ll
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stackmap-dynamic-alloca.ll
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stackmap-frame-setup.ll
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stackmap-liveness.ll
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stackmap.ll
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stacksmash-arm64ec.ll
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statepoint-call-lowering-lr.ll
|
[CodeGen] Rename prologpeilog to prolog-epilog (#207870)
|
2026-07-06 18:26:05 -07:00 |
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statepoint-call-lowering-sp.ll
|
[CodeGen] Rename prologpeilog to prolog-epilog (#207870)
|
2026-07-06 18:26:05 -07:00 |
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statepoint-call-lowering.ll
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statepoint-twoaddr.mir
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stgp.ll
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store-float-conversion.ll
|
[AArch64] Improve post-inc stores of SIMD/FP values (#151372)
|
2026-05-10 18:04:42 +03:00 |
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store-swift-async-context-clobber-live-reg.ll
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store.ll
|
[AArch64][GlobalISel] FP Info implementation for AArch64. (#177158)
|
2026-04-20 09:38:16 +01:00 |
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store_merge_pair_offset.ll
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storepairsuppress.ll
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storepairsuppress_minsize.ll
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stp-opt-with-renaming-debug.mir
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stp-opt-with-renaming-ld3.mir
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stp-opt-with-renaming-reserved-regs.mir
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stp-opt-with-renaming-undef-assert.mir
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stp-opt-with-renaming.mir
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[AArch64] Remove assembler-only register classes (#211527)
|
2026-07-30 08:43:53 +01:00 |
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str-narrow-zero-merge.mir
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streaming-compatible-memory-ops.ll
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streaming-func-no-sme.ll
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strict-fp-func.ll
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strict-fp-int-promote.ll
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strict-fp-opt.ll
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strictfp-inlineasm.ll
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strictfp_f16_abi_promote.ll
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strpre-str-merge.mir
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strqro.ll
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strqu.ll
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sub-of-bias.ll
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sub-of-not.ll
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sub-splat-sub.ll
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sub.ll
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[AArch64][GlobalISel] Fold buildvector of bitcast (#141553)
|
2026-05-16 16:30:15 +01:00 |
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sub1.ll
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subreg-liveness-fix-subreg-to-reg-implicit-def.mir
|
[NewPM][AArch64] Port AArch64SRLTDefineSuperRegs pass to NewPassManager (#202803)
|
2026-06-24 22:24:11 -07:00 |
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subreg_to_reg_coalescing_issue.mir
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subs-to-sub-opt.ll
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sve-aba.ll
|
[NFC][LLVM][Tests] Replace instances of @llvm.aarch64.sve.ptrue.nxv16i1(i32 31) with splat (i1 true). (#204113)
|
2026-06-16 12:44:06 +01:00 |
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sve-abd.ll
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sve-adr.ll
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sve-aliasing.ll
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sve-aliasing.mir
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sve-alloca-stackid.ll
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sve-alloca.ll
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sve-asrd.ll
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sve-bad-intrinsics.ll
|
[LLVM][Verifier] Move intrinsic signature verification to declarations (#204478)
|
2026-06-29 06:57:16 -07:00 |
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sve-bad-select.ll
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sve-bf16-arith.ll
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sve-bf16-combines.ll
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sve-bf16-compares.ll
|
[AArch64] Hint regalloc to choose distinct predicate for MATCH/CMP (#190139)
|
2026-04-14 09:40:50 +01:00 |
|
sve-bf16-converts.ll
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sve-bf16-int-converts.ll
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sve-bf16-reductions.ll
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sve-bf16-rounding.ll
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sve-bit-counting-pred.ll
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sve-bit-counting.ll
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sve-bitcast.ll
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sve-breakdown-scalable-vectortype.ll
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sve-callbyref-notailcall.ll
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sve-callee-save-restore-pairs.ll
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sve-calling-convention-byref.ll
|
[LLVM][CodeGen][SVE] Make use of predicate load/store "mul vl" addressing mode. (#206997)
|
2026-07-08 12:25:53 +01:00 |
|
sve-calling-convention-mixed.ll
|
[NFC][LLVM][Tests] Replace instances of @llvm.aarch64.sve.ptrue.nxv16i1(i32 31) with splat (i1 true). (#204113)
|
2026-06-16 12:44:06 +01:00 |
|
sve-calling-convention.ll
|
[CodeGen] Rename prologpeilog to prolog-epilog (#207870)
|
2026-07-06 18:26:05 -07:00 |
|
sve-cmp-folds.ll
|
[LLVM][CodeGen][SVE] Add isel for zext(setcc(x,0,ne)) -> umin(x,1). (#209452)
|
2026-07-14 14:22:21 +01:00 |
|
sve-cmp-select.ll
|
[AArch64] Hint regalloc to choose distinct predicate for MATCH/CMP (#190139)
|
2026-04-14 09:40:50 +01:00 |
|
sve-cntp-combine-i32.ll
|
[NFC][LLVM][Tests] Replace instances of @llvm.aarch64.sve.ptrue.nxv16i1(i32 31) with splat (i1 true). (#204113)
|
2026-06-16 12:44:06 +01:00 |
|
sve-cntp-combine-i64.ll
|
[NFC][LLVM][Tests] Replace instances of @llvm.aarch64.sve.ptrue.nxv16i1(i32 31) with splat (i1 true). (#204113)
|
2026-06-16 12:44:06 +01:00 |
|
sve-copy-zprpair.mir
|
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sve-dead-masked-store.ll
|
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sve-distinct-predicate-dst.ll
|
[AArch64] Hint regalloc to choose distinct predicate for MATCH/CMP (#190139)
|
2026-04-14 09:40:50 +01:00 |
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sve-doublereduct.ll
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sve-expand-div.ll
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sve-extload-icmp.ll
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sve-extract-element.ll
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sve-extract-fixed-from-scalable-vector.ll
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sve-extract-fixed-vector.ll
|
[LLVM][CodeGen] Remove +bf16 for ARM/AArch64 tests that don't strictly need the feature flag. (#204199)
|
2026-06-23 12:29:11 +01:00 |
|
sve-extract-scalable-vector.ll
|
[LLVM][CodeGen] Remove +bf16 for ARM/AArch64 tests that don't strictly need the feature flag. (#204199)
|
2026-06-23 12:29:11 +01:00 |
|
sve-extract-vector-to-predicate-store.ll
|
[LLVM][CodeGen][SVE] Reimplement SVE VLS predicate load/store transformation as DAG combines. (#203314)
|
2026-06-15 12:09:33 +01:00 |
|
sve-fadda-select.ll
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|
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sve-fcmp.ll
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sve-fcopysign.ll
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sve-fcvt.ll
|
[AArch64] Hint regalloc to choose distinct predicate for MATCH/CMP (#190139)
|
2026-04-14 09:40:50 +01:00 |
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sve-fix-length-and-combine-512.ll
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|
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sve-fixed-ld2-alloca.ll
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sve-fixed-length-addressing-modes.ll
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sve-fixed-length-bf16-vselect.ll
|
[LLVM][CodeGen] Clean up uses of useSVEForFixedLengthVectorVT(). (#211605)
|
2026-07-28 13:45:54 +01:00 |
|
sve-fixed-length-bit-counting.ll
|
[AArch64] Improve fixed vector lowering for cttz/ctlz when sve (#192427)
|
2026-05-12 09:18:57 +05:30 |
|
sve-fixed-length-bitcast.ll
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sve-fixed-length-bitselect.ll
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sve-fixed-length-build-vector.ll
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sve-fixed-length-concat.ll
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sve-fixed-length-ext-loads.ll
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sve-fixed-length-extract-subvector.ll
|
[AArch64] Use dup (lane mov) over ext for high-half extract (#195010)
|
2026-05-11 07:31:59 +00:00 |
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sve-fixed-length-extract-vector-elt.ll
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sve-fixed-length-fcopysign.ll
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sve-fixed-length-fp-arith.ll
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sve-fixed-length-fp-compares.ll
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[AArch64][DAG] Use getSetCCResultType in PromoteSETCC (#198320)
|
2026-05-26 17:46:31 +01:00 |
|
sve-fixed-length-fp-convert.ll
|
|
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sve-fixed-length-fp-extend-bf16.ll
|
[AArch64] Lower fixed width bf16 fpround (#209411)
|
2026-07-15 21:19:55 +01:00 |
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sve-fixed-length-fp-extend-trunc.ll
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sve-fixed-length-fp-fma.ll
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sve-fixed-length-fp-minmax.ll
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sve-fixed-length-fp-reduce.ll
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sve-fixed-length-fp-rounding.ll
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sve-fixed-length-fp-select.ll
|
[AArch64] Hint regalloc to choose distinct predicate for MATCH/CMP (#190139)
|
2026-04-14 09:40:50 +01:00 |
|
sve-fixed-length-fp-to-int-sat.ll
|
[AArch64] Add SVE lowering for FP_TO_[US]INT_SAT. (#207201)
|
2026-07-23 09:32:02 +01:00 |
|
sve-fixed-length-fp-to-int.ll
|
[AArch64] Use dup (lane mov) over ext for high-half extract (#195010)
|
2026-05-11 07:31:59 +00:00 |
|
sve-fixed-length-fp-trunc-bf16.ll
|
[AArch64] Lower fixed width bf16 fpround (#209411)
|
2026-07-15 21:19:55 +01:00 |
|
sve-fixed-length-fp-vselect.ll
|
|
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sve-fixed-length-fp128.ll
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sve-fixed-length-fptrunc.ll
|
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sve-fixed-length-frame-offests-crash.ll
|
|
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sve-fixed-length-frame-offests.ll
|
DAG: Stop legalizing poison to undef (#211890)
|
2026-07-25 20:39:49 +02:00 |
|
sve-fixed-length-frintz.ll
|
[SelectionDAG] Remove the remaining NoSignedZerosFPMath use (#201535)
|
2026-06-05 11:48:05 +00:00 |
|
sve-fixed-length-function-calls.ll
|
|
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sve-fixed-length-functions.ll
|
|
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sve-fixed-length-insert-vector-elt.ll
|
[AArch64] Hint regalloc to choose distinct predicate for MATCH/CMP (#190139)
|
2026-04-14 09:40:50 +01:00 |
|
sve-fixed-length-int-abd.ll
|
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sve-fixed-length-int-arith.ll
|
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sve-fixed-length-int-compares.ll
|
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sve-fixed-length-int-div.ll
|
|
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sve-fixed-length-int-extends.ll
|
[AArch64] Use dup (lane mov) over ext for high-half extract (#195010)
|
2026-05-11 07:31:59 +00:00 |
|
sve-fixed-length-int-immediates.ll
|
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sve-fixed-length-int-log.ll
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sve-fixed-length-int-minmax.ll
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sve-fixed-length-int-mulh.ll
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sve-fixed-length-int-reduce.ll
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sve-fixed-length-int-rem.ll
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|
|
sve-fixed-length-int-select.ll
|
[AArch64] Hint regalloc to choose distinct predicate for MATCH/CMP (#190139)
|
2026-04-14 09:40:50 +01:00 |
|
sve-fixed-length-int-shifts.ll
|
|
|
|
sve-fixed-length-int-to-fp.ll
|
[LLVM][CodeGen][SVE] Extend NEON->SVE splat imm isel to cover 64-bit vectors. (#209833)
|
2026-07-22 11:01:27 +01:00 |
|
sve-fixed-length-int-vselect.ll
|
[AArch64] Hint regalloc to choose distinct predicate for MATCH/CMP (#190139)
|
2026-04-14 09:40:50 +01:00 |
|
sve-fixed-length-limit-duplane.ll
|
|
|
|
sve-fixed-length-loads-stores.ll
|
|
|
|
sve-fixed-length-log-reduce.ll
|
[AArch64][ISel] Use SVE for fixed width vector reductions (#195806)
|
2026-05-13 10:29:48 +01:00 |
|
sve-fixed-length-mask-opt.ll
|
|
|
|
sve-fixed-length-masked-64-128bit-loads.ll
|
[AArch64][SVE] Prefer SVE over scalarization for masked load/store of bf16 vectors (#210986)
|
2026-07-24 09:20:49 +08:00 |
|
sve-fixed-length-masked-64-128bit-stores.ll
|
[AArch64][SVE] Prefer SVE over scalarization for masked load/store of bf16 vectors (#210986)
|
2026-07-24 09:20:49 +08:00 |
|
sve-fixed-length-masked-div.ll
|
[LLVM][CodeGen][SVE] Add custom lowering for ISD::MASKED_SDIV/UDIV. (#191164)
|
2026-04-17 13:42:19 +01:00 |
|
sve-fixed-length-masked-expandloads.ll
|
[AArch64] Mark FIXED_REGS register class as non-allocatable (#212250)
|
2026-07-29 12:06:05 +01:00 |
|
sve-fixed-length-masked-gather.ll
|
[AArch64][SVE] Prefer SVE over scalarization for masked load/store of bf16 vectors (#210986)
|
2026-07-24 09:20:49 +08:00 |
|
sve-fixed-length-masked-loads.ll
|
[AArch64] Use dup (lane mov) over ext for high-half extract (#195010)
|
2026-05-11 07:31:59 +00:00 |
|
sve-fixed-length-masked-rem.ll
|
[LLVM][CodeGen][SVE] Add custom lowering for ISD::MASKED_SDIV/UDIV. (#191164)
|
2026-04-17 13:42:19 +01:00 |
|
sve-fixed-length-masked-scatter.ll
|
[AArch64][SVE] Prefer SVE over scalarization for masked load/store of bf16 vectors (#210986)
|
2026-07-24 09:20:49 +08:00 |
|
sve-fixed-length-masked-stores.ll
|
[AArch64] Hint regalloc to choose distinct predicate for MATCH/CMP (#190139)
|
2026-04-14 09:40:50 +01:00 |
|
sve-fixed-length-no-vscale-range.ll
|
|
|
|
sve-fixed-length-offsets.ll
|
|
|
|
sve-fixed-length-optimize-ptrue.ll
|
|
|
|
sve-fixed-length-partial-reduce.ll
|
[AArch64][SVE] Fix v16i8 -> v2i64 partial_reduce for VL > 128 (#204938)
|
2026-07-22 13:17:54 +01:00 |
|
sve-fixed-length-permute-rev.ll
|
|
|
|
sve-fixed-length-permute-zip-uzp-trn.ll
|
|
|
|
sve-fixed-length-ptest.ll
|
|
|
|
sve-fixed-length-reshuffle.ll
|
|
|
|
sve-fixed-length-rev.ll
|
[AArch64][Isel] For fixed length vectors use sve for bitreverse when available (#196025)
|
2026-05-12 08:19:56 +05:30 |
|
sve-fixed-length-sdiv-pow2.ll
|
|
|
|
sve-fixed-length-shuffles.ll
|
|
|
|
sve-fixed-length-splat-segment.ll
|
|
|
|
sve-fixed-length-splat-vector.ll
|
|
|
|
sve-fixed-length-subvector.ll
|
[AArch64] Hint regalloc to choose distinct predicate for MATCH/CMP (#190139)
|
2026-04-14 09:40:50 +01:00 |
|
sve-fixed-length-trunc-stores.ll
|
[AArch64] Address issue reported in PR#196029 (#199122)
|
2026-06-03 08:33:24 -07:00 |
|
sve-fixed-length-trunc.ll
|
|
|
|
sve-fixed-length-vector-shuffle-tbl.ll
|
|
|
|
sve-fixed-length-vector-shuffle.ll
|
|
|
|
sve-fixed-vector-extract-256-bits.ll
|
|
|
|
sve-fixed-vector-llrint.ll
|
[AArch64] Add SVE lowering for FP_TO_[US]INT_SAT. (#207201)
|
2026-07-23 09:32:02 +01:00 |
|
sve-fixed-vector-lrint.ll
|
[AArch64] Add SVE lowering for FP_TO_[US]INT_SAT. (#207201)
|
2026-07-23 09:32:02 +01:00 |
|
sve-fixed-vector-zext.ll
|
|
|
|
sve-fmmla-f32f16.ll
|
|
|
|
sve-fmsub.ll
|
|
|
|
sve-fold-loadext-and-splat-vector.ll
|
|
|
|
sve-fold-vscale.ll
|
|
|
|
sve-forward-st-to-ld.ll
|
|
|
|
sve-fp-combine.ll
|
|
|
|
sve-fp-immediates-merging.ll
|
[LLVM][Constants] Remove the option to disable vector ConstantFP support. (#197427)
|
2026-05-14 11:45:37 +01:00 |
|
sve-fp-int-min-max.ll
|
|
|
|
sve-fp-reciprocal.ll
|
|
|
|
sve-fp-reduce-fadda.ll
|
|
|
|
sve-fp-reduce.ll
|
|
|
|
sve-fp-rounding.ll
|
|
|
|
sve-fp-vselect.ll
|
|
|
|
sve-fp.ll
|
|
|
|
sve-fpext-load.ll
|
|
|
|
sve-fptosi-sat.ll
|
[AArch64] Add SVE lowering for FP_TO_[US]INT_SAT. (#207201)
|
2026-07-23 09:32:02 +01:00 |
|
sve-fptoui-sat.ll
|
[AArch64] Add SVE lowering for FP_TO_[US]INT_SAT. (#207201)
|
2026-07-23 09:32:02 +01:00 |
|
sve-fptrunc-store.ll
|
|
|
|
sve-frintz.ll
|
[SelectionDAG] Remove the remaining NoSignedZerosFPMath use (#201535)
|
2026-06-05 11:48:05 +00:00 |
|
sve-gather-scatter-addr-opts.ll
|
[AArch64][SDAG] Fix invalid index into STEP_VECTOR operand (#193236)
|
2026-04-28 09:58:11 +01:00 |
|
sve-gather-scatter-dag-combine.ll
|
[AArch64][SVE] Add more MOVPRFX pseudos for SVE immediate instructions. (#192491)
|
2026-04-20 14:55:54 +01:00 |
|
sve-gep.ll
|
|
|
|
sve-hadd.ll
|
[LLVM][CodeGen][SVE] Add isel patterns for add/sub where the second operand is promoted. (#212771)
|
2026-07-30 11:31:13 +01:00 |
|
sve-i1-add-reduce.ll
|
|
|
|
sve-implicit-zero-filling.ll
|
|
|
|
sve-index-const-step-vector.ll
|
|
|
|
sve-indexed-arithmetic.ll
|
|
|
|
sve-insert-element.ll
|
[LLVM][CodeGen] Remove +bf16 for ARM/AArch64 tests that don't strictly need the feature flag. (#204199)
|
2026-06-23 12:29:11 +01:00 |
|
sve-insert-scalable-vector.ll
|
|
|
|
sve-insert-vector-to-predicate-load.ll
|
[LLVM][CodeGen][SVE] Reimplement SVE VLS predicate load/store transformation as DAG combines. (#203314)
|
2026-06-15 12:09:33 +01:00 |
|
sve-insert-vector.ll
|
[LLVM][CodeGen] Remove +bf16 for ARM/AArch64 tests that don't strictly need the feature flag. (#204199)
|
2026-06-23 12:29:11 +01:00 |
|
sve-insr.ll
|
|
|
|
sve-int-arith-imm.ll
|
|
|
|
sve-int-arith-pred.ll
|
|
|
|
sve-int-arith.ll
|
|
|
|
sve-int-div-pred.ll
|
|
|
|
sve-int-imm.ll
|
|
|
|
sve-int-log-imm.ll
|
|
|
|
sve-int-log-pred.ll
|
|
|
|
sve-int-log.ll
|
[AArch64][SVE] Use SUBR for unpredicated bitwise NOT. (#191155)
|
2026-04-09 14:13:59 +01:00 |
|
sve-int-mad-pred.ll
|
|
|
|
sve-int-mul-neg.ll
|
|
|
|
sve-int-mul-pred.ll
|
|
|
|
sve-int-mulh-pred.ll
|
|
|
|
sve-int-pred-reduce.ll
|
|
|
|
sve-int-reduce-pred.ll
|
|
|
|
sve-int-reduce.ll
|
|
|
|
sve-interleave-low-vf.ll
|
[AArch64][LV] Cost low-VF interleaved access (#205844)
|
2026-07-07 15:57:21 +00:00 |
|
sve-intrinsics-adr.ll
|
|
|
|
sve-intrinsics-bfloat.ll
|
[AArch64][llvm][clang] Remove int_aarch64_sve_bfmmla and reuse existing def (NFC) (#193970)
|
2026-05-01 10:49:31 +01:00 |
|
sve-intrinsics-bfscale.ll
|
|
|
|
sve-intrinsics-contiguous-prefetches.ll
|
|
|
|
sve-intrinsics-conversion.ll
|
|
|
|
sve-intrinsics-counting-bits.ll
|
|
|
|
sve-intrinsics-counting-elems-i32.ll
|
|
|
|
sve-intrinsics-counting-elems.ll
|
|
|
|
sve-intrinsics-dup-x.ll
|
|
|
|
sve-intrinsics-fexpa.ll
|
|
|
|
sve-intrinsics-ff-gather-loads-32bit-scaled-offsets.ll
|
|
|
|
sve-intrinsics-ff-gather-loads-32bit-unscaled-offsets.ll
|
|
|
|
sve-intrinsics-ff-gather-loads-64bit-scaled-offset.ll
|
|
|
|
sve-intrinsics-ff-gather-loads-64bit-unscaled-offset.ll
|
|
|
|
sve-intrinsics-ff-gather-loads-vector-base-imm-offset.ll
|
|
|
|
sve-intrinsics-ff-gather-loads-vector-base-scalar-offset.ll
|
|
|
|
sve-intrinsics-ffr-manipulation.ll
|
|
|
|
sve-intrinsics-fp-arith-imm.ll
|
|
|
|
sve-intrinsics-fp-arith-merging.ll
|
|
|
|
sve-intrinsics-fp-arith-undef.ll
|
|
|
|
sve-intrinsics-fp-arith.ll
|
|
|
|
sve-intrinsics-fp-compares.ll
|
|
|
|
sve-intrinsics-fp-converts.ll
|
|
|
|
sve-intrinsics-fp-reduce.ll
|
|
|
|
sve-intrinsics-gather-loads-32bit-scaled-offsets.ll
|
|
|
|
sve-intrinsics-gather-loads-32bit-unscaled-offsets.ll
|
|
|
|
sve-intrinsics-gather-loads-64bit-scaled-offset.ll
|
|
|
|
sve-intrinsics-gather-loads-64bit-unscaled-offset.ll
|
|
|
|
sve-intrinsics-gather-loads-vector-base-imm-offset.ll
|
|
|
|
sve-intrinsics-gather-loads-vector-base-scalar-offset.ll
|
|
|
|
sve-intrinsics-gather-prefetches-scalar-base-vector-indexes.ll
|
|
|
|
sve-intrinsics-gather-prefetches-vect-base-imm-offset.ll
|
|
|
|
sve-intrinsics-gather-prefetches-vect-base-invalid-imm-offset.ll
|
|
|
|
sve-intrinsics-index.ll
|
|
|
|
sve-intrinsics-int-arith-imm-zero.ll
|
|
|
|
sve-intrinsics-int-arith-imm.ll
|
[NFC][LLVM][Tests] Replace instances of @llvm.aarch64.sve.ptrue.nxv16i1(i32 31) with splat (i1 true). (#204113)
|
2026-06-16 12:44:06 +01:00 |
|
sve-intrinsics-int-arith-merging.ll
|
|
|
|
sve-intrinsics-int-arith-merging.mir
|
|
|
|
sve-intrinsics-int-arith-undef.ll
|
[AArch64][SVE] Use ADD/ADR instead of MUL/MLA for x*N (#198566)
|
2026-06-24 11:43:29 +01:00 |
|
sve-intrinsics-int-arith.ll
|
|
|
|
sve-intrinsics-int-binaryComm-merging.mir
|
|
|
|
sve-intrinsics-int-binaryCommWithRev-merging.mir
|
|
|
|
sve-intrinsics-int-compares-with-imm.ll
|
|
|
|
sve-intrinsics-int-compares.ll
|
[AArch64] Hint regalloc to choose distinct predicate for MATCH/CMP (#190139)
|
2026-04-14 09:40:50 +01:00 |
|
sve-intrinsics-ld1-addressing-mode-reg-imm.ll
|
|
|
|
sve-intrinsics-ld1-addressing-mode-reg-reg.ll
|
|
|
|
sve-intrinsics-ld1.ll
|
|
|
|
sve-intrinsics-ld1ro-addressing-mode-reg-imm.ll
|
|
|
|
sve-intrinsics-ld1ro-addressing-mode-reg-reg.ll
|
|
|
|
sve-intrinsics-ld1ro.ll
|
|
|
|
sve-intrinsics-ldN-sret-reg+imm-addr-mode.ll
|
|
|
|
sve-intrinsics-ldN-sret-reg+reg-addr-mode.ll
|
|
|
|
sve-intrinsics-ldst-ext.ll
|
|
|
|
sve-intrinsics-loads-ff.ll
|
|
|
|
sve-intrinsics-loads-nf.ll
|
|
|
|
sve-intrinsics-loads.ll
|
[LLVM][CodeGen] Remove +bf16 for ARM/AArch64 tests that don't strictly need the feature flag. (#204199)
|
2026-06-23 12:29:11 +01:00 |
|
sve-intrinsics-logical-imm.ll
|
[NFC][LLVM][Tests] Replace instances of @llvm.aarch64.sve.ptrue.nxv16i1(i32 31) with splat (i1 true). (#204113)
|
2026-06-16 12:44:06 +01:00 |
|
sve-intrinsics-logical-undef.ll
|
|
|
|
sve-intrinsics-logical.ll
|
|
|
|
sve-intrinsics-mask-ldst-ext.ll
|
|
|
|
sve-intrinsics-matmul-bf16.ll
|
[AArch64][clang][llvm] Add ACLE Armv9.7 matrix multiply-accumulate intrinsics (#193017)
|
2026-04-27 15:40:50 +01:00 |
|
sve-intrinsics-matmul-f16.ll
|
[AArch64][clang][llvm] Add ACLE Armv9.7 matrix multiply-accumulate intrinsics (#193017)
|
2026-04-27 15:40:50 +01:00 |
|
sve-intrinsics-matmul-fp32.ll
|
|
|
|
sve-intrinsics-matmul-fp64.ll
|
|
|
|
sve-intrinsics-matmul-int8.ll
|
|
|
|
sve-intrinsics-perm-select-matmul-fp64.ll
|
|
|
|
sve-intrinsics-perm-select.ll
|
|
|
|
sve-intrinsics-pred-creation.ll
|
|
|
|
sve-intrinsics-pred-operations.ll
|
[NFC][LLVM][CodeGen] Refactor testing of SVE predicate logical instructions. (#206737)
|
2026-06-30 16:01:48 +01:00 |
|
sve-intrinsics-pred-testing.ll
|
|
|
|
sve-intrinsics-reinterpret-no-streaming.ll
|
|
|
|
sve-intrinsics-reinterpret.ll
|
[NFC][LLVM][Tests] Replace instances of @llvm.aarch64.sve.ptrue.nxv16i1(i32 31) with splat (i1 true). (#204113)
|
2026-06-16 12:44:06 +01:00 |
|
sve-intrinsics-reversal.ll
|
|
|
|
sve-intrinsics-scalar-to-vec.ll
|
|
|
|
sve-intrinsics-scatter-stores-32bit-scaled-offsets.ll
|
|
|
|
sve-intrinsics-scatter-stores-32bit-unscaled-offsets.ll
|
|
|
|
sve-intrinsics-scatter-stores-64bit-scaled-offset.ll
|
|
|
|
sve-intrinsics-scatter-stores-64bit-unscaled-offset.ll
|
|
|
|
sve-intrinsics-scatter-stores-vector-base-imm-offset.ll
|
|
|
|
sve-intrinsics-scatter-stores-vector-base-scalar-offset.ll
|
|
|
|
sve-intrinsics-sel.ll
|
|
|
|
sve-intrinsics-shifts-merging.ll
|
|
|
|
sve-intrinsics-shifts-undef.ll
|
|
|
|
sve-intrinsics-shifts.ll
|
|
|
|
sve-intrinsics-sqdec.ll
|
|
|
|
sve-intrinsics-sqinc.ll
|
|
|
|
sve-intrinsics-st1-addressing-mode-reg-imm.ll
|
|
|
|
sve-intrinsics-st1-addressing-mode-reg-reg.ll
|
|
|
|
sve-intrinsics-st1.ll
|
|
|
|
sve-intrinsics-stN-reg-imm-addr-mode.ll
|
|
|
|
sve-intrinsics-stN-reg-reg-addr-mode.ll
|
|
|
|
sve-intrinsics-stores.ll
|
|
|
|
sve-intrinsics-unpred-form.ll
|
[NFC][LLVM][Tests] Replace instances of @llvm.aarch64.sve.ptrue.nxv16i1(i32 31) with splat (i1 true). (#204113)
|
2026-06-16 12:44:06 +01:00 |
|
sve-intrinsics-uqdec.ll
|
|
|
|
sve-intrinsics-uqinc.ll
|
|
|
|
sve-intrinsics-while.ll
|
|
|
|
sve-knownbits.ll
|
|
|
|
sve-ld-post-inc.ll
|
[AArch64] Hint regalloc to choose distinct predicate for MATCH/CMP (#190139)
|
2026-04-14 09:40:50 +01:00 |
|
sve-ld1-addressing-mode-reg-imm.ll
|
|
|
|
sve-ld1-addressing-mode-reg-reg.ll
|
[LLVM][CodeGen] Remove +bf16 for ARM/AArch64 tests that don't strictly need the feature flag. (#204199)
|
2026-06-23 12:29:11 +01:00 |
|
sve-ld1r.ll
|
|
|
|
sve-ld1r.mir
|
[CodeGen] Rename prologpeilog to prolog-epilog (#207870)
|
2026-07-06 18:26:05 -07:00 |
|
sve-ldN.mir
|
[CodeGen] Rename prologpeilog to prolog-epilog (#207870)
|
2026-07-06 18:26:05 -07:00 |
|
sve-ldnf1.mir
|
[CodeGen] Rename prologpeilog to prolog-epilog (#207870)
|
2026-07-06 18:26:05 -07:00 |
|
sve-ldst-multi-vec.mir
|
[AArch64][SME2] Add stridedorcontiguous pseudos for multi-vector-stores (#211551)
|
2026-07-30 16:21:59 +00:00 |
|
sve-ldst-sext.ll
|
[AArch64] Add combine for interleave deinterleave (#208414)
|
2026-07-20 09:39:13 +01:00 |
|
sve-ldst-zext.ll
|
[AArch64] Add combine for interleave deinterleave (#208414)
|
2026-07-20 09:39:13 +01:00 |
|
sve-ldstnt1.mir
|
[CodeGen] Rename prologpeilog to prolog-epilog (#207870)
|
2026-07-06 18:26:05 -07:00 |
|
sve-llrint.ll
|
[AArch64] Add SVE lowering for FP_TO_[US]INT_SAT. (#207201)
|
2026-07-23 09:32:02 +01:00 |
|
sve-load-compare-store.ll
|
[NFC][LLVM][Tests] Replace instances of @llvm.aarch64.sve.ptrue.nxv16i1(i32 31) with splat (i1 true). (#204113)
|
2026-06-16 12:44:06 +01:00 |
|
sve-load-store-legalisation.ll
|
[AArch64][CodeGen] Split wide active lane mask into smaller masks if preferred (#202909)
|
2026-07-10 14:39:13 +01:00 |
|
sve-load-store-strict-align.ll
|
|
|
|
sve-localstackalloc.mir
|
|
|
|
sve-lrint.ll
|
[AArch64] Add SVE lowering for FP_TO_[US]INT_SAT. (#207201)
|
2026-07-23 09:32:02 +01:00 |
|
sve-lsr-scaled-index-addressing-mode.ll
|
|
|
|
sve-lsrchain.ll
|
[NFC][LLVM][Tests] Replace instances of @llvm.aarch64.sve.ptrue.nxv16i1(i32 31) with splat (i1 true). (#204113)
|
2026-06-16 12:44:06 +01:00 |
|
sve-mask-partition.ll
|
[AArch64] Tighten conditions for expanding GET_ACTIVE_LANE_MASK (#208962)
|
2026-07-14 10:20:24 -07:00 |
|
sve-masked-compressstore-sve2p2.ll
|
|
|
|
sve-masked-compressstore.ll
|
[AArch64] Hint regalloc to choose distinct predicate for MATCH/CMP (#190139)
|
2026-04-14 09:40:50 +01:00 |
|
sve-masked-gather-32b-signed-scaled.ll
|
|
|
|
sve-masked-gather-32b-signed-unscaled.ll
|
|
|
|
sve-masked-gather-32b-unsigned-scaled.ll
|
|
|
|
sve-masked-gather-32b-unsigned-unscaled.ll
|
|
|
|
sve-masked-gather-64b-scaled.ll
|
[AArch64][SDAG] Legalise nxv1 gather/scatter nodes (#204620)
|
2026-06-19 10:50:30 +01:00 |
|
sve-masked-gather-64b-unscaled.ll
|
[AArch64] Combine undef UZP and NVCAST away. (#204623)
|
2026-07-03 10:24:47 +01:00 |
|
sve-masked-gather-legalize.ll
|
[AArch64] Combine undef UZP and NVCAST away. (#204623)
|
2026-07-03 10:24:47 +01:00 |
|
sve-masked-gather-vec-plus-imm.ll
|
|
|
|
sve-masked-gather-vec-plus-reg.ll
|
|
|
|
sve-masked-gather.ll
|
[AArch64] Combine undef UZP and NVCAST away. (#204623)
|
2026-07-03 10:24:47 +01:00 |
|
sve-masked-int-arith.ll
|
|
|
|
sve-masked-ldst-alias-analysis.ll
|
[LLVM][SelectionDAG] Don't assume masked loads access all lanes in memory. (#192706)
|
2026-04-27 11:47:22 +01:00 |
|
sve-masked-ldst-nonext.ll
|
|
|
|
sve-masked-ldst-sext.ll
|
|
|
|
sve-masked-ldst-trunc.ll
|
|
|
|
sve-masked-ldst-zext.ll
|
|
|
|
sve-masked-scatter-32b-scaled.ll
|
|
|
|
sve-masked-scatter-32b-unscaled.ll
|
|
|
|
sve-masked-scatter-64b-scaled.ll
|
[AArch64][SDAG] Legalise nxv1 gather/scatter nodes (#204620)
|
2026-06-19 10:50:30 +01:00 |
|
sve-masked-scatter-64b-unscaled.ll
|
[AArch64][SDAG] Legalise nxv1 gather/scatter nodes (#204620)
|
2026-06-19 10:50:30 +01:00 |
|
sve-masked-scatter-legalize.ll
|
|
|
|
sve-masked-scatter-vec-plus-imm.ll
|
|
|
|
sve-masked-scatter-vec-plus-reg.ll
|
|
|
|
sve-masked-scatter.ll
|
[AArch64][SDAG] Legalise nxv1 gather/scatter nodes (#204620)
|
2026-06-19 10:50:30 +01:00 |
|
sve-merging-stores.ll
|
|
|
|
sve-merging-unary.ll
|
|
|
|
sve-min-max-pred.ll
|
|
|
|
sve-mov-imm-pred.ll
|
|
|
|
sve-mul-imm-add-adr.ll
|
[AArch64][SVE] add missing MLA commute instcombine (#205526)
|
2026-06-26 10:02:58 +01:00 |
|
sve-multivector-fold-imms.ll
|
[AArch64][SVE] Select immediate offsets for multi-vector instructions (#201637)
|
2026-06-09 09:28:50 +01:00 |
|
sve-multivector-load-stores.ll
|
[AArch64][SME2] Add stridedorcontiguous pseudos for multi-vector-stores (#211551)
|
2026-07-30 16:21:59 +00:00 |
|
sve-no-typesize-warnings.ll
|
|
|
|
sve-nontemporal-ldst.ll
|
|
|
|
sve-nontemporal-masked-ldst.ll
|
[AArch64] Hint regalloc to choose distinct predicate for MATCH/CMP (#190139)
|
2026-04-14 09:40:50 +01:00 |
|
sve-partial-reduce-dot-product.ll
|
[LLVM][CodeGen][SVE] Use pairwise instruction for partial_reduce_[s/u]mla. (#212772)
|
2026-07-31 11:27:08 +01:00 |
|
sve-partial-reduce-wide-add.ll
|
[LLVM][CodeGen][SVE] Use pairwise instruction for partial_reduce_[s/u]mla. (#212772)
|
2026-07-31 11:27:08 +01:00 |
|
sve-pfalse-machine-cse.mir
|
|
|
|
sve-pr62151.ll
|
|
|
|
sve-pr92779.ll
|
|
|
|
sve-pred-arith.ll
|
|
|
|
sve-pred-contiguous-ldst-addressing-mode-reg-imm.ll
|
|
|
|
sve-pred-contiguous-ldst-addressing-mode-reg-reg.ll
|
|
|
|
sve-pred-ldst.ll
|
[LLVM][CodeGen][SVE] Make use of predicate load/store "mul vl" addressing mode. (#206997)
|
2026-07-08 12:25:53 +01:00 |
|
sve-pred-log.ll
|
[LLVM][CodeGen][SVE] Add isel patterns for predicate "and a, (op b, c)" sequences. (#206751)
|
2026-07-02 11:45:40 +01:00 |
|
sve-pred-non-temporal-ldst-addressing-mode-reg-imm.ll
|
|
|
|
sve-pred-non-temporal-ldst-addressing-mode-reg-reg.ll
|
|
|
|
sve-pred-pair-spill-fill.ll
|
|
|
|
sve-pred-selectop.ll
|
[AArch64] Hint regalloc to choose distinct predicate for MATCH/CMP (#190139)
|
2026-04-14 09:40:50 +01:00 |
|
sve-pred-selectop2.ll
|
[AArch64] Hint regalloc to choose distinct predicate for MATCH/CMP (#190139)
|
2026-04-14 09:40:50 +01:00 |
|
sve-pred-selectop3.ll
|
[AArch64] Hint regalloc to choose distinct predicate for MATCH/CMP (#190139)
|
2026-04-14 09:40:50 +01:00 |
|
sve-pseudos-expand-undef.mir
|
|
|
|
sve-ptest-removal-brk.ll
|
[NFC][LLVM][Tests] Replace instances of @llvm.aarch64.sve.ptrue.nxv16i1(i32 31) with splat (i1 true). (#204113)
|
2026-06-16 12:44:06 +01:00 |
|
sve-ptest-removal-cmpeq.ll
|
[NFC][LLVM][Tests] Replace instances of @llvm.aarch64.sve.ptrue.nxv16i1(i32 31) with splat (i1 true). (#204113)
|
2026-06-16 12:44:06 +01:00 |
|
sve-ptest-removal-cmpeq.mir
|
|
|
|
sve-ptest-removal-cmpge.ll
|
[NFC][LLVM][Tests] Replace instances of @llvm.aarch64.sve.ptrue.nxv16i1(i32 31) with splat (i1 true). (#204113)
|
2026-06-16 12:44:06 +01:00 |
|
sve-ptest-removal-cmpgt.ll
|
[NFC][LLVM][Tests] Replace instances of @llvm.aarch64.sve.ptrue.nxv16i1(i32 31) with splat (i1 true). (#204113)
|
2026-06-16 12:44:06 +01:00 |
|
sve-ptest-removal-cmphi.ll
|
[NFC][LLVM][Tests] Replace instances of @llvm.aarch64.sve.ptrue.nxv16i1(i32 31) with splat (i1 true). (#204113)
|
2026-06-16 12:44:06 +01:00 |
|
sve-ptest-removal-cmphs.ll
|
[NFC][LLVM][Tests] Replace instances of @llvm.aarch64.sve.ptrue.nxv16i1(i32 31) with splat (i1 true). (#204113)
|
2026-06-16 12:44:06 +01:00 |
|
sve-ptest-removal-cmple.ll
|
[NFC][LLVM][Tests] Replace instances of @llvm.aarch64.sve.ptrue.nxv16i1(i32 31) with splat (i1 true). (#204113)
|
2026-06-16 12:44:06 +01:00 |
|
sve-ptest-removal-cmplo.ll
|
[NFC][LLVM][Tests] Replace instances of @llvm.aarch64.sve.ptrue.nxv16i1(i32 31) with splat (i1 true). (#204113)
|
2026-06-16 12:44:06 +01:00 |
|
sve-ptest-removal-cmpls.ll
|
[NFC][LLVM][Tests] Replace instances of @llvm.aarch64.sve.ptrue.nxv16i1(i32 31) with splat (i1 true). (#204113)
|
2026-06-16 12:44:06 +01:00 |
|
sve-ptest-removal-cmplt.ll
|
[NFC][LLVM][Tests] Replace instances of @llvm.aarch64.sve.ptrue.nxv16i1(i32 31) with splat (i1 true). (#204113)
|
2026-06-16 12:44:06 +01:00 |
|
sve-ptest-removal-cmpne.ll
|
[NFC][LLVM][Tests] Replace instances of @llvm.aarch64.sve.ptrue.nxv16i1(i32 31) with splat (i1 true). (#204113)
|
2026-06-16 12:44:06 +01:00 |
|
sve-ptest-removal-log.ll
|
[AArch64] Hint regalloc to choose distinct predicate for MATCH/CMP (#190139)
|
2026-04-14 09:40:50 +01:00 |
|
sve-ptest-removal-match.ll
|
[NFC][LLVM][Tests] Replace instances of @llvm.aarch64.sve.ptrue.nxv16i1(i32 31) with splat (i1 true). (#204113)
|
2026-06-16 12:44:06 +01:00 |
|
sve-ptest-removal-pfirst-pnext.ll
|
|
|
|
sve-ptest-removal-ptrue.ll
|
|
|
|
sve-ptest-removal-rdffr.mir
|
|
|
|
sve-ptest-removal-sink.ll
|
|
|
|
sve-ptest-removal-whilege.mir
|
|
|
|
sve-ptest-removal-whilegt.mir
|
|
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|
sve-ptest-removal-whilehi.mir
|
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|
sve-ptest-removal-whilehs.mir
|
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sve-ptest-removal-whilele.mir
|
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sve-ptest-removal-whilelo.mir
|
|
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sve-ptest-removal-whilels.mir
|
|
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sve-ptest-removal-whilelt.mir
|
|
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|
sve-ptest-removal-whilerw.mir
|
|
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|
sve-ptest-removal-whilewr.mir
|
|
|
|
sve-ptest.ll
|
[LLVM][Verifier] Move intrinsic signature verification to declarations (#204478)
|
2026-06-29 06:57:16 -07:00 |
|
sve-ptrue-coalesce.mir
|
[LLVM][CodeGen][SVE] Add ElementSize information to fp compare, continuous/replicating load and store instructions (#204821)
|
2026-07-29 11:09:09 +01:00 |
|
sve-punpklo-combine.ll
|
[NFC][LLVM][Tests] Replace instances of @llvm.aarch64.sve.ptrue.nxv16i1(i32 31) with splat (i1 true). (#204113)
|
2026-06-16 12:44:06 +01:00 |
|
sve-reassocadd.ll
|
|
|
|
sve-redundant-store.ll
|
|
|
|
sve-regalloc-hint-unique-predicate-dst.mir
|
[AArch64] Hint regalloc to choose distinct predicate for MATCH/CMP (#190139)
|
2026-04-14 09:40:50 +01:00 |
|
sve-rev.ll
|
|
|
|
sve-saba.ll
|
[NFC][LLVM][Tests] Replace instances of @llvm.aarch64.sve.ptrue.nxv16i1(i32 31) with splat (i1 true). (#204113)
|
2026-06-16 12:44:06 +01:00 |
|
sve-saddv_64.ll
|
|
|
|
sve-saturating-arith.ll
|
|
|
|
sve-scmp.ll
|
[AArch64] Hint regalloc to choose distinct predicate for MATCH/CMP (#190139)
|
2026-04-14 09:40:50 +01:00 |
|
sve-sdiv-pow2.ll
|
|
|
|
sve-select.ll
|
[AArch64] Fold any/sign-extend of CSET. (#207414)
|
2026-07-08 10:34:12 +01:00 |
|
sve-setcc.ll
|
[AArch64] Hint regalloc to choose distinct predicate for MATCH/CMP (#190139)
|
2026-04-14 09:40:50 +01:00 |
|
sve-sext-zext.ll
|
[AArch64][SVE] Add more MOVPRFX pseudos for SVE immediate instructions. (#192491)
|
2026-04-20 14:55:54 +01:00 |
|
sve-smulo-sdnode.ll
|
[AArch64] Hint regalloc to choose distinct predicate for MATCH/CMP (#190139)
|
2026-04-14 09:40:50 +01:00 |
|
sve-splat-one-and-ptrue.ll
|
|
|
|
sve-splat-sext.ll
|
|
|
|
sve-split-extract-elt.ll
|
|
|
|
sve-split-fcvt.ll
|
|
|
|
sve-split-fp-reduce.ll
|
|
|
|
sve-split-insert-elt.ll
|
[AArch64] Hint regalloc to choose distinct predicate for MATCH/CMP (#190139)
|
2026-04-14 09:40:50 +01:00 |
|
sve-split-int-pred-reduce.ll
|
[LLVM][CodeGen][SVE] Add isel patterns for predicate "and a, (op b, c)" sequences. (#206751)
|
2026-07-02 11:45:40 +01:00 |
|
sve-split-int-reduce.ll
|
|
|
|
sve-split-load.ll
|
|
|
|
sve-split-store.ll
|
|
|
|
sve-split-trunc.ll
|
|
|
|
sve-srem-combine-loop.ll
|
|
|
|
sve-st1-addressing-mode-reg-imm.ll
|
|
|
|
sve-st1-addressing-mode-reg-reg.ll
|
[LLVM][CodeGen] Remove +bf16 for ARM/AArch64 tests that don't strictly need the feature flag. (#204199)
|
2026-06-23 12:29:11 +01:00 |
|
sve-stack-frame-layout-win.ll
|
|
|
|
sve-stack-frame-layout.ll
|
[AArch64][SME] Remove SelectionDAG SME ABI lowering (#190950)
|
2026-04-13 09:52:18 +01:00 |
|
sve-stepvector.ll
|
|
|
|
sve-stlf.ll
|
|
|
|
sve-stN.mir
|
[CodeGen] Rename prologpeilog to prolog-epilog (#207870)
|
2026-07-06 18:26:05 -07:00 |
|
sve-streaming-mode-cvt-fp-int-fp.ll
|
|
|
|
sve-streaming-mode-cvt-fp-to-int.ll
|
[IR] Make semantics of strictfp consistent v2 (#211769)
|
2026-07-24 18:02:54 +00:00 |
|
sve-streaming-mode-cvt-int-to-fp.ll
|
[IR] Make semantics of strictfp consistent v2 (#211769)
|
2026-07-24 18:02:54 +00:00 |
|
sve-streaming-mode-fixed-length-and-combine.ll
|
|
|
|
sve-streaming-mode-fixed-length-bit-counting.ll
|
|
|
|
sve-streaming-mode-fixed-length-bitcast.ll
|
|
|
|
sve-streaming-mode-fixed-length-bitselect.ll
|
|
|
|
sve-streaming-mode-fixed-length-build-vector.ll
|
|
|
|
sve-streaming-mode-fixed-length-concat.ll
|
|
|
|
sve-streaming-mode-fixed-length-ext-loads.ll
|
|
|
|
sve-streaming-mode-fixed-length-extract-subvector.ll
|
|
|
|
sve-streaming-mode-fixed-length-extract-vector-elt.ll
|
|
|
|
sve-streaming-mode-fixed-length-fcopysign.ll
|
|
|
|
sve-streaming-mode-fixed-length-fp-arith.ll
|
|
|
|
sve-streaming-mode-fixed-length-fp-compares.ll
|
[AArch64][SVE] Use SUBR for unpredicated bitwise NOT. (#191155)
|
2026-04-09 14:13:59 +01:00 |
|
sve-streaming-mode-fixed-length-fp-convert.ll
|
|
|
|
sve-streaming-mode-fixed-length-fp-extend-trunc.ll
|
|
|
|
sve-streaming-mode-fixed-length-fp-fma.ll
|
|
|
|
sve-streaming-mode-fixed-length-fp-minmax.ll
|
|
|
|
sve-streaming-mode-fixed-length-fp-reduce-fa64.ll
|
|
|
|
sve-streaming-mode-fixed-length-fp-reduce.ll
|
|
|
|
sve-streaming-mode-fixed-length-fp-rounding.ll
|
|
|
|
sve-streaming-mode-fixed-length-fp-select.ll
|
[AArch64] Hint regalloc to choose distinct predicate for MATCH/CMP (#190139)
|
2026-04-14 09:40:50 +01:00 |
|
sve-streaming-mode-fixed-length-fp-to-int.ll
|
|
|
|
sve-streaming-mode-fixed-length-fp-vselect.ll
|
[AArch64] Hint regalloc to choose distinct predicate for MATCH/CMP (#190139)
|
2026-04-14 09:40:50 +01:00 |
|
sve-streaming-mode-fixed-length-insert-vector-elt.ll
|
[AArch64] Hint regalloc to choose distinct predicate for MATCH/CMP (#190139)
|
2026-04-14 09:40:50 +01:00 |
|
sve-streaming-mode-fixed-length-int-abd.ll
|
|
|
|
sve-streaming-mode-fixed-length-int-arith.ll
|
|
|
|
sve-streaming-mode-fixed-length-int-compares.ll
|
[AArch64] Hint regalloc to choose distinct predicate for MATCH/CMP (#190139)
|
2026-04-14 09:40:50 +01:00 |
|
sve-streaming-mode-fixed-length-int-div.ll
|
|
|
|
sve-streaming-mode-fixed-length-int-extends.ll
|
[AArch64] Mark FIXED_REGS register class as non-allocatable (#212250)
|
2026-07-29 12:06:05 +01:00 |
|
sve-streaming-mode-fixed-length-int-immediates.ll
|
[AArch64] Hint regalloc to choose distinct predicate for MATCH/CMP (#190139)
|
2026-04-14 09:40:50 +01:00 |
|
sve-streaming-mode-fixed-length-int-log.ll
|
|
|
|
sve-streaming-mode-fixed-length-int-minmax.ll
|
|
|
|
sve-streaming-mode-fixed-length-int-mla-neon-fa64.ll
|
|
|
|
sve-streaming-mode-fixed-length-int-mul.ll
|
|
|
|
sve-streaming-mode-fixed-length-int-mulh.ll
|
[AArch64] Mark FIXED_REGS register class as non-allocatable (#212250)
|
2026-07-29 12:06:05 +01:00 |
|
sve-streaming-mode-fixed-length-int-reduce.ll
|
|
|
|
sve-streaming-mode-fixed-length-int-rem.ll
|
|
|
|
sve-streaming-mode-fixed-length-int-select.ll
|
[AArch64] Hint regalloc to choose distinct predicate for MATCH/CMP (#190139)
|
2026-04-14 09:40:50 +01:00 |
|
sve-streaming-mode-fixed-length-int-shifts.ll
|
|
|
|
sve-streaming-mode-fixed-length-int-to-fp.ll
|
|
|
|
sve-streaming-mode-fixed-length-int-vselect.ll
|
[AArch64] Mark FIXED_REGS register class as non-allocatable (#212250)
|
2026-07-29 12:06:05 +01:00 |
|
sve-streaming-mode-fixed-length-ld2-alloca.ll
|
|
|
|
sve-streaming-mode-fixed-length-limit-duplane.ll
|
|
|
|
sve-streaming-mode-fixed-length-loads.ll
|
|
|
|
sve-streaming-mode-fixed-length-log-reduce.ll
|
|
|
|
sve-streaming-mode-fixed-length-masked-expandload.ll
|
[AArch64] Lower masked.expandload intrinsic using SVE2p2/SME2p2 EXPAND (#190999)
|
2026-04-20 11:06:34 +01:00 |
|
sve-streaming-mode-fixed-length-masked-gather-scatter.ll
|
[AArch64] Hint regalloc to choose distinct predicate for MATCH/CMP (#190139)
|
2026-04-14 09:40:50 +01:00 |
|
sve-streaming-mode-fixed-length-masked-load.ll
|
[DAG] visitAND - attempt to fold (and buildvector(), buildvector()) -> buildvector() (#193987)
|
2026-04-27 08:33:45 +00:00 |
|
sve-streaming-mode-fixed-length-masked-store.ll
|
[AArch64] Hint regalloc to choose distinct predicate for MATCH/CMP (#190139)
|
2026-04-14 09:40:50 +01:00 |
|
sve-streaming-mode-fixed-length-optimize-ptrue.ll
|
|
|
|
sve-streaming-mode-fixed-length-permute-rev.ll
|
|
|
|
sve-streaming-mode-fixed-length-permute-zip-uzp-trn.ll
|
|
|
|
sve-streaming-mode-fixed-length-ptest.ll
|
|
|
|
sve-streaming-mode-fixed-length-reductions.ll
|
|
|
|
sve-streaming-mode-fixed-length-reshuffle.ll
|
|
|
|
sve-streaming-mode-fixed-length-rev.ll
|
|
|
|
sve-streaming-mode-fixed-length-sdiv-pow2.ll
|
|
|
|
sve-streaming-mode-fixed-length-shuffle.ll
|
|
|
|
sve-streaming-mode-fixed-length-splat-vector.ll
|
[LLVM][Constants] Remove the option to disable vector ConstantFP support. (#197427)
|
2026-05-14 11:45:37 +01:00 |
|
sve-streaming-mode-fixed-length-stores.ll
|
|
|
|
sve-streaming-mode-fixed-length-subvector.ll
|
|
|
|
sve-streaming-mode-fixed-length-trunc-stores.ll
|
|
|
|
sve-streaming-mode-fixed-length-trunc.ll
|
[AArch64] Mark FIXED_REGS register class as non-allocatable (#212250)
|
2026-07-29 12:06:05 +01:00 |
|
sve-streaming-mode-fixed-length-vector-shuffle.ll
|
|
|
|
sve-streaming-mode-test-register-mov.ll
|
|
|
|
sve-structured-store-memoperands.ll
|
[AArch64] Preserve store memoperand (#210936)
|
2026-07-31 05:51:26 +01:00 |
|
sve-tailcall.ll
|
|
|
|
sve-tbl-folding-new-pm.ll
|
[AArch64] Add SVE shuffle optimization pass (#193951)
|
2026-06-19 11:49:56 +01:00 |
|
sve-tbl-folding-opts.ll
|
[AArch64] Add SVE shuffle optimization pass (#193951)
|
2026-06-19 11:49:56 +01:00 |
|
sve-trunc.ll
|
[AArch64] Hint regalloc to choose distinct predicate for MATCH/CMP (#190139)
|
2026-04-14 09:40:50 +01:00 |
|
sve-ucmp.ll
|
[AArch64] Hint regalloc to choose distinct predicate for MATCH/CMP (#190139)
|
2026-04-14 09:40:50 +01:00 |
|
sve-umulo-sdnode.ll
|
[AArch64] Hint regalloc to choose distinct predicate for MATCH/CMP (#190139)
|
2026-04-14 09:40:50 +01:00 |
|
sve-unaligned-load-store-strict-align.ll
|
|
|
|
sve-unary-movprfx.ll
|
[NFC][LLVM][Tests] Replace instances of @llvm.aarch64.sve.ptrue.nxv16i1(i32 31) with splat (i1 true). (#204113)
|
2026-06-16 12:44:06 +01:00 |
|
sve-uunpklo-load-uzp1-store-combine.ll
|
[NFC][LLVM][Tests] Replace instances of @llvm.aarch64.sve.ptrue.nxv16i1(i32 31) with splat (i1 true). (#204113)
|
2026-06-16 12:44:06 +01:00 |
|
sve-varargs-callee-broken.ll
|
|
|
|
sve-varargs-caller-broken.ll
|
|
|
|
sve-varargs.ll
|
|
|
|
sve-vecreduce-dot.ll
|
|
|
|
sve-vecreduce-fold.ll
|
|
|
|
sve-vector-compress.ll
|
[LLVM][CodeGen][SVE] Extend NEON->SVE splat imm isel to cover 64-bit vectors. (#209833)
|
2026-07-22 11:01:27 +01:00 |
|
sve-vector-deinterleave.ll
|
[SelectionDAG][AArch64] Legalize vector.[de]interleave6 (#193723)
|
2026-04-30 10:06:41 +01:00 |
|
sve-vector-interleave.ll
|
[AArch64] Preserve store memoperand (#210936)
|
2026-07-31 05:51:26 +01:00 |
|
sve-vector-splat.ll
|
|
|
|
sve-vl-arith.ll
|
|
|
|
sve-vls-ldst-opt.mir
|
|
|
|
sve-vscale-attr.ll
|
|
|
|
sve-vscale-combine.ll
|
|
|
|
sve-vscale.ll
|
|
|
|
sve-vselect-fold.ll
|
[NFC][LLVM][Tests] Replace instances of @llvm.aarch64.sve.ptrue.nxv16i1(i32 31) with splat (i1 true). (#204113)
|
2026-06-16 12:44:06 +01:00 |
|
sve-vselect-imm.ll
|
|
|
|
sve-widen-scalable-vectortype.ll
|
|
|
|
sve-zeroinit.ll
|
|
|
|
sve-zext.ll
|
[AArch64][SelectionDAG] Improve codegen for and(sext(Op), splat(1)) (#192405)
|
2026-04-21 03:04:03 -07:00 |
|
sve2-bcax.ll
|
|
|
|
sve2-bf16-converts.ll
|
|
|
|
sve2-bitsel-pseudos-expansion.mir
|
|
|
|
sve2-bitwise-ternary.ll
|
|
|
|
sve2-bsl.ll
|
[AArch64][SVE] Use SUBR for unpredicated bitwise NOT. (#191155)
|
2026-04-09 14:13:59 +01:00 |
|
sve2-eor3.ll
|
|
|
|
sve2-fcopysign.ll
|
|
|
|
sve2-fixed-length-fcopysign.ll
|
|
|
|
sve2-fixed-length-sra-flag.ll
|
[AArch64] Preserve SDNode flags when lowering fixed vectors to scalable operations (#204616)
|
2026-06-25 16:11:12 +01:00 |
|
sve2-fixed-length-sra.ll
|
[AArch64] Preserve SDNode flags when lowering fixed vectors to scalable operations (#204616)
|
2026-06-25 16:11:12 +01:00 |
|
sve2-fmmla-f16mf8.ll
|
|
|
|
sve2-fmmla-f32mf8.ll
|
|
|
|
sve2-histcnt.ll
|
[AArch64][SVE] Use ADD/ADR instead of MUL/MLA for x*N (#198566)
|
2026-06-24 11:43:29 +01:00 |
|
sve2-int-addsub-long.ll
|
|
|
|
sve2-int-mul.ll
|
[NFC][LLVM][Tests] Replace instances of @llvm.aarch64.sve.ptrue.nxv16i1(i32 31) with splat (i1 true). (#204113)
|
2026-06-16 12:44:06 +01:00 |
|
sve2-int-mulh.ll
|
|
|
|
sve2-intrinsics-binary-narrowing-add-sub.ll
|
|
|
|
sve2-intrinsics-binary-narrowing-shr.ll
|
|
|
|
sve2-intrinsics-bit-permutation.ll
|
|
|
|
sve2-intrinsics-character-match.ll
|
|
|
|
sve2-intrinsics-combine-rshrnb.ll
|
|
|
|
sve2-intrinsics-complex-dot.ll
|
|
|
|
sve2-intrinsics-contiguous-conflict-detection.ll
|
|
|
|
sve2-intrinsics-crypto.ll
|
|
|
|
sve2-intrinsics-faminmax.ll
|
|
|
|
sve2-intrinsics-fp-converts.ll
|
|
|
|
sve2-intrinsics-fp-int-binary-logarithm-zeroing.ll
|
|
|
|
sve2-intrinsics-fp-int-binary-logarithm.ll
|
|
|
|
sve2-intrinsics-fp-widening-mul-acc.ll
|
|
|
|
sve2-intrinsics-int-arith-imm.ll
|
[NFC][LLVM][Tests] Replace instances of @llvm.aarch64.sve.ptrue.nxv16i1(i32 31) with splat (i1 true). (#204113)
|
2026-06-16 12:44:06 +01:00 |
|
sve2-intrinsics-int-mul-lane.ll
|
|
|
|
sve2-intrinsics-luti.ll
|
|
|
|
sve2-intrinsics-non-widening-pairwise-arith.ll
|
|
|
|
sve2-intrinsics-nt-gather-loads-32bit-unscaled-offset.ll
|
[LLVM][Verifier] Move intrinsic signature verification to declarations (#204478)
|
2026-06-29 06:57:16 -07:00 |
|
sve2-intrinsics-nt-gather-loads-64bit-scaled-offset.ll
|
|
|
|
sve2-intrinsics-nt-gather-loads-64bit-unscaled-offset.ll
|
|
|
|
sve2-intrinsics-nt-gather-loads-vector-base-scalar-offset.ll
|
|
|
|
sve2-intrinsics-nt-scatter-stores-32bit-unscaled-offset.ll
|
[LLVM][Verifier] Move intrinsic signature verification to declarations (#204478)
|
2026-06-29 06:57:16 -07:00 |
|
sve2-intrinsics-nt-scatter-stores-64bit-scaled-offset.ll
|
|
|
|
sve2-intrinsics-nt-scatter-stores-64bit-unscaled-offset.ll
|
|
|
|
sve2-intrinsics-nt-scatter-stores-vector-base-scalar-offset.ll
|
|
|
|
sve2-intrinsics-perm-tb.ll
|
|
|
|
sve2-intrinsics-polynomial-arithmetic-128.ll
|
|
|
|
sve2-intrinsics-polynomial-arithmetic.ll
|
|
|
|
sve2-intrinsics-psel.ll
|
|
|
|
sve2-intrinsics-rax1.ll
|
|
|
|
sve2-intrinsics-reinterpret.ll
|
|
|
|
sve2-intrinsics-revd.ll
|
|
|
|
sve2-intrinsics-sm4.ll
|
|
|
|
sve2-intrinsics-unary-narrowing.ll
|
|
|
|
sve2-intrinsics-uniform-complex-arith.ll
|
|
|
|
sve2-intrinsics-uniform-dsp-undef.ll
|
|
|
|
sve2-intrinsics-uniform-dsp-zeroing.ll
|
|
|
|
sve2-intrinsics-uniform-dsp.ll
|
|
|
|
sve2-intrinsics-vec-hist-count.ll
|
|
|
|
sve2-intrinsics-while-reversed.ll
|
|
|
|
sve2-intrinsics-while.ll
|
|
|
|
sve2-intrinsics-widening-complex-int-arith.ll
|
|
|
|
sve2-intrinsics-widening-dsp.ll
|
|
|
|
sve2-intrinsics-widening-pairwise-arith.ll
|
|
|
|
sve2-min-max-clamp.ll
|
|
|
|
sve2-mla-indexed.ll
|
|
|
|
sve2-mla-unpredicated.ll
|
|
|
|
sve2-mull-acc.ll
|
[AArch64] Select SVE2 multiply-add long from mull and add/sub (#207951)
|
2026-07-07 13:18:00 +01:00 |
|
sve2-rsh.ll
|
[AArch64] Fix and vs or in tryCombineExtendRShTrunc (#202053)
|
2026-06-06 16:39:10 +01:00 |
|
sve2-rsra.ll
|
[NFC][LLVM][Tests] Replace instances of @llvm.aarch64.sve.ptrue.nxv16i1(i32 31) with splat (i1 true). (#204113)
|
2026-06-16 12:44:06 +01:00 |
|
sve2-sli-sri.ll
|
[AArch64][SVE] Enable known bits for predicated shifts (#200347)
|
2026-06-17 12:14:47 +00:00 |
|
sve2-sra.ll
|
[AArch64][SVE] Enable known bits for predicated shifts (#200347)
|
2026-06-17 12:14:47 +00:00 |
|
sve2-unary-movprfx.ll
|
[NFC][LLVM][Tests] Replace instances of @llvm.aarch64.sve.ptrue.nxv16i1(i32 31) with splat (i1 true). (#204113)
|
2026-06-16 12:44:06 +01:00 |
|
sve2-vscale-sinking.ll
|
|
|
|
sve2-wide-ops.ll
|
[LLVM][CodeGen][SVE] Add isel patterns for add/sub where the second operand is promoted. (#212771)
|
2026-07-30 11:31:13 +01:00 |
|
sve2-xar.ll
|
|
|
|
sve2p1-dots-partial-reduction.ll
|
|
|
|
sve2p1-fdot.ll
|
|
|
|
sve2p1-fixed-length-fdot.ll
|
|
|
|
sve2p1-intrinsics-bfadd.ll
|
[NFC][LLVM][Tests] Replace instances of @llvm.aarch64.sve.ptrue.nxv16i1(i32 31) with splat (i1 true). (#204113)
|
2026-06-16 12:44:06 +01:00 |
|
sve2p1-intrinsics-bfclamp.ll
|
[AArch64] Fixup f16->bf16 in intrinsic defs. NFC (#200244)
|
2026-05-28 19:51:23 +01:00 |
|
sve2p1-intrinsics-bfmax.ll
|
[NFC][LLVM][Tests] Replace instances of @llvm.aarch64.sve.ptrue.nxv16i1(i32 31) with splat (i1 true). (#204113)
|
2026-06-16 12:44:06 +01:00 |
|
sve2p1-intrinsics-bfmaxnm.ll
|
[NFC][LLVM][Tests] Replace instances of @llvm.aarch64.sve.ptrue.nxv16i1(i32 31) with splat (i1 true). (#204113)
|
2026-06-16 12:44:06 +01:00 |
|
sve2p1-intrinsics-bfmin.ll
|
[NFC][LLVM][Tests] Replace instances of @llvm.aarch64.sve.ptrue.nxv16i1(i32 31) with splat (i1 true). (#204113)
|
2026-06-16 12:44:06 +01:00 |
|
sve2p1-intrinsics-bfminnm.ll
|
[NFC][LLVM][Tests] Replace instances of @llvm.aarch64.sve.ptrue.nxv16i1(i32 31) with splat (i1 true). (#204113)
|
2026-06-16 12:44:06 +01:00 |
|
sve2p1-intrinsics-bfmla.ll
|
|
|
|
sve2p1-intrinsics-bfmla_lane.ll
|
|
|
|
sve2p1-intrinsics-bfmls.ll
|
|
|
|
sve2p1-intrinsics-bfmls_lane.ll
|
|
|
|
sve2p1-intrinsics-bfmlsl.ll
|
|
|
|
sve2p1-intrinsics-bfmul.ll
|
[NFC][LLVM][Tests] Replace instances of @llvm.aarch64.sve.ptrue.nxv16i1(i32 31) with splat (i1 true). (#204113)
|
2026-06-16 12:44:06 +01:00 |
|
sve2p1-intrinsics-bfmul_lane.ll
|
|
|
|
sve2p1-intrinsics-bfsub.ll
|
[NFC][LLVM][Tests] Replace instances of @llvm.aarch64.sve.ptrue.nxv16i1(i32 31) with splat (i1 true). (#204113)
|
2026-06-16 12:44:06 +01:00 |
|
sve2p1-intrinsics-cntp.ll
|
|
|
|
sve2p1-intrinsics-crypto.ll
|
|
|
|
sve2p1-intrinsics-dots.ll
|
|
|
|
sve2p1-intrinsics-dupq.ll
|
|
|
|
sve2p1-intrinsics-extq.ll
|
|
|
|
sve2p1-intrinsics-fclamp.ll
|
|
|
|
sve2p1-intrinsics-fp-reduce.ll
|
|
|
|
sve2p1-intrinsics-gather-loads-128bit-index.ll
|
[LLVM][CodeGen] Remove +bf16 for ARM/AArch64 tests that don't strictly need the feature flag. (#204199)
|
2026-06-23 12:29:11 +01:00 |
|
sve2p1-intrinsics-gather-loads-128bit-unscaled-offset.ll
|
[LLVM][CodeGen] Remove +bf16 for ARM/AArch64 tests that don't strictly need the feature flag. (#204199)
|
2026-06-23 12:29:11 +01:00 |
|
sve2p1-intrinsics-int-reduce.ll
|
|
|
|
sve2p1-intrinsics-ld1-single.ll
|
|
|
|
sve2p1-intrinsics-loads.ll
|
|
|
|
sve2p1-intrinsics-multivec-loads.ll
|
|
|
|
sve2p1-intrinsics-multivec-stores.ll
|
|
|
|
sve2p1-intrinsics-pmov-to-pred.ll
|
|
|
|
sve2p1-intrinsics-pmov-to-vector.ll
|
|
|
|
sve2p1-intrinsics-predicate-as-counter.ll
|
|
|
|
sve2p1-intrinsics-qcvtn.ll
|
|
|
|
sve2p1-intrinsics-qrshr.ll
|
|
|
|
sve2p1-intrinsics-scatter-stores-128bit-index.ll
|
[LLVM][CodeGen] Remove +bf16 for ARM/AArch64 tests that don't strictly need the feature flag. (#204199)
|
2026-06-23 12:29:11 +01:00 |
|
sve2p1-intrinsics-scatter-stores-128bit-unscaled-offset.ll
|
[LLVM][CodeGen] Remove +bf16 for ARM/AArch64 tests that don't strictly need the feature flag. (#204199)
|
2026-06-23 12:29:11 +01:00 |
|
sve2p1-intrinsics-sclamp.ll
|
|
|
|
sve2p1-intrinsics-selx2.ll
|
|
|
|
sve2p1-intrinsics-selx4.ll
|
|
|
|
sve2p1-intrinsics-st1-single.ll
|
|
|
|
sve2p1-intrinsics-stores.ll
|
[AArch64][SME2] Add stridedorcontiguous pseudos for multi-vector-stores (#211551)
|
2026-07-30 16:21:59 +00:00 |
|
sve2p1-intrinsics-tblq.ll
|
[LLVM][CodeGen] Remove +bf16 for ARM/AArch64 tests that don't strictly need the feature flag. (#204199)
|
2026-06-23 12:29:11 +01:00 |
|
sve2p1-intrinsics-tbxq.ll
|
[LLVM][CodeGen] Remove +bf16 for ARM/AArch64 tests that don't strictly need the feature flag. (#204199)
|
2026-06-23 12:29:11 +01:00 |
|
sve2p1-intrinsics-uclamp.ll
|
|
|
|
sve2p1-intrinsics-unpk.ll
|
|
|
|
sve2p1-intrinsics-uzpq1.ll
|
[LLVM][CodeGen] Remove +bf16 for ARM/AArch64 tests that don't strictly need the feature flag. (#204199)
|
2026-06-23 12:29:11 +01:00 |
|
sve2p1-intrinsics-uzpq2.ll
|
[LLVM][CodeGen] Remove +bf16 for ARM/AArch64 tests that don't strictly need the feature flag. (#204199)
|
2026-06-23 12:29:11 +01:00 |
|
sve2p1-intrinsics-uzpx2.ll
|
|
|
|
sve2p1-intrinsics-uzpx4.ll
|
|
|
|
sve2p1-intrinsics-while-pn.ll
|
|
|
|
sve2p1-intrinsics-while-pp.ll
|
|
|
|
sve2p1-intrinsics-zipq1.ll
|
[LLVM][CodeGen] Remove +bf16 for ARM/AArch64 tests that don't strictly need the feature flag. (#204199)
|
2026-06-23 12:29:11 +01:00 |
|
sve2p1-intrinsics-zipq2.ll
|
[LLVM][CodeGen] Remove +bf16 for ARM/AArch64 tests that don't strictly need the feature flag. (#204199)
|
2026-06-23 12:29:11 +01:00 |
|
sve2p1-intrinsics-zipx2.ll
|
|
|
|
sve2p1-intrinsics-zipx4.ll
|
|
|
|
sve2p1-vector-shuffles.ll
|
[LLVM][CodeGen] Remove +bf16 for ARM/AArch64 tests that don't strictly need the feature flag. (#204199)
|
2026-06-23 12:29:11 +01:00 |
|
sve2p1-while-pn-folds.ll
|
[AArch64] Fold CSET + BR_CC into a conditional branch (#207398)
|
2026-07-14 08:07:35 +01:00 |
|
sve2p1_copy_pnr.mir
|
|
|
|
sve2p2-intrinsics-fp-arith.ll
|
|
|
|
sve2p2-intrinsics-fp-converts.ll
|
|
|
|
sve2p2-intrinsics.ll
|
|
|
|
sve2p3-dots-partial-reduction.ll
|
|
|
|
sve2p3-intrinsics-dots.ll
|
[AARCH64] Add intrinsic support for new s/udot intrinsics (#189424)
|
2026-05-05 15:42:48 +01:00 |
|
sve2p3-intrinsics-fp-converts.ll
|
[AArch64] Add 9.7 CVT data processing intrinsics (#186807)
|
2026-06-03 09:33:22 +01:00 |
|
sve2p3-intrinsics-fp-converts_x2.ll
|
[AArch64] Add 9.7 CVT data processing intrinsics (#186807)
|
2026-06-03 09:33:22 +01:00 |
|
sve2p3-intrinsics-luti6.ll
|
[AArch64][clang][llvm] Add ACLE Armv9.7 lookup table intrinsics (#187046)
|
2026-06-12 16:47:16 +01:00 |
|
svtcf-fmul-fdiv-combine.ll
|
|
|
|
swap-compare-operands.ll
|
[AArch64] Select CMP WZR, reg, shift #amount (#197424)
|
2026-05-21 09:19:52 +02:00 |
|
swift-async-context-seh.ll
|
|
|
|
swift-async-context-slot-offset-win.ll
|
|
|
|
swift-async-pei.ll
|
|
|
|
swift-async-reg.ll
|
|
|
|
swift-async-unwind.ll
|
|
|
|
swift-async-win.ll
|
|
|
|
swift-async.ll
|
|
|
|
swift-csr-win.ll
|
|
|
|
swift-dynamic-async-frame.ll
|
|
|
|
swift-error-unreachable-use.ll
|
|
|
|
swift-error.ll
|
|
|
|
swift-return.ll
|
|
|
|
swiftcc.ll
|
|
|
|
swifterror.ll
|
[RegAllocFast] Eliminate dead copies (#196056)
|
2026-05-15 16:47:07 +01:00 |
|
swiftself-scavenger.ll
|
[AArch64] Optimise materialisation of large stack offset calculations (#201856)
|
2026-06-24 15:02:00 +01:00 |
|
swiftself.ll
|
|
|
|
swifttail-arm64_32.ll
|
|
|
|
swifttail-async.ll
|
|
|
|
swifttail-call.ll
|
|
|
|
swifttail-funclet.ll
|
|
|
|
swifttail-ptrauth.ll
|
[llvm][AArch64] Fix the location of PAuth_LR AUT CFI (#211702)
|
2026-07-24 06:33:33 -07:00 |
|
switch-cases-to-branch-and.ll
|
|
|
|
switch-unreachable-default.ll
|
|
|
|
tagged-globals-pic.ll
|
[PAC][clang] Fix ptrauth module flags behavior (#204226)
|
2026-07-13 19:07:24 +00:00 |
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tagged-globals-static.ll
|
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tagp.ll
|
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tail-call-stack-args.ll
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tail-call-unused-zext.ll
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tail-call.ll
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tail-dup-redundant-phi.mir
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tail-duplicate-debug-variance.mir
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tailcall-bitcast-memcpy.ll
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tailcall-ccmismatch.ll
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tailcall-ccmismatch2.ll
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tailcall-explicit-sret.ll
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tailcall-fastisel.ll
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tailcall-implicit-sret.ll
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tailcall-mem-intrinsics.ll
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tailcall-ssp-split-debug.ll
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tailcall-string-rvo.ll
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tailcall_misched_graph.ll
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tailcc-notail.ll
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tailcc-tail-call.ll
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taildup-addrtaken.mir
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taildup-cfi.ll
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taildup-inst-dup-loc.mir
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taildup-ssa-update-pr62712.mir
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taildup-subreg-compose.mir
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tailmerging_in_mbp.ll
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tbi.ll
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tbl-loops.ll
|
[AArch64][ISel] Enable profile-aware branch condition merging (#201486)
|
2026-06-24 16:22:51 +01:00 |
|
tbz-tbnz.ll
|
[AArch64][ISel] Enable profile-aware branch condition merging (#201486)
|
2026-06-24 16:22:51 +01:00 |
|
tiny-model-pic.ll
|
[PAC][clang] Fix ptrauth module flags behavior (#204226)
|
2026-07-13 19:07:24 +00:00 |
|
tiny-model-static.ll
|
[PAC][clang] Fix ptrauth module flags behavior (#204226)
|
2026-07-13 19:07:24 +00:00 |
|
tiny_supported.ll
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trampoline.ll
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trunc-avg-fold.ll
|
[AArch64][GlobalISel] Normalize and cleanup some test checks. NFC (#195016)
|
2026-04-30 07:35:34 +01:00 |
|
trunc-nsw-nuw.ll
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trunc-to-tbl.ll
|
[Test] Fix loop exit conditions to prevent trivial optimizations (#201867)
|
2026-06-05 16:19:14 +00:00 |
|
trunc-v1i64.ll
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trunc.ll
|
[AArch64] Remove xtn.ll test. NFC (#193306)
|
2026-04-21 21:07:18 +01:00 |
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tst-br.ll
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typepromotion-cost.ll
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typepromotion-gep.ll
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typepromotion-overflow.ll
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typepromotion-phisret.ll
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typepromotion-signed.ll
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uadd_sat.ll
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uadd_sat_plus.ll
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uadd_sat_vec.ll
|
[AArch64][GlobalISel] Fold buildvector of bitcast (#141553)
|
2026-05-16 16:30:15 +01:00 |
|
uaddlp.ll
|
[AArch64] Additional Tablegen patterns for shuffle(zext(...)) and shuffle(sext(...)) to uaddlp (#195120)
|
2026-05-11 20:58:51 +05:30 |
|
uaddlv-vaddlp-combine.ll
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uaddo.ll
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ubsantrap.ll
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ucmp.ll
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udiv-by-const-promoted-ops.ll
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udiv-const-optimization.ll
|
[SelectionDAG] Widen even 33-bit-magic udiv on free-zext targets (#207634)
|
2026-07-09 10:01:05 +00:00 |
|
udivmodei5.ll
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umin-sub-to-usubo-select-combine.ll
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uminp-umaxp.ll
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umov-fpr-store-from-phi.ll
|
[AArch64] Fold UMOV(lane 0) + GPR store in FPR store (#199139)
|
2026-06-04 10:25:10 -07:00 |
|
umul_fix.ll
|
[AArch64][GlobalISel] Update and cleanup s/umul.fix tests. NFC (#211232)
|
2026-07-22 12:05:54 +01:00 |
|
umul_fix_sat.ll
|
[SelectionDAG][AArch64][X86] Don't scalarize vector smul.fix.sat/umul.fix.sat (#209351)
|
2026-07-23 12:11:04 +00:00 |
|
umulo-128-legalisation-lowering.ll
|
[AArch64] optimize lowering for icmp on i128 when RHS is an immediate (#181822)
|
2026-07-06 17:20:43 +01:00 |
|
unfold-masked-merge-scalar-constmask-innerouter.ll
|
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unfold-masked-merge-scalar-constmask-interleavedbits.ll
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unfold-masked-merge-scalar-constmask-interleavedbytehalves.ll
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unfold-masked-merge-scalar-constmask-lowhigh.ll
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unfold-masked-merge-scalar-variablemask.ll
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unfold-masked-merge-vector-variablemask-const.ll
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unfold-masked-merge-vector-variablemask.ll
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|
unreachable-emergency-spill-slot.mir
|
[CodeGen] Rename prologpeilog to prolog-epilog (#207870)
|
2026-07-06 18:26:05 -07:00 |
|
unsupported-cc-call.ll
|
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unsupported-cc-func.ll
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unsupported-fpext-x86-fp80.ll
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unsupported-object-format-err.ll
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unwind-preserved-from-mir.mir
|
[CodeGen] Rename prologpeilog to prolog-epilog (#207870)
|
2026-07-06 18:26:05 -07:00 |
|
unwind-preserved.ll
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|
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|
urem-lkk.ll
|
[GIsel] Add combine (sub a, (mul x, C)) -> (add a, (mul x, -C)) (#194282)
|
2026-05-04 10:50:27 -07:00 |
|
urem-seteq-illegal-types.ll
|
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|
urem-seteq-nonzero.ll
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urem-seteq-optsize.ll
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urem-seteq-vec-nonsplat.ll
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urem-seteq-vec-nonzero.ll
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urem-seteq-vec-splat.ll
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urem-seteq-vec-tautological.ll
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urem-seteq.ll
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|
urem-vector-lkk.ll
|
|
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|
use-cr-result-of-dom-icmp-st.ll
|
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|
ushl_sat.ll
|
[DAG] Fold any-extend(and(trunc(x), C)) -> and(x, C) (#200052)
|
2026-06-03 17:48:40 +02:00 |
|
usub_sat.ll
|
|
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|
usub_sat_plus.ll
|
[AArch64][SelectionDAG] Generate subs+csel for usub.sat (#193203)
|
2026-04-28 09:20:29 +05:30 |
|
usub_sat_vec.ll
|
[AArch64][GlobalISel] Fold buildvector of bitcast (#141553)
|
2026-05-16 16:30:15 +01:00 |
|
v2i64-min-max.ll
|
[AArch64][ISel] Use SVE for fixed width vector reductions (#195806)
|
2026-05-13 10:29:48 +01:00 |
|
v3f-to-int.ll
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|
v8.2a-neon-intrinsics-constrained.ll
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|
v8.4-atomic-128.ll
|
[AArch64] fix 128-bit Sequentially Consistent load (#206936)
|
2026-07-09 10:16:48 +01:00 |
|
v8.4-atomic.ll
|
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|
v8.5a-neon-frint3264-intrinsic.ll
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|
v8.5a-scalar-frint3264-intrinsic.ll
|
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|
vacg.ll
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|
vararg-tallcall.ll
|
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|
vararg.ll
|
Revert "[AArch64][GlobalISel] Do not run the Localizer at -O0 (#177359)" (#193781)
|
2026-04-23 16:38:44 +01:00 |
|
varargs-fixed-i16.ll
|
|
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|
variant-pcs.ll
|
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|
vcvt-oversize.ll
|
|
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|
vec-combine-compare-to-bitmask.ll
|
[AArch64] Use ADDP tree for v16i8 to i16 bitmask extraction (#199812)
|
2026-05-31 10:05:50 +00:00 |
|
vec-combine-compare-truncate-store.ll
|
[AArch64] Use ADDP tree for v16i8 to i16 bitmask extraction (#199812)
|
2026-05-31 10:05:50 +00:00 |
|
vec-combine-trunc-dup-ext.ll
|
[AArch64][GlobalISel] More test updates for vector select. NFC (#197023)
|
2026-05-11 20:58:04 +01:00 |
|
vec-extract-branch.ll
|
|
|
|
vec-libcalls.ll
|
|
|
|
vec3-loads-ext-trunc-stores.ll
|
[AArch64] Protect against v3i64->v3i8 truncates in combineI8TruncStore (#202039)
|
2026-06-06 14:14:56 +01:00 |
|
vec_uaddo.ll
|
[AArch64] Use dup (lane mov) over ext for high-half extract (#195010)
|
2026-05-11 07:31:59 +00:00 |
|
vec_umulo.ll
|
[AArch64] Use dup (lane mov) over ext for high-half extract (#195010)
|
2026-05-11 07:31:59 +00:00 |
|
veclib-llvm.modf.ll
|
|
|
|
veclib-llvm.pow.ll
|
[AArch64][NFC] Fix veclib-llvm.pow.ll test to run all pre-isel passes (#193996)
|
2026-04-27 09:47:56 +01:00 |
|
veclib-llvm.sincos.ll
|
|
|
|
veclib-llvm.sincospi.ll
|
|
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|
vecreduce-add-legalization.ll
|
|
|
|
vecreduce-add.ll
|
[DAGCombiner] Reassociate chains of vector reductions (#206471)
|
2026-07-03 03:32:02 +00:00 |
|
vecreduce-and-legalization.ll
|
[AArch64] Use dup (lane mov) over ext for high-half extract (#195010)
|
2026-05-11 07:31:59 +00:00 |
|
vecreduce-bitext.ll
|
[AArch64] Use dup (lane mov) over ext for high-half extract (#195010)
|
2026-05-11 07:31:59 +00:00 |
|
vecreduce-bool.ll
|
|
|
|
vecreduce-fadd-legalization-strict.ll
|
|
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|
vecreduce-fadd-legalization.ll
|
|
|
|
vecreduce-fadd-strict.ll
|
|
|
|
vecreduce-fadd.ll
|
[DAGCombiner] Reassociate chains of vector reductions (#206471)
|
2026-07-03 03:32:02 +00:00 |
|
vecreduce-fmax-legalization-nan.ll
|
|
|
|
vecreduce-fmax-legalization.ll
|
|
|
|
vecreduce-fmaximum.ll
|
|
|
|
vecreduce-fmin-legalization.ll
|
|
|
|
vecreduce-fminimum.ll
|
|
|
|
vecreduce-fmul-legalization-strict.ll
|
|
|
|
vecreduce-fmul-strict.ll
|
|
|
|
vecreduce-fmul.ll
|
[DAGCombiner] Reassociate chains of vector reductions (#206471)
|
2026-07-03 03:32:02 +00:00 |
|
vecreduce-mul-constant-fold.ll
|
[SelectionDAG] Fold VECREDUCE_MUL of a constant BUILD_VECTOR (#210126)
|
2026-07-20 21:38:45 +00:00 |
|
vecreduce-propagate-sd-flags.ll
|
|
|
|
vecreduce-umax-legalization.ll
|
[AArch64] Use dup (lane mov) over ext for high-half extract (#195010)
|
2026-05-11 07:31:59 +00:00 |
|
vector-absolute-difference.ll
|
[LLVM][CodeGen][SVE] Use pairwise instruction for partial_reduce_[s/u]mla. (#212772)
|
2026-07-31 11:27:08 +01:00 |
|
vector-compress.ll
|
|
|
|
vector-deinterleave-load.ll
|
[AArch64] Add combine for interleave deinterleave (#208414)
|
2026-07-20 09:39:13 +01:00 |
|
vector-div-by-promoted-const-no-assertion.ll
|
|
|
|
vector-extract-last-active.ll
|
[LLVM][CodeGen] Remove +bf16 for ARM/AArch64 tests that don't strictly need the feature flag. (#204199)
|
2026-06-23 12:29:11 +01:00 |
|
vector-fcopysign.ll
|
|
|
|
vector-fcvt.ll
|
[AArch64] Use dup (lane mov) over ext for high-half extract (#195010)
|
2026-05-11 07:31:59 +00:00 |
|
vector-gep.ll
|
|
|
|
vector-global-i1.ll
|
|
|
|
vector-insert-dag-combines.ll
|
|
|
|
vector-insert-shuffle-cycle.ll
|
|
|
|
vector-interleave-store.ll
|
[AArch64] Add combine for interleave deinterleave (#208414)
|
2026-07-20 09:39:13 +01:00 |
|
vector-ldst-offset.ll
|
|
|
|
vector-llrint.ll
|
[AArch64] Use dup (lane mov) over ext for high-half extract (#195010)
|
2026-05-11 07:31:59 +00:00 |
|
vector-lrint.ll
|
[AArch64] Use dup (lane mov) over ext for high-half extract (#195010)
|
2026-05-11 07:31:59 +00:00 |
|
vector-minmax.ll
|
|
|
|
vector-op-scalarize-strict.ll
|
|
|
|
vector-popcnt-128-ult-ugt.ll
|
|
|
|
vector-splice-compress-mmo-align.ll
|
[SelectionDAG] Don't over-claim alignment on vector splice/compress stack MMOs (#200622)
|
2026-06-01 21:09:45 -07:00 |
|
vector-to-scalar-bitmask.ll
|
|
|
|
vector_merge_dep_check.ll
|
|
|
|
vector_splat-const-shift-of-constmasked.ll
|
|
|
|
verify-imm.mir
|
[AArch64] Add a OPERAND_IMM_UINT1 operand type (#211986)
|
2026-07-25 06:20:16 +01:00 |
|
verify-memop.mir
|
|
|
|
vldn_shuffle.ll
|
[DAG] SimplifyDemandedVectorElts - always attempt SimplifyMultipleUseDemandedVectorElts call for ISD::EXTRACT_SUBVECTOR (#204351)
|
2026-06-17 13:50:42 +00:00 |
|
volatile-combine.ll
|
|
|
|
volatile-reg-writeback.ll
|
[AArch64] Do not generate indexed addressing mode for volatile accesses (#196305)
|
2026-05-28 13:08:05 +00:00 |
|
vqabs.ll
|
[AArch64] Add sqneg tablegen patterns (#196265)
|
2026-05-08 14:44:07 +01:00 |
|
vqneg.ll
|
[AArch64] Add sqneg tablegen patterns (#196265)
|
2026-05-08 14:44:07 +01:00 |
|
vscale-and-sve-cnt-demandedbits.ll
|
|
|
|
vscale-constant-range.ll
|
|
|
|
vscale-power-of-two.ll
|
|
|
|
vselect-constants.ll
|
|
|
|
vselect-ext.ll
|
[AArch64] Use dup (lane mov) over ext for high-half extract (#195010)
|
2026-05-11 07:31:59 +00:00 |
|
vselect-masked-shift.ll
|
[AArch64] Fold vector shifts guarded against oversized amounts into USHL (#207628)
|
2026-07-20 08:51:44 +01:00 |
|
wide-scalar-shift-by-byte-multiple-legalization.ll
|
|
|
|
wide-scalar-shift-legalization.ll
|
|
|
|
win-align-chkstk.ll
|
|
|
|
win-alloca-no-stack-probe.ll
|
|
|
|
win-alloca.ll
|
|
|
|
win-catchpad-nested-cxx.ll
|
|
|
|
win-import-call-optimization-nocalls.ll
|
|
|
|
win-import-call-optimization.ll
|
|
|
|
win-loader-replaceable-function.ll
|
|
|
|
win-realign.ll
|
|
|
|
win-sve.ll
|
|
|
|
win-tls.ll
|
|
|
|
win64-fpowi.ll
|
|
|
|
win64-jumptable.ll
|
|
|
|
win64-no-uwtable.ll
|
|
|
|
win64-nocfi.ll
|
|
|
|
win64_vararg.ll
|
|
|
|
win64_vararg2.ll
|
|
|
|
win64_vararg_float.ll
|
Revert "[AArch64][GlobalISel] Do not run the Localizer at -O0 (#177359)" (#193781)
|
2026-04-23 16:38:44 +01:00 |
|
win64_vararg_float_cc.ll
|
Revert "[AArch64][GlobalISel] Do not run the Localizer at -O0 (#177359)" (#193781)
|
2026-04-23 16:38:44 +01:00 |
|
win64cc-backup-x18.ll
|
|
|
|
win64cc-darwin-backup-x18.ll
|
|
|
|
win64cc-x18.ll
|
|
|
|
win_cst_pool.ll
|
|
|
|
wincfi-minimal-seh-prologue.ll
|
|
|
|
wincfi-missing-seh-directives.ll
|
|
|
|
windows-elf-frame-record-pairing.ll
|
[AArch64] Fix Windows target detection in FrameLowering (#204347)
|
2026-06-19 09:36:00 +01:00 |
|
windows-extern-weak.ll
|
|
|
|
windows-pac-invalid-a-key.ll
|
[AArch64][COFF] Branch-protection=standard/pac-ret means "b-key" on Windows (#203989)
|
2026-07-17 00:04:26 +03:00 |
|
windows-SEH-support.ll
|
|
|
|
windows-trap.ll
|
|
|
|
wineh-align-stack.ll
|
|
|
|
wineh-aligned-stack-obj.ll
|
|
|
|
wineh-bti-funclet.ll
|
|
|
|
wineh-bti.ll
|
[AArch64][COFF] Branch-protection=standard/pac-ret means "b-key" on Windows (#203989)
|
2026-07-17 00:04:26 +03:00 |
|
wineh-catchret-label-generation.ll
|
|
|
|
wineh-dangling-eh-pad-reference.ll
|
|
|
|
wineh-frame-predecrement.mir
|
[CodeGen] Rename prologpeilog to prolog-epilog (#207870)
|
2026-07-06 18:26:05 -07:00 |
|
wineh-frame-scavenge.mir
|
[CodeGen] Rename prologpeilog to prolog-epilog (#207870)
|
2026-07-06 18:26:05 -07:00 |
|
wineh-frame0.mir
|
[CodeGen] Rename prologpeilog to prolog-epilog (#207870)
|
2026-07-06 18:26:05 -07:00 |
|
wineh-frame1.mir
|
[CodeGen] Rename prologpeilog to prolog-epilog (#207870)
|
2026-07-06 18:26:05 -07:00 |
|
wineh-frame2.mir
|
[CodeGen] Rename prologpeilog to prolog-epilog (#207870)
|
2026-07-06 18:26:05 -07:00 |
|
wineh-frame3.mir
|
[CodeGen] Rename prologpeilog to prolog-epilog (#207870)
|
2026-07-06 18:26:05 -07:00 |
|
wineh-frame4.mir
|
[CodeGen] Rename prologpeilog to prolog-epilog (#207870)
|
2026-07-06 18:26:05 -07:00 |
|
wineh-frame5.mir
|
[CodeGen] Rename prologpeilog to prolog-epilog (#207870)
|
2026-07-06 18:26:05 -07:00 |
|
wineh-frame6.mir
|
[CodeGen] Rename prologpeilog to prolog-epilog (#207870)
|
2026-07-06 18:26:05 -07:00 |
|
wineh-frame7.mir
|
[CodeGen] Rename prologpeilog to prolog-epilog (#207870)
|
2026-07-06 18:26:05 -07:00 |
|
wineh-frame8.mir
|
[CodeGen] Rename prologpeilog to prolog-epilog (#207870)
|
2026-07-06 18:26:05 -07:00 |
|
wineh-mingw.ll
|
|
|
|
wineh-pac.ll
|
|
|
|
wineh-save-lrpair1.mir
|
[CodeGen] Rename prologpeilog to prolog-epilog (#207870)
|
2026-07-06 18:26:05 -07:00 |
|
wineh-save-lrpair2.mir
|
[CodeGen] Rename prologpeilog to prolog-epilog (#207870)
|
2026-07-06 18:26:05 -07:00 |
|
wineh-save-lrpair3.mir
|
[CodeGen] Rename prologpeilog to prolog-epilog (#207870)
|
2026-07-06 18:26:05 -07:00 |
|
wineh-try-catch-cbz.ll
|
|
|
|
wineh-try-catch-nobase.ll
|
|
|
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wineh-try-catch-realign.ll
|
|
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wineh-try-catch-vla.ll
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wineh-try-catch.ll
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wineh-unwindhelp-via-fp.ll
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wineh1.mir
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[CodeGen] Rename prologpeilog to prolog-epilog (#207870)
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2026-07-06 18:26:05 -07:00 |
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wineh2.mir
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[CodeGen] Rename prologpeilog to prolog-epilog (#207870)
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2026-07-06 18:26:05 -07:00 |
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wineh3.mir
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[CodeGen] Rename prologpeilog to prolog-epilog (#207870)
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2026-07-06 18:26:05 -07:00 |
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wineh4.mir
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[CodeGen] Rename prologpeilog to prolog-epilog (#207870)
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2026-07-06 18:26:05 -07:00 |
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wineh5.mir
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[CodeGen] Rename prologpeilog to prolog-epilog (#207870)
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2026-07-06 18:26:05 -07:00 |
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wineh6.mir
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[CodeGen] Rename prologpeilog to prolog-epilog (#207870)
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2026-07-06 18:26:05 -07:00 |
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wineh7.mir
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[CodeGen] Rename prologpeilog to prolog-epilog (#207870)
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2026-07-06 18:26:05 -07:00 |
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wineh8.mir
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[CodeGen] Rename prologpeilog to prolog-epilog (#207870)
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2026-07-06 18:26:05 -07:00 |
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wineh9.mir
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[AMDGPU][NFC] Update MIR tests to use symbolic INLINEASM operands (#186839)
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2026-04-17 12:23:56 +01:00 |
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wineh_shrinkwrap.mir
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[CodeGen] Rename prologpeilog to prolog-epilog (#207870)
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2026-07-06 18:26:05 -07:00 |
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write-volatile-register.ll
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[CodeGen] Mark read_register of allocatable physreg as live-in (#200825)
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2026-06-03 14:57:12 -07:00 |
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wrong-callee-save-size-after-livedebugvariables.mir
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[CodeGen] Rename prologpeilog to prolog-epilog (#207870)
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2026-07-06 18:26:05 -07:00 |
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wrong_debug_loc_after_regalloc.ll
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xar.ll
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xbfiz.ll
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xor-min-max.ll
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xor.ll
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xray-attribute-instrumentation.ll
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xray-custom-log.ll
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xray-omit-function-index.ll
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xray-partial-instrumentation-skip-entry.ll
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xray-partial-instrumentation-skip-exit.ll
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xray-tail-call-sled.ll
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zero-call-used-regs-no-neon.ll
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[AArch64] Fix zero-call-used-regs crash on targets without NEON (#211603)
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2026-07-31 13:56:50 -07:00 |
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zero-call-used-regs.ll
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[clang] Add more test coverage for "zero-call-used-regs" (#201834)
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2026-06-09 08:40:01 -07:00 |
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zero-reg.ll
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zeroing-forms-abs-neg.ll
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[NFC][LLVM][Tests] Replace instances of @llvm.aarch64.sve.ptrue.nxv16i1(i32 31) with splat (i1 true). (#204113)
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2026-06-16 12:44:06 +01:00 |
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zeroing-forms-counts-not.ll
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[LLVM][CodeGen] Remove +bf16 for ARM/AArch64 tests that don't strictly need the feature flag. (#204199)
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2026-06-23 12:29:11 +01:00 |
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zeroing-forms-ext.ll
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[NFC][LLVM][Tests] Replace instances of @llvm.aarch64.sve.ptrue.nxv16i1(i32 31) with splat (i1 true). (#204113)
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2026-06-16 12:44:06 +01:00 |
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zeroing-forms-fcvt-bfcvt.ll
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[NFC][LLVM][Tests] Replace instances of @llvm.aarch64.sve.ptrue.nxv16i1(i32 31) with splat (i1 true). (#204113)
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2026-06-16 12:44:06 +01:00 |
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zeroing-forms-fcvtlt-fcvtx.ll
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[NFC][LLVM][Tests] Replace instances of @llvm.aarch64.sve.ptrue.nxv16i1(i32 31) with splat (i1 true). (#204113)
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2026-06-16 12:44:06 +01:00 |
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zeroing-forms-fcvtzsu.ll
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[NFC][LLVM][Tests] Replace instances of @llvm.aarch64.sve.ptrue.nxv16i1(i32 31) with splat (i1 true). (#204113)
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2026-06-16 12:44:06 +01:00 |
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zeroing-forms-flogb.ll
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[NFC][LLVM][Tests] Replace instances of @llvm.aarch64.sve.ptrue.nxv16i1(i32 31) with splat (i1 true). (#204113)
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2026-06-16 12:44:06 +01:00 |
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zeroing-forms-frint-frecpx-fsqrt.ll
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[NFC][LLVM][Tests] Replace instances of @llvm.aarch64.sve.ptrue.nxv16i1(i32 31) with splat (i1 true). (#204113)
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2026-06-16 12:44:06 +01:00 |
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zeroing-forms-rev.ll
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[NFC][LLVM][Tests] Replace instances of @llvm.aarch64.sve.ptrue.nxv16i1(i32 31) with splat (i1 true). (#204113)
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2026-06-16 12:44:06 +01:00 |
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zeroing-forms-urecpe-ursqrte-sqabs-sqneg.ll
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[NFC][LLVM][Tests] Replace instances of @llvm.aarch64.sve.ptrue.nxv16i1(i32 31) with splat (i1 true). (#204113)
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2026-06-16 12:44:06 +01:00 |
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zeroing-forms-uscvtf.ll
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[NFC][LLVM][Tests] Replace instances of @llvm.aarch64.sve.ptrue.nxv16i1(i32 31) with splat (i1 true). (#204113)
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2026-06-16 12:44:06 +01:00 |
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zext-logic-shift-load.ll
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zext-reg-coalesce.mir
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zext-shuffle.ll
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[AArch64] Use dup (lane mov) over ext for high-half extract (#195010)
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2026-05-11 07:31:59 +00:00 |
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zext-to-tbl.ll
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[AArch64] Correct A510 scheduling information for LDn instructions (#205518)
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2026-06-25 14:52:48 +01:00 |
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zext.ll
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[AArch64] Use dup (lane mov) over ext for high-half extract (#195010)
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2026-05-11 07:31:59 +00:00 |
