67a20745d6
Currently, it is unclear if a test that is skipped is either:
- Unsupported because it will never run (macosx tests should not run on
Windows).
- Skipped because it's supposed to work but does not yet.
`@expectedFailure` is not always an option because a test might be
timing out and waiting 600s for it to fail is not acceptable.
This patch introduces 2 new decorators to differentiate those tests:
- `@requireX` meaning the tests require X to run (e.g `@requireDarwin`).
- `@requireNotX` meaning the tests requires anything but `X` to run (e.g
`@requireNotDarwin`).
In the tests results summary, this introduces a new category: `skipped`
tests:
- `@requireX` -> `UNSUPPORTED`
- `@skipIfX` -> `SKIPPED`
Here is how they can and cannot be stacked:
This will never run:
```py3
@requireDarwin
@requireWindows
def test():
...
```
This will not run on Linux, because `@requireWindows` is not satisfied.
```py3
@requireNotDarwin
@requireWindows
def test():
...
```
For "require Darwin or Windows", you need:
```py3
@requirePlatform(["darwin", "windows"])
def test():
...
```
For "require Darwin on ARM64 or Windows on ARM64", you need:
```py3
@requireARM64
@requirePlatform(["darwin", "windows"])
def test():
...
```
This patch also converts the tests in
`lldb/tests/API/{macosx,linux,windows}` to use these decorators. Patches
to convert the rest of the tests will follow.
92 lines
3.6 KiB
Python
92 lines
3.6 KiB
Python
"""
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Tests debugserver support for MultiMemRead.
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"""
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import lldb
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from lldbsuite.test.decorators import *
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from lldbsuite.test.lldbtest import *
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from lldbsuite.test import lldbutil
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@requireDarwin
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@skipIfOutOfTreeDebugserver
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class TestCase(TestBase):
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def check_invalid_packet(self, packet_str):
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reply = lldbutil.send_packet_get_reply(self, "packet_str")
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self.assertEqual(reply, "E03")
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def send_process_packet(self, packet_str):
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return lldbutil.send_packet_get_reply(self, packet_str)
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def test_packets(self):
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self.build()
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source_file = lldb.SBFileSpec("main.c")
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target, process, thread, bkpt = lldbutil.run_to_source_breakpoint(
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self, "break here", source_file
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)
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capabilities = lldbutil.get_qsupported_capabilities(self)
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self.assertIn("MultiMemRead+", capabilities)
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mem_address_var = thread.frames[0].FindVariable("memory")
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self.assertTrue(mem_address_var)
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mem_address = mem_address_var.GetValueAsUnsigned() + 42
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# no ":"
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self.check_invalid_packet("MultiMemRead")
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# missing ranges
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self.check_invalid_packet("MultiMemRead:")
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# needs at least one range
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self.check_invalid_packet("MultiMemRead:ranges:")
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# needs at least one range
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self.check_invalid_packet("MultiMemRead:ranges:,")
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# a range is a pair of numbers
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self.check_invalid_packet("MultiMemRead:ranges:10")
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# a range is a pair of numbers
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self.check_invalid_packet("MultiMemRead:ranges:10,")
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# range list must end with ;
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self.check_invalid_packet("MultiMemRead:ranges:10,2")
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self.check_invalid_packet("MultiMemRead:ranges:10,2,")
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self.check_invalid_packet("MultiMemRead:ranges:10,2,3")
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# ranges are pairs of numbers.
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self.check_invalid_packet("MultiMemRead:ranges:10,2,3;")
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# unrecognized field
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self.check_invalid_packet("MultiMemRead:ranges:10,2;blah:;")
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# unrecognized field
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self.check_invalid_packet("MultiMemRead:blah:;ranges:10,2;")
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# Zero-length reads are ok.
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reply = self.send_process_packet("MultiMemRead:ranges:0,0;")
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self.assertEqual(reply, "0;")
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# Debugserver is permissive with trailing commas.
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reply = self.send_process_packet("MultiMemRead:ranges:10,2,;")
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self.assertEqual(reply, "0;")
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reply = self.send_process_packet(f"MultiMemRead:ranges:{mem_address:x},2,;")
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self.assertEqual(reply, "2;ab")
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reply = self.send_process_packet("MultiMemRead:ranges:10,2;")
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self.assertEqual(reply, "0;")
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reply = self.send_process_packet(f"MultiMemRead:ranges:{mem_address:x},0;")
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self.assertEqual(reply, "0;")
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reply = self.send_process_packet(f"MultiMemRead:ranges:{mem_address:x},2;")
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self.assertEqual(reply, "2;ab")
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reply = self.send_process_packet(
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f"MultiMemRead:ranges:{mem_address:x},2,{mem_address+2:x},4;"
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)
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self.assertEqual(reply, "2,4;abcdef")
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reply = self.send_process_packet(
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f"MultiMemRead:ranges:{mem_address:x},2,{mem_address+2:x},4,{mem_address+6:x},8;"
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)
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self.assertEqual(reply, "2,4,8;abcdefghijklmn")
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# Test zero length in the middle.
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reply = self.send_process_packet(
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f"MultiMemRead:ranges:{mem_address:x},2,{mem_address+2:x},0,{mem_address+6:x},8;"
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)
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self.assertEqual(reply, "2,0,8;abghijklmn")
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# Test zero length in the end.
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reply = self.send_process_packet(
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f"MultiMemRead:ranges:{mem_address:x},2,{mem_address+2:x},4,{mem_address+6:x},0;"
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)
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self.assertEqual(reply, "2,4,0;abcdef")
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