mirror-llvm-project/mlir/test
Andrzej Warzyński de5cef3127
[mlir][vector] Extend combineContractAndBroadcast to accept vector.shape_cast (#208752)
`combineContractAndBroadcast` is a pattern that matches
`vector.contract` operations whose inputs are defined by
`vector.broadcast`, e.g.:

```mlir
%0 = vector.broadcast %lhs : vector<8x4xi32> to vector<1x8x4xi32>
%1 = vector.broadcast %rhs : vector<8x4xi32> to vector<1x8x4xi32>
%result = vector.contract {
    indexing_maps = [#map0, #map1, #map2],
    iterator_types = ["reduction", "parallel", "parallel", "reduction"],
    kind = #vector.kind<add>
  } %0, %1, %acc : vector<1x8x4xi32>, vector<1x8x4xi32> into vector<8x8xi32>
```

The pattern folds away the reduction over a unit dimension introduced by
the defining operations, producing a simplified `vector.contract`:

```mlir
vector.contract {
  indexing_maps = [#[[$MAP0]], #[[$MAP1]], #[[$MAP2]]]
  iterator_types = ["parallel", "parallel", "reduction"]
} %0, %1, %acc : vector<8x4xi32>, vector<8x4xi32> into vector<8x8xi32>
```

This change extends the pattern to also accept broadcast-like
`vector.shape_cast` operations:

```mlir
%0 = vector.shape_cast %lhs : vector<8x4xi32> to vector<1x8x4xi32>
%1 = vector.shape_cast %rhs : vector<8x4xi32> to vector<1x8x4xi32>
%result = vector.contract {
    indexing_maps = [#map0, #map1, #map2],
    iterator_types = ["reduction", "parallel", "parallel", "reduction"],
    kind = #vector.kind<add>
  } %0, %1, %acc : vector<1x8x4xi32>, vector<1x8x4xi32> into vector<8x8xi32>
```

Note that `mlir::vector::isBroadcastableTo` was only moved to make it
available to the newly introduced `ShapeCastOp` helper,
`ShapeCastOp::isBroadcastLike()`.
2026-07-17 15:45:40 +00:00
..
Analysis Added a check for unsigned integer before accessing (#204276) 2026-06-18 10:10:35 -05:00
Bytecode [mlirbc] Fix use-list ordering during deserialization (#191942) 2026-04-15 05:36:13 -07:00
CAPI [mlir-c] Reapply Add ConversionTarget dynamic legality C API (#207104) (#207253) 2026-07-02 22:43:48 -07:00
Conversion [NVGPU] Add FP8 (e4m3/e5m2) support to nvgpu.mma.sync (#207342) 2026-07-16 07:41:49 +02:00
Dialect [mlir][vector] Extend combineContractAndBroadcast to accept vector.shape_cast (#208752) 2026-07-17 15:45:40 +00:00
Examples [mlir][NVGPU] Fix double spaces in tests after ODS printer fix. NFC. (#185327) 2026-03-08 21:00:02 -04:00
Integration [mlir][vector] Fix e2e test post #210090 (#210270) 2026-07-17 08:30:53 +00:00
Interfaces [mlir][tensor] Preserve tensor encodings when materializing tensor.empty in some passes (#192411) 2026-04-20 16:44:25 +08:00
IR [mlir] Fix visitor block erasure (#205854) 2026-06-25 22:50:17 +02:00
lib [mlir][scf] Validate pipelining annotations in test pass (#208788) 2026-07-10 22:53:19 +02:00
mlir-linalg-ods-gen
mlir-lsp-server [mlir][lsp] Use rootUri and rootPath for source files (#185479) 2026-04-07 14:13:47 +00:00
mlir-opt [MLIR] Fix crash in FrozenRewritePatternSet when PDL lowering is skipped by debug counter (#186159) 2026-03-18 16:01:49 +01:00
mlir-pdll [mlir] Fix C++ name hiding bug in PDLPatternMatch for Op classes (#195554) 2026-05-08 07:32:54 -07:00
mlir-pdll-lsp-server
mlir-query
mlir-reduce [mlir][reducer] Change mlir-reducer apply pattern logic (#195997) 2026-05-08 09:34:47 +08:00
mlir-rewrite
mlir-runner [AIX] XFAIL mlir testcases on AIX to be investigated NFC (#186157) 2026-03-12 15:29:15 -04:00
mlir-tblgen [MLIR] Fix broken 'Successor<CPred<...>>' functionality in mlir-tblgen (#205375) 2026-06-25 12:36:58 -06:00
mlir-translate [DebugInfo] Verify DISubprogram has a type (#194556) 2026-05-04 11:32:19 +01:00
Pass [mlir][core] in -mlir-print-ir-*, dump the pass options as well (#195198) 2026-05-08 06:03:34 -07:00
python [mlir][python] Fix segfault at interpreter shutdown with entered contexts (#203826) 2026-06-15 12:32:36 -07:00
Rewrite [mlir][PDL] Support running pdl_interp.foreach on ranges of values and types (#173161) 2026-02-02 08:58:48 -08:00
Target [mlir][emitc] Add increment and decrement ops (#208648) 2026-07-16 10:36:07 +08:00
tblgen-lsp-server
tblgen-to-irdl
Transforms [mlir] Fix RDV poison cleanup (#206270) 2026-07-10 12:40:55 +02:00
Unit
APITest.h
CMakeLists.txt [mlir] Replace MLIR_ENABLE_ROCM_CONVERSIONS with LLVM_HAS_AMDGPU_TARGET (#182652) 2026-03-13 22:03:05 +00:00
get_darwin_real_python.py
lit.cfg.py [MLIR] Remove ability to use external shell 2026-07-14 18:09:09 -07:00
lit.site.cfg.py.in [mlir] Replace MLIR_ENABLE_ROCM_CONVERSIONS with LLVM_HAS_AMDGPU_TARGET (#182652) 2026-03-13 22:03:05 +00:00