[RISCV] Support spacemit vsmtvdotii extensions ( #202533 )
2026-07-13 19:05:52 +08:00
[RISCV] Support spacemit vsmtvdotii extensions ( #202533 )
2026-07-13 19:05:52 +08:00
Remove analysis preservations subsumed by CFG preservation. NFC ( #212672 )
2026-07-28 21:47:19 -07:00
[RISCV][MCA] Avoid deriving EMUL without SEW ( #207986 )
2026-07-09 11:29:43 +08:00
[MC][NFC] Remove some virtual function from MCAsmInfo ( #211858 )
2026-07-24 20:41:56 +02:00
[RISCV] Add a Pass for adding %qc.access specifiers ( #201938 )
2026-06-22 10:35:18 -07:00
[RISCV] Add a Pass for adding %qc.access specifiers ( #201938 )
2026-06-22 10:35:18 -07:00
[RISCV] Report all near-miss reasons in the AsmParser ( #205721 )
2026-07-01 13:58:36 -07:00
Reapply [IR] Explicitly specify target feature for module asm ( #204548 ) ( #207677 )
2026-07-06 11:57:38 +02:00
[RISCV] Add support for vector registers with -fzero-call-used-regs ( #206206 )
2026-07-27 09:37:37 +00:00
[RISCV] Add support for vector registers with -fzero-call-used-regs ( #206206 )
2026-07-27 09:37:37 +00:00
[PatternMatch] Add capturing m_Phi matcher (NFC) ( #208949 )
2026-07-12 09:39:05 +00:00
Remove analysis preservations subsumed by CFG preservation. NFC ( #212672 )
2026-07-28 21:47:19 -07:00
[RISCV] Support uimm5 operands for Xqcicm cmovs in RISCVExpandPseudoInsts ( #210955 )
2026-07-22 09:03:29 +05:30
[RISCV] Support spacemit vsmtvdotii extensions ( #202533 )
2026-07-13 19:05:52 +08:00
[RISCV] Fix RISCVFoldMemOffset to report when it makes changes ( #208149 )
2026-07-09 09:28:44 +08:00
[RISC-V] Fix assert after 255162a ( #212791 )
2026-07-29 15:53:36 +00:00
[RISCV] Add support for vector registers with -fzero-call-used-regs ( #206206 )
2026-07-27 09:37:37 +00:00
[InstCombine] Create or as disjoint where applicable ( #193725 )
2026-05-11 16:25:13 +02:00
[RISCV] Fix typo in ImmPlus1 SDNodeXForm ( #190785 )
2026-04-08 07:57:35 +08:00
[RISCV] Ensure LPAD alignment for calls to returns_twice functions ( #177515 )
2026-06-02 13:45:28 +08:00
Remove analysis preservations subsumed by CFG preservation. NFC ( #212672 )
2026-07-28 21:47:19 -07:00
[RISCV] Support spacemit vsmtvdotii extensions ( #202533 )
2026-07-13 19:05:52 +08:00
[RISCV] Add OPC_C0/C1/C2 named values to tablegen. NFC ( #178325 )
2026-01-27 22:55:47 -08:00
[RISCV] Support spacemit vsmtvdotii extensions ( #202533 )
2026-07-13 19:05:52 +08:00
[RISCV] Rename RVVConstraint->VS1VS2Constraint. NFC ( #182688 )
2026-02-23 08:58:14 -08:00
[RISCV] AI Foundry ET extensions for RISC-V ( #174571 )
2026-01-13 12:54:11 -08:00
[RISCV][GlobalISel] Lower i8 bitreverse using brev8 with Zbkb ( #199469 )
2026-05-26 13:51:17 +01:00
[RISCV] Don't move memory instructions across calls in isSafeToMove ( #212236 )
2026-07-28 19:19:15 +08:00
[RISCV] Add partial support for -fzero-call-used-regs ( #194883 )
2026-06-11 00:11:23 -07:00
[RISCV] Declare TLSDESC clobbers for vector registers and CSRs per psABI ( #205027 )
2026-07-27 09:39:08 +08:00
[RISCV] Use GPR instead of ixlenimm for sextshamt in PseudoMaskedAMOMinMax. NFC ( #171736 )
2025-12-10 20:43:46 -08:00
[RISC-V] Rename GPRCMem operand to BasePtrC. NFC
2026-06-16 14:18:28 -07:00
[RISCV] Support floating point registers with -fzero-call-used-regs ( #204929 )
2026-06-26 21:39:54 +00:00
[RISCV] Support floating point registers with -fzero-call-used-regs ( #204929 )
2026-06-26 21:39:54 +00:00
[Clang][RISCV] Add packed pair byte intrinsics ( #212589 )
2026-07-30 02:24:02 +08:00
[RISCV] Support floating point registers with -fzero-call-used-regs ( #204929 )
2026-06-26 21:39:54 +00:00
[RISC-V] Make Short Forward Branches capable of matching Zibi instructions ( #208637 )
2026-07-16 16:35:06 +08:00
[RISCV] Rework vmsge(u).vx pseudos to work better with near-miss assembler support ( #207097 )
2026-07-01 22:23:49 -07:00
[RISCV] Add support for vector registers with -fzero-call-used-regs ( #206206 )
2026-07-27 09:37:37 +00:00
[RISCV] Enable combineAddMulh for vectors to improve div by constant. ( #201657 )
2026-06-04 21:28:25 -07:00
[RISCV] Add custom lowering for fixed-vector CLMUL/CLMULH ( #210429 )
2026-07-27 23:51:29 -07:00
[RISCV][P-ext] Rename simm8_unsigned/simm10_unsigned used PLUI/PLI. NFC ( #188808 )
2026-03-31 14:48:17 -07:00
[RISCV] Use the nhs.lea.h/w/d instead of nhs.lea.h/w/d.ze with Sh1AddPat. ( #196660 )
2026-05-08 16:28:39 -07:00
[RISCV] Use simm12 instead of simm12_lo for CORE-V post-increment load/store. ( #207067 )
2026-07-02 07:07:16 -07:00
[RISC-V] Reduce code duplication for uimm*_lsb* operands. NFC
2026-01-25 21:45:00 -08:00
[RISCV] Add OPC_C0/C1/C2 named values to tablegen. NFC ( #178325 )
2026-01-27 22:55:47 -08:00
[RISCV] Add assembler and disassembler support for Xqccmt extension ( #197673 )
2026-05-19 10:50:27 +05:30
[RISCV] Fold 26-bit frame-index offsets into Xqcilo/Xqcilia load/store/addi ( #209315 )
2026-07-14 23:11:07 +05:30
[RISCV] Make ElementsDependOn opt-in instead of opt-out. NFCI ( #181601 )
2026-02-26 01:07:25 +08:00
[NFC][RISCV] Fix mismatched closing comment in XSfmm instruction definition ( #190898 )
2026-04-08 14:56:27 +08:00
[RISCV] Support spacemit vsmtvdotii extensions ( #202533 )
2026-07-13 19:05:52 +08:00
[RISCV] Rename add_like pattern -> riscv_add_like ( #187306 )
2026-03-18 16:26:03 +00:00
[RISC-V] Rename GPRCMem operand to BasePtrC. NFC
2026-06-16 14:18:28 -07:00
[RISC-V][MC] Introduce initial support for RVY (CHERI)
2026-05-29 10:04:43 -07:00
[RISCV] Fix address type in Zacas seq_cst atomic pattern ( #190729 )
2026-04-07 05:57:25 +00:00
[RISCV] Use the new "let append" TableGen feature to reduce duplication. NFC ( #199596 )
2026-05-25 22:37:26 -07:00
[RISC-V] Rename GPRCMem operand to BasePtrC. NFC
2026-06-16 14:18:28 -07:00
[RISCV][MC] Improve diagnostics for Zclsd RV32 GPR pair operands ( #207639 )
2026-07-06 21:19:08 -07:00
[RISCV] Make MOP/HINT-based instruction mnemonics always available ( #178609 )
2026-02-03 23:39:53 +08:00
[RISCV] Remove decodeRTZArg. NFC ( #177744 )
2026-01-24 11:08:57 -08:00
[RISCV][NFC] Push riscv_selectcc PatFrag Inwards ( #175902 )
2026-01-14 10:22:47 -08:00
[RISCV] Fix fcanonicalize for Z*inx ( #175984 )
2026-01-15 23:03:38 -08:00
[RISCV] Relax out of range Zibi conditional branches ( #186965 )
2026-03-19 21:07:53 +08:00
[RISC-V] Rename GPRMem operand to BasePtr. NFC
2026-06-16 11:32:43 -07:00
[RISCV] Use sspush/sspopchk mnemonics for shadow stack codegen ( #200182 )
2026-06-01 16:12:45 -07:00
[RISCV] Make ElementsDependOn opt-in instead of opt-out. NFCI ( #181601 )
2026-02-26 01:07:25 +08:00
[llvm][RISCV] Support batched dot product extensions MC layer ( #196467 )
2026-05-27 14:21:31 +00:00
[RISCV] Add scheduling data to vdot4aus.vx ( #204038 )
2026-06-15 20:37:18 -07:00
[RISCV][MC] Support experimental Zvdota Family instructions ( #195069 )
2026-06-04 16:45:05 +08:00
[RISCV] Consistently use hasVInstructionsF16/BF16(). NFC ( #191592 )
2026-04-11 16:11:17 +00:00
[RISCV][llvm] Support [s|u]int_to_fp and fp_to_[s|u]int for zvfbfa ( #192287 )
2026-04-21 09:09:18 +08:00
[RISCV] Add custom lowering for fixed-vector CLMUL/CLMULH ( #210429 )
2026-07-27 23:51:29 -07:00
[RISCV][MC] Add experimental Zvvmtls and Zvvmttls support ( #198229 )
2026-06-05 16:10:34 +08:00
[RISCV][CodeGen] Add initial CodeGen support of vunzip{e,o} ( #196024 )
2026-05-25 17:23:20 +08:00
[RISCV] Fold 26-bit frame-index offsets into Xqcilo/Xqcilia load/store/addi ( #209315 )
2026-07-14 23:11:07 +05:30
[IRBuilder] Refactor for intrinsics const-folding (NFC) ( #202738 )
2026-06-17 11:16:14 +00:00
[RISCV] Preserve call-preserved reg mask for LPAD-aligned calls ( #210868 )
2026-07-22 14:17:10 +08:00
[RISCV] Add SelectAddrRegImm26 isel complex pattern for Xqcilo 26-bit load/store ( #207363 )
2026-07-13 22:02:34 +05:30
[Clang][RISCV] Add packed pair byte intrinsics ( #212589 )
2026-07-30 02:24:02 +08:00
[RISCV][P-ext] Add packed sign and zero extend intrinsics ( #208685 )
2026-07-23 13:55:44 +08:00
[RISCV] Generate landing pad based on cf-protection-branch flag only ( #179960 )
2026-04-16 15:27:59 +00:00
[RISCV] Use MCRegister. NFC ( #210110 )
2026-07-16 18:05:10 +00:00
[RISCV] Generate landing pad based on cf-protection-branch flag only ( #179960 )
2026-04-16 15:27:59 +00:00
[RISCV] Fix musttail with indirect arguments by forwarding incoming pointers ( #185094 )
2026-05-20 08:54:50 -07:00
[RISCV] Schedule RVV instructions with compatible vtype/vl first
2026-01-12 12:02:39 +08:00
[RISCV] Schedule RVV instructions with compatible vtype/vl first
2026-01-12 12:02:39 +08:00
[RISCV] Add macro fusion support for the Xqci extension instructions ( #209542 )
2026-07-28 13:06:45 -07:00
[RISCV] Add macro fusion support for the Xqci extension instructions ( #209542 )
2026-07-28 13:06:45 -07:00
[RISCV] Run MakeCompresible at Os as well ( #207172 )
2026-07-06 05:48:31 +05:30
[RISCV] Merge Base Offset for SFB Pseudos ( #187620 )
2026-03-24 10:41:34 -07:00
[RISCV][P-ext] Add mvd alias for padd.dw rd, zero, rs. Use for copy idiom. ( #205223 )
2026-06-23 08:21:48 -07:00
[RISCV] Prevent RISCVOptWInstrs from shrinking volatile LD instructions. ( #200472 )
2026-05-30 22:02:52 -07:00
[RISCV] Add basic scalar support for MERGE, MVM, and MVMN from P extension ( #180677 )
2026-02-10 13:39:34 -08:00
Revert "[RISCV] Add TuneNoDefaultUnroll to generic CPUs ( #135318 )" ( #212400 )
2026-07-28 05:25:15 +00:00
[RISC-V] Do not emit cm.popret[z] with zicfiss ( #196267 )
2026-07-28 21:59:19 +02:00
[RISCV] Add a Pass for adding %qc.access specifiers ( #201938 )
2026-06-22 10:35:18 -07:00
[CodeGen] Add MachineRegisterClassInfo analysis pass ( #210826 )
2026-07-22 21:34:54 +02:00
[RISCV] Add support for vector registers with -fzero-call-used-regs ( #206206 )
2026-07-27 09:37:37 +00:00
[RISCV] Support floating point registers with -fzero-call-used-regs ( #204929 )
2026-06-26 21:39:54 +00:00
[RISCV][RVY] Fix DwarfRegAlias for X10_Y to X15_Y ( #210104 )
2026-07-16 17:55:24 +00:00
[RISCV] Rename VLSU_MEM_LATENCY to Andes45VLSU_MEM_LATENCY in RISCVSchedAndes45.td ( #209388 )
2026-07-15 09:07:09 +08:00
[RISCV] Use BufferSize = 0 for ProcResGroup in SiFive7 scheduling models ( #194754 )
2026-04-29 09:02:33 -07:00
[RISCV] Factor out common scheduling model part between SiFive P400 and P500. NFCI ( #199796 )
2026-05-28 09:55:24 -07:00
[RISCV] Update the ProcResource used by vsetvli in SiFiveP400 model ( #199802 )
2026-05-28 18:02:21 +00:00
[RISCV] Factor out common scheduling model part between SiFive P400 and P500. NFCI ( #199796 )
2026-05-28 09:55:24 -07:00
[RISCV] Fix wrong use of SiFiveP400GetVLMAX in RISCVSchedSiFiveP600 ( #171562 )
2025-12-10 13:59:13 +08:00
[RISCV] Assign separate latencies for vector COPYs in SpacemitX60 scheduling model ( #172556 )
2025-12-18 07:04:42 -08:00
[RISCV] Add SpacemiT X100 base scheduling model ( #178189 )
2026-02-09 11:36:45 +08:00
[RISCV] Rename Tenstorrent Ascalon D8 to Ascalon X ( #178199 )
2026-01-27 21:31:51 +00:00
[RISCV] Assign separate latencies for vector COPYs in SpacemitX60 scheduling model ( #172556 )
2025-12-18 07:04:42 -08:00
[NFC][ValueType] Add is*VectorOf(VT) helpers. ( #200189 )
2026-05-29 11:33:27 +01:00
[TableGen][RISCV] Generate pre/post-RA statistics for macro fusions ( #209394 )
2026-07-16 12:12:15 +00:00
[MCSched] Allow tuning LoadLatency/MispredictPenalty ( #203139 )
2026-07-15 16:18:20 -07:00
[RISCV] Avoid let statements in RISCVSystemOperands. NFC ( #207890 )
2026-07-08 08:18:40 -07:00
Reapply "[RISCV] Run EarlyMachineLICM before VLOptimizer to hoist constant splats" ( #210937 ) ( #211452 )
2026-07-23 03:38:51 +00:00
[RISCV] Put Large Code Model Constant Pools in .text ( #151393 )
2026-03-02 13:17:06 -08:00
[RISCV] Put Large Code Model Constant Pools in .text ( #151393 )
2026-03-02 13:17:06 -08:00
Revert "[RISCV] Add TuneNoDefaultUnroll to generic CPUs ( #135318 )" ( #212400 )
2026-07-28 05:25:15 +00:00
[RISCV] Enumerate all RecurKind cases in isLegalToVectorizeReduction. nfc ( #207932 )
2026-07-07 17:26:28 +08:00
[RISCV] Fix ensureDominates with successive defs ( #203174 )
2026-06-11 15:23:50 +08:00
[RISCV] Remove experimental XRivosVizip support ( #200761 )
2026-06-03 10:07:32 +08:00
[RISCV] Use a switch default+llvm_unreachable instead of an assert. NFC ( #189770 )
2026-03-31 18:12:32 -07:00
[RISCV] Make SFMM configuration instruction emit like VSETVLI ( #196487 )
2026-05-13 02:34:29 +00:00
[RISCV] Avoid forming Zilsd pairs with x0 for non-x0 register classes ( #211019 )
2026-07-22 10:04:23 +05:30
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