33c7ef4a63
Add the 32-bit byte forms and the 64-bit byte/halfword forms of the P-extension packed pair intrinsics to riscv_packed_simd.h using generic shufflevector IR. Extend the existing packed pair shuffle lowering to recognize the mixed even/odd forms and select ppaireo/ppairoe in addition to ppaire/ppairo. Add Clang CodeGen, LLVM CodeGen, and intrinsic header tests for the new forms.
9355 lines
449 KiB
C
9355 lines
449 KiB
C
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 6
|
|
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-p \
|
|
// RUN: -disable-O0-optnone -emit-llvm -o - %s \
|
|
// RUN: | opt -S -passes=sroa,instcombine | FileCheck %s --check-prefix=RV32
|
|
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-p \
|
|
// RUN: -disable-O0-optnone -emit-llvm -o - %s \
|
|
// RUN: | opt -S -passes=sroa,instcombine | FileCheck %s --check-prefix=RV64
|
|
|
|
#include <riscv_packed_simd.h>
|
|
|
|
/* Packed Splat (32-bit) */
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_pmv_s_u8x4(
|
|
// RV32-SAME: i8 noundef zeroext [[X:%.*]]) #[[ATTR0:[0-9]+]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x i8> poison, i8 [[X]], i64 0
|
|
// RV32-NEXT: [[VECINIT3_I:%.*]] = shufflevector <4 x i8> [[VECINIT_I]], <4 x i8> poison, <4 x i32> zeroinitializer
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast <4 x i8> [[VECINIT3_I]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP0]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_pmv_s_u8x4(
|
|
// RV64-SAME: i8 noundef zeroext [[X:%.*]]) #[[ATTR0:[0-9]+]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x i8> poison, i8 [[X]], i64 0
|
|
// RV64-NEXT: [[VECINIT3_I:%.*]] = shufflevector <4 x i8> [[VECINIT_I]], <4 x i8> poison, <4 x i32> zeroinitializer
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast <4 x i8> [[VECINIT3_I]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP0]]
|
|
//
|
|
uint8x4_t test_pmv_s_u8x4(uint8_t x) {
|
|
return __riscv_pmv_s_u8x4(x);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_pmv_s_i8x4(
|
|
// RV32-SAME: i8 noundef signext [[X:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x i8> poison, i8 [[X]], i64 0
|
|
// RV32-NEXT: [[VECINIT3_I:%.*]] = shufflevector <4 x i8> [[VECINIT_I]], <4 x i8> poison, <4 x i32> zeroinitializer
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast <4 x i8> [[VECINIT3_I]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP0]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_pmv_s_i8x4(
|
|
// RV64-SAME: i8 noundef signext [[X:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x i8> poison, i8 [[X]], i64 0
|
|
// RV64-NEXT: [[VECINIT3_I:%.*]] = shufflevector <4 x i8> [[VECINIT_I]], <4 x i8> poison, <4 x i32> zeroinitializer
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast <4 x i8> [[VECINIT3_I]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP0]]
|
|
//
|
|
int8x4_t test_pmv_s_i8x4(int8_t x) {
|
|
return __riscv_pmv_s_i8x4(x);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_pmv_s_u16x2(
|
|
// RV32-SAME: i16 noundef zeroext [[X:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[VECINIT_I:%.*]] = insertelement <2 x i16> poison, i16 [[X]], i64 0
|
|
// RV32-NEXT: [[VECINIT1_I:%.*]] = shufflevector <2 x i16> [[VECINIT_I]], <2 x i16> poison, <2 x i32> zeroinitializer
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast <2 x i16> [[VECINIT1_I]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP0]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_pmv_s_u16x2(
|
|
// RV64-SAME: i16 noundef zeroext [[X:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[VECINIT_I:%.*]] = insertelement <2 x i16> poison, i16 [[X]], i64 0
|
|
// RV64-NEXT: [[VECINIT1_I:%.*]] = shufflevector <2 x i16> [[VECINIT_I]], <2 x i16> poison, <2 x i32> zeroinitializer
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast <2 x i16> [[VECINIT1_I]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP0]]
|
|
//
|
|
uint16x2_t test_pmv_s_u16x2(uint16_t x) {
|
|
return __riscv_pmv_s_u16x2(x);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_pmv_s_i16x2(
|
|
// RV32-SAME: i16 noundef signext [[X:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[VECINIT_I:%.*]] = insertelement <2 x i16> poison, i16 [[X]], i64 0
|
|
// RV32-NEXT: [[VECINIT1_I:%.*]] = shufflevector <2 x i16> [[VECINIT_I]], <2 x i16> poison, <2 x i32> zeroinitializer
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast <2 x i16> [[VECINIT1_I]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP0]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_pmv_s_i16x2(
|
|
// RV64-SAME: i16 noundef signext [[X:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[VECINIT_I:%.*]] = insertelement <2 x i16> poison, i16 [[X]], i64 0
|
|
// RV64-NEXT: [[VECINIT1_I:%.*]] = shufflevector <2 x i16> [[VECINIT_I]], <2 x i16> poison, <2 x i32> zeroinitializer
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast <2 x i16> [[VECINIT1_I]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP0]]
|
|
//
|
|
int16x2_t test_pmv_s_i16x2(int16_t x) {
|
|
return __riscv_pmv_s_i16x2(x);
|
|
}
|
|
|
|
/* Packed Splat (64-bit) */
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pmv_s_u8x8(
|
|
// RV32-SAME: i8 noundef zeroext [[X:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[VECINIT_I:%.*]] = insertelement <8 x i8> poison, i8 [[X]], i64 0
|
|
// RV32-NEXT: [[VECINIT7_I:%.*]] = shufflevector <8 x i8> [[VECINIT_I]], <8 x i8> poison, <8 x i32> zeroinitializer
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast <8 x i8> [[VECINIT7_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP0]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pmv_s_u8x8(
|
|
// RV64-SAME: i8 noundef zeroext [[X:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[VECINIT_I:%.*]] = insertelement <8 x i8> poison, i8 [[X]], i64 0
|
|
// RV64-NEXT: [[VECINIT7_I:%.*]] = shufflevector <8 x i8> [[VECINIT_I]], <8 x i8> poison, <8 x i32> zeroinitializer
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast <8 x i8> [[VECINIT7_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP0]]
|
|
//
|
|
uint8x8_t test_pmv_s_u8x8(uint8_t x) {
|
|
return __riscv_pmv_s_u8x8(x);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pmv_s_i8x8(
|
|
// RV32-SAME: i8 noundef signext [[X:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[VECINIT_I:%.*]] = insertelement <8 x i8> poison, i8 [[X]], i64 0
|
|
// RV32-NEXT: [[VECINIT7_I:%.*]] = shufflevector <8 x i8> [[VECINIT_I]], <8 x i8> poison, <8 x i32> zeroinitializer
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast <8 x i8> [[VECINIT7_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP0]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pmv_s_i8x8(
|
|
// RV64-SAME: i8 noundef signext [[X:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[VECINIT_I:%.*]] = insertelement <8 x i8> poison, i8 [[X]], i64 0
|
|
// RV64-NEXT: [[VECINIT7_I:%.*]] = shufflevector <8 x i8> [[VECINIT_I]], <8 x i8> poison, <8 x i32> zeroinitializer
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast <8 x i8> [[VECINIT7_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP0]]
|
|
//
|
|
int8x8_t test_pmv_s_i8x8(int8_t x) {
|
|
return __riscv_pmv_s_i8x8(x);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pmv_s_u16x4(
|
|
// RV32-SAME: i16 noundef zeroext [[X:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x i16> poison, i16 [[X]], i64 0
|
|
// RV32-NEXT: [[VECINIT3_I:%.*]] = shufflevector <4 x i16> [[VECINIT_I]], <4 x i16> poison, <4 x i32> zeroinitializer
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[VECINIT3_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP0]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pmv_s_u16x4(
|
|
// RV64-SAME: i16 noundef zeroext [[X:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x i16> poison, i16 [[X]], i64 0
|
|
// RV64-NEXT: [[VECINIT3_I:%.*]] = shufflevector <4 x i16> [[VECINIT_I]], <4 x i16> poison, <4 x i32> zeroinitializer
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[VECINIT3_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP0]]
|
|
//
|
|
uint16x4_t test_pmv_s_u16x4(uint16_t x) {
|
|
return __riscv_pmv_s_u16x4(x);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pmv_s_i16x4(
|
|
// RV32-SAME: i16 noundef signext [[X:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x i16> poison, i16 [[X]], i64 0
|
|
// RV32-NEXT: [[VECINIT3_I:%.*]] = shufflevector <4 x i16> [[VECINIT_I]], <4 x i16> poison, <4 x i32> zeroinitializer
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[VECINIT3_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP0]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pmv_s_i16x4(
|
|
// RV64-SAME: i16 noundef signext [[X:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x i16> poison, i16 [[X]], i64 0
|
|
// RV64-NEXT: [[VECINIT3_I:%.*]] = shufflevector <4 x i16> [[VECINIT_I]], <4 x i16> poison, <4 x i32> zeroinitializer
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[VECINIT3_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP0]]
|
|
//
|
|
int16x4_t test_pmv_s_i16x4(int16_t x) {
|
|
return __riscv_pmv_s_i16x4(x);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pmv_s_u32x2(
|
|
// RV32-SAME: i32 noundef [[X:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[VECINIT_I:%.*]] = insertelement <2 x i32> poison, i32 [[X]], i64 0
|
|
// RV32-NEXT: [[VECINIT1_I:%.*]] = shufflevector <2 x i32> [[VECINIT_I]], <2 x i32> poison, <2 x i32> zeroinitializer
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[VECINIT1_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP0]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pmv_s_u32x2(
|
|
// RV64-SAME: i32 noundef signext [[X:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[VECINIT_I:%.*]] = insertelement <2 x i32> poison, i32 [[X]], i64 0
|
|
// RV64-NEXT: [[VECINIT1_I:%.*]] = shufflevector <2 x i32> [[VECINIT_I]], <2 x i32> poison, <2 x i32> zeroinitializer
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[VECINIT1_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP0]]
|
|
//
|
|
uint32x2_t test_pmv_s_u32x2(uint32_t x) {
|
|
return __riscv_pmv_s_u32x2(x);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pmv_s_i32x2(
|
|
// RV32-SAME: i32 noundef [[X:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[VECINIT_I:%.*]] = insertelement <2 x i32> poison, i32 [[X]], i64 0
|
|
// RV32-NEXT: [[VECINIT1_I:%.*]] = shufflevector <2 x i32> [[VECINIT_I]], <2 x i32> poison, <2 x i32> zeroinitializer
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[VECINIT1_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP0]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pmv_s_i32x2(
|
|
// RV64-SAME: i32 noundef signext [[X:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[VECINIT_I:%.*]] = insertelement <2 x i32> poison, i32 [[X]], i64 0
|
|
// RV64-NEXT: [[VECINIT1_I:%.*]] = shufflevector <2 x i32> [[VECINIT_I]], <2 x i32> poison, <2 x i32> zeroinitializer
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[VECINIT1_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP0]]
|
|
//
|
|
int32x2_t test_pmv_s_i32x2(int32_t x) {
|
|
return __riscv_pmv_s_i32x2(x);
|
|
}
|
|
|
|
/* Packed Addition and Subtraction (32-bit) */
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_padd_i8x4(
|
|
// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
|
|
// RV32-NEXT: [[ADD_I:%.*]] = add <4 x i8> [[TMP0]], [[TMP1]]
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[ADD_I]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_padd_i8x4(
|
|
// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
|
|
// RV64-NEXT: [[ADD_I:%.*]] = add <4 x i8> [[TMP0]], [[TMP1]]
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[ADD_I]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
int8x4_t test_padd_i8x4(int8x4_t a, int8x4_t b) {
|
|
return __riscv_padd_i8x4(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_padd_u8x4(
|
|
// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
|
|
// RV32-NEXT: [[ADD_I:%.*]] = add <4 x i8> [[TMP0]], [[TMP1]]
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[ADD_I]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_padd_u8x4(
|
|
// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
|
|
// RV64-NEXT: [[ADD_I:%.*]] = add <4 x i8> [[TMP0]], [[TMP1]]
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[ADD_I]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
uint8x4_t test_padd_u8x4(uint8x4_t a, uint8x4_t b) {
|
|
return __riscv_padd_u8x4(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_padd_i16x2(
|
|
// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
|
|
// RV32-NEXT: [[ADD_I:%.*]] = add <2 x i16> [[TMP0]], [[TMP1]]
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[ADD_I]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_padd_i16x2(
|
|
// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
|
|
// RV64-NEXT: [[ADD_I:%.*]] = add <2 x i16> [[TMP0]], [[TMP1]]
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[ADD_I]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
int16x2_t test_padd_i16x2(int16x2_t a, int16x2_t b) {
|
|
return __riscv_padd_i16x2(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_padd_u16x2(
|
|
// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
|
|
// RV32-NEXT: [[ADD_I:%.*]] = add <2 x i16> [[TMP0]], [[TMP1]]
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[ADD_I]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_padd_u16x2(
|
|
// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
|
|
// RV64-NEXT: [[ADD_I:%.*]] = add <2 x i16> [[TMP0]], [[TMP1]]
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[ADD_I]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
uint16x2_t test_padd_u16x2(uint16x2_t a, uint16x2_t b) {
|
|
return __riscv_padd_u16x2(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_psub_i8x4(
|
|
// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
|
|
// RV32-NEXT: [[SUB_I:%.*]] = sub <4 x i8> [[TMP0]], [[TMP1]]
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SUB_I]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_psub_i8x4(
|
|
// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
|
|
// RV64-NEXT: [[SUB_I:%.*]] = sub <4 x i8> [[TMP0]], [[TMP1]]
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SUB_I]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
int8x4_t test_psub_i8x4(int8x4_t a, int8x4_t b) {
|
|
return __riscv_psub_i8x4(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_psub_u8x4(
|
|
// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
|
|
// RV32-NEXT: [[SUB_I:%.*]] = sub <4 x i8> [[TMP0]], [[TMP1]]
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SUB_I]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_psub_u8x4(
|
|
// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
|
|
// RV64-NEXT: [[SUB_I:%.*]] = sub <4 x i8> [[TMP0]], [[TMP1]]
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SUB_I]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
uint8x4_t test_psub_u8x4(uint8x4_t a, uint8x4_t b) {
|
|
return __riscv_psub_u8x4(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_psub_i16x2(
|
|
// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
|
|
// RV32-NEXT: [[SUB_I:%.*]] = sub <2 x i16> [[TMP0]], [[TMP1]]
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[SUB_I]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_psub_i16x2(
|
|
// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
|
|
// RV64-NEXT: [[SUB_I:%.*]] = sub <2 x i16> [[TMP0]], [[TMP1]]
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[SUB_I]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
int16x2_t test_psub_i16x2(int16x2_t a, int16x2_t b) {
|
|
return __riscv_psub_i16x2(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_psub_u16x2(
|
|
// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
|
|
// RV32-NEXT: [[SUB_I:%.*]] = sub <2 x i16> [[TMP0]], [[TMP1]]
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[SUB_I]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_psub_u16x2(
|
|
// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
|
|
// RV64-NEXT: [[SUB_I:%.*]] = sub <2 x i16> [[TMP0]], [[TMP1]]
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[SUB_I]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
uint16x2_t test_psub_u16x2(uint16x2_t a, uint16x2_t b) {
|
|
return __riscv_psub_u16x2(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_pneg_i8x4(
|
|
// RV32-SAME: i32 noundef [[A_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
|
|
// RV32-NEXT: [[SUB_I:%.*]] = sub <4 x i8> zeroinitializer, [[TMP0]]
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast <4 x i8> [[SUB_I]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP1]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_pneg_i8x4(
|
|
// RV64-SAME: i32 noundef [[A_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
|
|
// RV64-NEXT: [[SUB_I:%.*]] = sub <4 x i8> zeroinitializer, [[TMP0]]
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast <4 x i8> [[SUB_I]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP1]]
|
|
//
|
|
int8x4_t test_pneg_i8x4(int8x4_t a) {
|
|
return __riscv_pneg_i8x4(a);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_pneg_i16x2(
|
|
// RV32-SAME: i32 noundef [[A_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
|
|
// RV32-NEXT: [[SUB_I:%.*]] = sub <2 x i16> zeroinitializer, [[TMP0]]
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast <2 x i16> [[SUB_I]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP1]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_pneg_i16x2(
|
|
// RV64-SAME: i32 noundef [[A_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
|
|
// RV64-NEXT: [[SUB_I:%.*]] = sub <2 x i16> zeroinitializer, [[TMP0]]
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast <2 x i16> [[SUB_I]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP1]]
|
|
//
|
|
int16x2_t test_pneg_i16x2(int16x2_t a) {
|
|
return __riscv_pneg_i16x2(a);
|
|
}
|
|
|
|
/* Packed Addition and Subtraction (64-bit) */
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_padd_i8x8(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
|
|
// RV32-NEXT: [[ADD_I:%.*]] = add <8 x i8> [[TMP0]], [[TMP1]]
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[ADD_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_padd_i8x8(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
|
|
// RV64-NEXT: [[ADD_I:%.*]] = add <8 x i8> [[TMP0]], [[TMP1]]
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[ADD_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
int8x8_t test_padd_i8x8(int8x8_t a, int8x8_t b) {
|
|
return __riscv_padd_i8x8(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_padd_u8x8(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
|
|
// RV32-NEXT: [[ADD_I:%.*]] = add <8 x i8> [[TMP0]], [[TMP1]]
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[ADD_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_padd_u8x8(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
|
|
// RV64-NEXT: [[ADD_I:%.*]] = add <8 x i8> [[TMP0]], [[TMP1]]
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[ADD_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
uint8x8_t test_padd_u8x8(uint8x8_t a, uint8x8_t b) {
|
|
return __riscv_padd_u8x8(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_padd_i16x4(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[ADD_I:%.*]] = add <4 x i16> [[TMP0]], [[TMP1]]
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[ADD_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_padd_i16x4(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[ADD_I:%.*]] = add <4 x i16> [[TMP0]], [[TMP1]]
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[ADD_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
int16x4_t test_padd_i16x4(int16x4_t a, int16x4_t b) {
|
|
return __riscv_padd_i16x4(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_padd_u16x4(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[ADD_I:%.*]] = add <4 x i16> [[TMP0]], [[TMP1]]
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[ADD_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_padd_u16x4(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[ADD_I:%.*]] = add <4 x i16> [[TMP0]], [[TMP1]]
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[ADD_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
uint16x4_t test_padd_u16x4(uint16x4_t a, uint16x4_t b) {
|
|
return __riscv_padd_u16x4(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_padd_i32x2(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
|
|
// RV32-NEXT: [[ADD_I:%.*]] = add <2 x i32> [[TMP0]], [[TMP1]]
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[ADD_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_padd_i32x2(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
|
|
// RV64-NEXT: [[ADD_I:%.*]] = add <2 x i32> [[TMP0]], [[TMP1]]
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[ADD_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
int32x2_t test_padd_i32x2(int32x2_t a, int32x2_t b) {
|
|
return __riscv_padd_i32x2(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_padd_u32x2(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
|
|
// RV32-NEXT: [[ADD_I:%.*]] = add <2 x i32> [[TMP0]], [[TMP1]]
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[ADD_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_padd_u32x2(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
|
|
// RV64-NEXT: [[ADD_I:%.*]] = add <2 x i32> [[TMP0]], [[TMP1]]
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[ADD_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
uint32x2_t test_padd_u32x2(uint32x2_t a, uint32x2_t b) {
|
|
return __riscv_padd_u32x2(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_psub_i8x8(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
|
|
// RV32-NEXT: [[SUB_I:%.*]] = sub <8 x i8> [[TMP0]], [[TMP1]]
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SUB_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_psub_i8x8(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
|
|
// RV64-NEXT: [[SUB_I:%.*]] = sub <8 x i8> [[TMP0]], [[TMP1]]
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SUB_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
int8x8_t test_psub_i8x8(int8x8_t a, int8x8_t b) {
|
|
return __riscv_psub_i8x8(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_psub_u8x8(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
|
|
// RV32-NEXT: [[SUB_I:%.*]] = sub <8 x i8> [[TMP0]], [[TMP1]]
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SUB_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_psub_u8x8(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
|
|
// RV64-NEXT: [[SUB_I:%.*]] = sub <8 x i8> [[TMP0]], [[TMP1]]
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SUB_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
uint8x8_t test_psub_u8x8(uint8x8_t a, uint8x8_t b) {
|
|
return __riscv_psub_u8x8(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_psub_i16x4(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[SUB_I:%.*]] = sub <4 x i16> [[TMP0]], [[TMP1]]
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SUB_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_psub_i16x4(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[SUB_I:%.*]] = sub <4 x i16> [[TMP0]], [[TMP1]]
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SUB_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
int16x4_t test_psub_i16x4(int16x4_t a, int16x4_t b) {
|
|
return __riscv_psub_i16x4(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_psub_u16x4(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[SUB_I:%.*]] = sub <4 x i16> [[TMP0]], [[TMP1]]
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SUB_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_psub_u16x4(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[SUB_I:%.*]] = sub <4 x i16> [[TMP0]], [[TMP1]]
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SUB_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
uint16x4_t test_psub_u16x4(uint16x4_t a, uint16x4_t b) {
|
|
return __riscv_psub_u16x4(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_psub_i32x2(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
|
|
// RV32-NEXT: [[SUB_I:%.*]] = sub <2 x i32> [[TMP0]], [[TMP1]]
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[SUB_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_psub_i32x2(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
|
|
// RV64-NEXT: [[SUB_I:%.*]] = sub <2 x i32> [[TMP0]], [[TMP1]]
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[SUB_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
int32x2_t test_psub_i32x2(int32x2_t a, int32x2_t b) {
|
|
return __riscv_psub_i32x2(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_psub_u32x2(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
|
|
// RV32-NEXT: [[SUB_I:%.*]] = sub <2 x i32> [[TMP0]], [[TMP1]]
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[SUB_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_psub_u32x2(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
|
|
// RV64-NEXT: [[SUB_I:%.*]] = sub <2 x i32> [[TMP0]], [[TMP1]]
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[SUB_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
uint32x2_t test_psub_u32x2(uint32x2_t a, uint32x2_t b) {
|
|
return __riscv_psub_u32x2(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pneg_i8x8(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
|
|
// RV32-NEXT: [[SUB_I:%.*]] = sub <8 x i8> zeroinitializer, [[TMP0]]
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[SUB_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP1]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pneg_i8x8(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
|
|
// RV64-NEXT: [[SUB_I:%.*]] = sub <8 x i8> zeroinitializer, [[TMP0]]
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[SUB_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP1]]
|
|
//
|
|
int8x8_t test_pneg_i8x8(int8x8_t a) {
|
|
return __riscv_pneg_i8x8(a);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pneg_i16x4(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[SUB_I:%.*]] = sub <4 x i16> zeroinitializer, [[TMP0]]
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[SUB_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP1]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pneg_i16x4(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[SUB_I:%.*]] = sub <4 x i16> zeroinitializer, [[TMP0]]
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[SUB_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP1]]
|
|
//
|
|
int16x4_t test_pneg_i16x4(int16x4_t a) {
|
|
return __riscv_pneg_i16x4(a);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pneg_i32x2(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
|
|
// RV32-NEXT: [[SUB_I:%.*]] = sub <2 x i32> zeroinitializer, [[TMP0]]
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[SUB_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP1]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pneg_i32x2(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
|
|
// RV64-NEXT: [[SUB_I:%.*]] = sub <2 x i32> zeroinitializer, [[TMP0]]
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[SUB_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP1]]
|
|
//
|
|
int32x2_t test_pneg_i32x2(int32x2_t a) {
|
|
return __riscv_pneg_i32x2(a);
|
|
}
|
|
|
|
/* Packed Addition with Scalar (32-bit) */
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_padd_s_u8x4(
|
|
// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i8 noundef zeroext [[B:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
|
|
// RV32-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x i8> poison, i8 [[B]], i64 0
|
|
// RV32-NEXT: [[VECINIT4_I:%.*]] = shufflevector <4 x i8> [[VECINIT_I]], <4 x i8> poison, <4 x i32> zeroinitializer
|
|
// RV32-NEXT: [[ADD_I:%.*]] = add <4 x i8> [[VECINIT4_I]], [[TMP0]]
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast <4 x i8> [[ADD_I]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP1]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_padd_s_u8x4(
|
|
// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i8 noundef zeroext [[B:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
|
|
// RV64-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x i8> poison, i8 [[B]], i64 0
|
|
// RV64-NEXT: [[VECINIT4_I:%.*]] = shufflevector <4 x i8> [[VECINIT_I]], <4 x i8> poison, <4 x i32> zeroinitializer
|
|
// RV64-NEXT: [[ADD_I:%.*]] = add <4 x i8> [[VECINIT4_I]], [[TMP0]]
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast <4 x i8> [[ADD_I]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP1]]
|
|
//
|
|
uint8x4_t test_padd_s_u8x4(uint8x4_t a, uint8_t b) {
|
|
return __riscv_padd_s_u8x4(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_padd_s_i8x4(
|
|
// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i8 noundef signext [[B:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
|
|
// RV32-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x i8> poison, i8 [[B]], i64 0
|
|
// RV32-NEXT: [[VECINIT4_I:%.*]] = shufflevector <4 x i8> [[VECINIT_I]], <4 x i8> poison, <4 x i32> zeroinitializer
|
|
// RV32-NEXT: [[ADD_I:%.*]] = add <4 x i8> [[VECINIT4_I]], [[TMP0]]
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast <4 x i8> [[ADD_I]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP1]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_padd_s_i8x4(
|
|
// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i8 noundef signext [[B:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
|
|
// RV64-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x i8> poison, i8 [[B]], i64 0
|
|
// RV64-NEXT: [[VECINIT4_I:%.*]] = shufflevector <4 x i8> [[VECINIT_I]], <4 x i8> poison, <4 x i32> zeroinitializer
|
|
// RV64-NEXT: [[ADD_I:%.*]] = add <4 x i8> [[VECINIT4_I]], [[TMP0]]
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast <4 x i8> [[ADD_I]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP1]]
|
|
//
|
|
int8x4_t test_padd_s_i8x4(int8x4_t a, int8_t b) {
|
|
return __riscv_padd_s_i8x4(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_padd_s_u16x2(
|
|
// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i16 noundef zeroext [[B:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
|
|
// RV32-NEXT: [[VECINIT_I:%.*]] = insertelement <2 x i16> poison, i16 [[B]], i64 0
|
|
// RV32-NEXT: [[VECINIT2_I:%.*]] = shufflevector <2 x i16> [[VECINIT_I]], <2 x i16> poison, <2 x i32> zeroinitializer
|
|
// RV32-NEXT: [[ADD_I:%.*]] = add <2 x i16> [[VECINIT2_I]], [[TMP0]]
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast <2 x i16> [[ADD_I]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP1]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_padd_s_u16x2(
|
|
// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i16 noundef zeroext [[B:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
|
|
// RV64-NEXT: [[VECINIT_I:%.*]] = insertelement <2 x i16> poison, i16 [[B]], i64 0
|
|
// RV64-NEXT: [[VECINIT2_I:%.*]] = shufflevector <2 x i16> [[VECINIT_I]], <2 x i16> poison, <2 x i32> zeroinitializer
|
|
// RV64-NEXT: [[ADD_I:%.*]] = add <2 x i16> [[VECINIT2_I]], [[TMP0]]
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast <2 x i16> [[ADD_I]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP1]]
|
|
//
|
|
uint16x2_t test_padd_s_u16x2(uint16x2_t a, uint16_t b) {
|
|
return __riscv_padd_s_u16x2(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_padd_s_i16x2(
|
|
// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i16 noundef signext [[B:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
|
|
// RV32-NEXT: [[VECINIT_I:%.*]] = insertelement <2 x i16> poison, i16 [[B]], i64 0
|
|
// RV32-NEXT: [[VECINIT2_I:%.*]] = shufflevector <2 x i16> [[VECINIT_I]], <2 x i16> poison, <2 x i32> zeroinitializer
|
|
// RV32-NEXT: [[ADD_I:%.*]] = add <2 x i16> [[VECINIT2_I]], [[TMP0]]
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast <2 x i16> [[ADD_I]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP1]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_padd_s_i16x2(
|
|
// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i16 noundef signext [[B:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
|
|
// RV64-NEXT: [[VECINIT_I:%.*]] = insertelement <2 x i16> poison, i16 [[B]], i64 0
|
|
// RV64-NEXT: [[VECINIT2_I:%.*]] = shufflevector <2 x i16> [[VECINIT_I]], <2 x i16> poison, <2 x i32> zeroinitializer
|
|
// RV64-NEXT: [[ADD_I:%.*]] = add <2 x i16> [[VECINIT2_I]], [[TMP0]]
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast <2 x i16> [[ADD_I]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP1]]
|
|
//
|
|
int16x2_t test_padd_s_i16x2(int16x2_t a, int16_t b) {
|
|
return __riscv_padd_s_i16x2(a, b);
|
|
}
|
|
|
|
/* Packed Addition with Scalar (64-bit) */
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_padd_s_u8x8(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i8 noundef zeroext [[B:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
|
|
// RV32-NEXT: [[VECINIT_I:%.*]] = insertelement <8 x i8> poison, i8 [[B]], i64 0
|
|
// RV32-NEXT: [[VECINIT8_I:%.*]] = shufflevector <8 x i8> [[VECINIT_I]], <8 x i8> poison, <8 x i32> zeroinitializer
|
|
// RV32-NEXT: [[ADD_I:%.*]] = add <8 x i8> [[VECINIT8_I]], [[TMP0]]
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[ADD_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP1]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_padd_s_u8x8(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i8 noundef zeroext [[B:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
|
|
// RV64-NEXT: [[VECINIT_I:%.*]] = insertelement <8 x i8> poison, i8 [[B]], i64 0
|
|
// RV64-NEXT: [[VECINIT8_I:%.*]] = shufflevector <8 x i8> [[VECINIT_I]], <8 x i8> poison, <8 x i32> zeroinitializer
|
|
// RV64-NEXT: [[ADD_I:%.*]] = add <8 x i8> [[VECINIT8_I]], [[TMP0]]
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[ADD_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP1]]
|
|
//
|
|
uint8x8_t test_padd_s_u8x8(uint8x8_t a, uint8_t b) {
|
|
return __riscv_padd_s_u8x8(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_padd_s_i8x8(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i8 noundef signext [[B:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
|
|
// RV32-NEXT: [[VECINIT_I:%.*]] = insertelement <8 x i8> poison, i8 [[B]], i64 0
|
|
// RV32-NEXT: [[VECINIT8_I:%.*]] = shufflevector <8 x i8> [[VECINIT_I]], <8 x i8> poison, <8 x i32> zeroinitializer
|
|
// RV32-NEXT: [[ADD_I:%.*]] = add <8 x i8> [[VECINIT8_I]], [[TMP0]]
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[ADD_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP1]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_padd_s_i8x8(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i8 noundef signext [[B:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
|
|
// RV64-NEXT: [[VECINIT_I:%.*]] = insertelement <8 x i8> poison, i8 [[B]], i64 0
|
|
// RV64-NEXT: [[VECINIT8_I:%.*]] = shufflevector <8 x i8> [[VECINIT_I]], <8 x i8> poison, <8 x i32> zeroinitializer
|
|
// RV64-NEXT: [[ADD_I:%.*]] = add <8 x i8> [[VECINIT8_I]], [[TMP0]]
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[ADD_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP1]]
|
|
//
|
|
int8x8_t test_padd_s_i8x8(int8x8_t a, int8_t b) {
|
|
return __riscv_padd_s_i8x8(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_padd_s_u16x4(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i16 noundef zeroext [[B:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x i16> poison, i16 [[B]], i64 0
|
|
// RV32-NEXT: [[VECINIT4_I:%.*]] = shufflevector <4 x i16> [[VECINIT_I]], <4 x i16> poison, <4 x i32> zeroinitializer
|
|
// RV32-NEXT: [[ADD_I:%.*]] = add <4 x i16> [[VECINIT4_I]], [[TMP0]]
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[ADD_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP1]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_padd_s_u16x4(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i16 noundef zeroext [[B:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x i16> poison, i16 [[B]], i64 0
|
|
// RV64-NEXT: [[VECINIT4_I:%.*]] = shufflevector <4 x i16> [[VECINIT_I]], <4 x i16> poison, <4 x i32> zeroinitializer
|
|
// RV64-NEXT: [[ADD_I:%.*]] = add <4 x i16> [[VECINIT4_I]], [[TMP0]]
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[ADD_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP1]]
|
|
//
|
|
uint16x4_t test_padd_s_u16x4(uint16x4_t a, uint16_t b) {
|
|
return __riscv_padd_s_u16x4(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_padd_s_i16x4(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i16 noundef signext [[B:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x i16> poison, i16 [[B]], i64 0
|
|
// RV32-NEXT: [[VECINIT4_I:%.*]] = shufflevector <4 x i16> [[VECINIT_I]], <4 x i16> poison, <4 x i32> zeroinitializer
|
|
// RV32-NEXT: [[ADD_I:%.*]] = add <4 x i16> [[VECINIT4_I]], [[TMP0]]
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[ADD_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP1]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_padd_s_i16x4(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i16 noundef signext [[B:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x i16> poison, i16 [[B]], i64 0
|
|
// RV64-NEXT: [[VECINIT4_I:%.*]] = shufflevector <4 x i16> [[VECINIT_I]], <4 x i16> poison, <4 x i32> zeroinitializer
|
|
// RV64-NEXT: [[ADD_I:%.*]] = add <4 x i16> [[VECINIT4_I]], [[TMP0]]
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[ADD_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP1]]
|
|
//
|
|
int16x4_t test_padd_s_i16x4(int16x4_t a, int16_t b) {
|
|
return __riscv_padd_s_i16x4(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_padd_s_u32x2(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i32 noundef [[B:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
|
|
// RV32-NEXT: [[VECINIT_I:%.*]] = insertelement <2 x i32> poison, i32 [[B]], i64 0
|
|
// RV32-NEXT: [[VECINIT2_I:%.*]] = shufflevector <2 x i32> [[VECINIT_I]], <2 x i32> poison, <2 x i32> zeroinitializer
|
|
// RV32-NEXT: [[ADD_I:%.*]] = add <2 x i32> [[VECINIT2_I]], [[TMP0]]
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[ADD_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP1]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_padd_s_u32x2(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i32 noundef signext [[B:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
|
|
// RV64-NEXT: [[VECINIT_I:%.*]] = insertelement <2 x i32> poison, i32 [[B]], i64 0
|
|
// RV64-NEXT: [[VECINIT2_I:%.*]] = shufflevector <2 x i32> [[VECINIT_I]], <2 x i32> poison, <2 x i32> zeroinitializer
|
|
// RV64-NEXT: [[ADD_I:%.*]] = add <2 x i32> [[VECINIT2_I]], [[TMP0]]
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[ADD_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP1]]
|
|
//
|
|
uint32x2_t test_padd_s_u32x2(uint32x2_t a, uint32_t b) {
|
|
return __riscv_padd_s_u32x2(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_padd_s_i32x2(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i32 noundef [[B:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
|
|
// RV32-NEXT: [[VECINIT_I:%.*]] = insertelement <2 x i32> poison, i32 [[B]], i64 0
|
|
// RV32-NEXT: [[VECINIT2_I:%.*]] = shufflevector <2 x i32> [[VECINIT_I]], <2 x i32> poison, <2 x i32> zeroinitializer
|
|
// RV32-NEXT: [[ADD_I:%.*]] = add <2 x i32> [[VECINIT2_I]], [[TMP0]]
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[ADD_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP1]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_padd_s_i32x2(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i32 noundef signext [[B:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
|
|
// RV64-NEXT: [[VECINIT_I:%.*]] = insertelement <2 x i32> poison, i32 [[B]], i64 0
|
|
// RV64-NEXT: [[VECINIT2_I:%.*]] = shufflevector <2 x i32> [[VECINIT_I]], <2 x i32> poison, <2 x i32> zeroinitializer
|
|
// RV64-NEXT: [[ADD_I:%.*]] = add <2 x i32> [[VECINIT2_I]], [[TMP0]]
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[ADD_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP1]]
|
|
//
|
|
int32x2_t test_padd_s_i32x2(int32x2_t a, int32_t b) {
|
|
return __riscv_padd_s_i32x2(a, b);
|
|
}
|
|
|
|
/* Packed Saturating Addition and Subtraction (32-bit) */
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_psadd_i8x4(
|
|
// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
|
|
// RV32-NEXT: [[ELT_SAT_I:%.*]] = call <4 x i8> @llvm.sadd.sat.v4i8(<4 x i8> [[TMP0]], <4 x i8> [[TMP1]])
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[ELT_SAT_I]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_psadd_i8x4(
|
|
// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
|
|
// RV64-NEXT: [[ELT_SAT_I:%.*]] = call <4 x i8> @llvm.sadd.sat.v4i8(<4 x i8> [[TMP0]], <4 x i8> [[TMP1]])
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[ELT_SAT_I]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
int8x4_t test_psadd_i8x4(int8x4_t a, int8x4_t b) {
|
|
return __riscv_psadd_i8x4(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_psadd_i16x2(
|
|
// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
|
|
// RV32-NEXT: [[ELT_SAT_I:%.*]] = call <2 x i16> @llvm.sadd.sat.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[ELT_SAT_I]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_psadd_i16x2(
|
|
// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
|
|
// RV64-NEXT: [[ELT_SAT_I:%.*]] = call <2 x i16> @llvm.sadd.sat.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[ELT_SAT_I]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
int16x2_t test_psadd_i16x2(int16x2_t a, int16x2_t b) {
|
|
return __riscv_psadd_i16x2(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_psaddu_u8x4(
|
|
// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
|
|
// RV32-NEXT: [[ELT_SAT_I:%.*]] = call <4 x i8> @llvm.uadd.sat.v4i8(<4 x i8> [[TMP0]], <4 x i8> [[TMP1]])
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[ELT_SAT_I]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_psaddu_u8x4(
|
|
// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
|
|
// RV64-NEXT: [[ELT_SAT_I:%.*]] = call <4 x i8> @llvm.uadd.sat.v4i8(<4 x i8> [[TMP0]], <4 x i8> [[TMP1]])
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[ELT_SAT_I]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
uint8x4_t test_psaddu_u8x4(uint8x4_t a, uint8x4_t b) {
|
|
return __riscv_psaddu_u8x4(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_psaddu_u16x2(
|
|
// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
|
|
// RV32-NEXT: [[ELT_SAT_I:%.*]] = call <2 x i16> @llvm.uadd.sat.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[ELT_SAT_I]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_psaddu_u16x2(
|
|
// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
|
|
// RV64-NEXT: [[ELT_SAT_I:%.*]] = call <2 x i16> @llvm.uadd.sat.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[ELT_SAT_I]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
uint16x2_t test_psaddu_u16x2(uint16x2_t a, uint16x2_t b) {
|
|
return __riscv_psaddu_u16x2(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_pssub_i8x4(
|
|
// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
|
|
// RV32-NEXT: [[ELT_SAT_I:%.*]] = call <4 x i8> @llvm.ssub.sat.v4i8(<4 x i8> [[TMP0]], <4 x i8> [[TMP1]])
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[ELT_SAT_I]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_pssub_i8x4(
|
|
// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
|
|
// RV64-NEXT: [[ELT_SAT_I:%.*]] = call <4 x i8> @llvm.ssub.sat.v4i8(<4 x i8> [[TMP0]], <4 x i8> [[TMP1]])
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[ELT_SAT_I]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
int8x4_t test_pssub_i8x4(int8x4_t a, int8x4_t b) {
|
|
return __riscv_pssub_i8x4(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_pssub_i16x2(
|
|
// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
|
|
// RV32-NEXT: [[ELT_SAT_I:%.*]] = call <2 x i16> @llvm.ssub.sat.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[ELT_SAT_I]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_pssub_i16x2(
|
|
// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
|
|
// RV64-NEXT: [[ELT_SAT_I:%.*]] = call <2 x i16> @llvm.ssub.sat.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[ELT_SAT_I]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
int16x2_t test_pssub_i16x2(int16x2_t a, int16x2_t b) {
|
|
return __riscv_pssub_i16x2(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_pssubu_u8x4(
|
|
// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
|
|
// RV32-NEXT: [[ELT_SAT_I:%.*]] = call <4 x i8> @llvm.usub.sat.v4i8(<4 x i8> [[TMP0]], <4 x i8> [[TMP1]])
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[ELT_SAT_I]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_pssubu_u8x4(
|
|
// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
|
|
// RV64-NEXT: [[ELT_SAT_I:%.*]] = call <4 x i8> @llvm.usub.sat.v4i8(<4 x i8> [[TMP0]], <4 x i8> [[TMP1]])
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[ELT_SAT_I]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
uint8x4_t test_pssubu_u8x4(uint8x4_t a, uint8x4_t b) {
|
|
return __riscv_pssubu_u8x4(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_pssubu_u16x2(
|
|
// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
|
|
// RV32-NEXT: [[ELT_SAT_I:%.*]] = call <2 x i16> @llvm.usub.sat.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[ELT_SAT_I]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_pssubu_u16x2(
|
|
// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
|
|
// RV64-NEXT: [[ELT_SAT_I:%.*]] = call <2 x i16> @llvm.usub.sat.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[ELT_SAT_I]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
uint16x2_t test_pssubu_u16x2(uint16x2_t a, uint16x2_t b) {
|
|
return __riscv_pssubu_u16x2(a, b);
|
|
}
|
|
|
|
/* Packed Saturating Addition and Subtraction (64-bit) */
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_psadd_i8x8(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
|
|
// RV32-NEXT: [[ELT_SAT_I:%.*]] = call <8 x i8> @llvm.sadd.sat.v8i8(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]])
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[ELT_SAT_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_psadd_i8x8(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
|
|
// RV64-NEXT: [[ELT_SAT_I:%.*]] = call <8 x i8> @llvm.sadd.sat.v8i8(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]])
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[ELT_SAT_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
int8x8_t test_psadd_i8x8(int8x8_t a, int8x8_t b) {
|
|
return __riscv_psadd_i8x8(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_psadd_i16x4(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[ELT_SAT_I:%.*]] = call <4 x i16> @llvm.sadd.sat.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[ELT_SAT_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_psadd_i16x4(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[ELT_SAT_I:%.*]] = call <4 x i16> @llvm.sadd.sat.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[ELT_SAT_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
int16x4_t test_psadd_i16x4(int16x4_t a, int16x4_t b) {
|
|
return __riscv_psadd_i16x4(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_psadd_i32x2(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
|
|
// RV32-NEXT: [[ELT_SAT_I:%.*]] = call <2 x i32> @llvm.sadd.sat.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[ELT_SAT_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_psadd_i32x2(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
|
|
// RV64-NEXT: [[ELT_SAT_I:%.*]] = call <2 x i32> @llvm.sadd.sat.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[ELT_SAT_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
int32x2_t test_psadd_i32x2(int32x2_t a, int32x2_t b) {
|
|
return __riscv_psadd_i32x2(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_psaddu_u8x8(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
|
|
// RV32-NEXT: [[ELT_SAT_I:%.*]] = call <8 x i8> @llvm.uadd.sat.v8i8(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]])
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[ELT_SAT_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_psaddu_u8x8(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
|
|
// RV64-NEXT: [[ELT_SAT_I:%.*]] = call <8 x i8> @llvm.uadd.sat.v8i8(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]])
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[ELT_SAT_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
uint8x8_t test_psaddu_u8x8(uint8x8_t a, uint8x8_t b) {
|
|
return __riscv_psaddu_u8x8(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_psaddu_u16x4(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[ELT_SAT_I:%.*]] = call <4 x i16> @llvm.uadd.sat.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[ELT_SAT_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_psaddu_u16x4(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[ELT_SAT_I:%.*]] = call <4 x i16> @llvm.uadd.sat.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[ELT_SAT_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
uint16x4_t test_psaddu_u16x4(uint16x4_t a, uint16x4_t b) {
|
|
return __riscv_psaddu_u16x4(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_psaddu_u32x2(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
|
|
// RV32-NEXT: [[ELT_SAT_I:%.*]] = call <2 x i32> @llvm.uadd.sat.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[ELT_SAT_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_psaddu_u32x2(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
|
|
// RV64-NEXT: [[ELT_SAT_I:%.*]] = call <2 x i32> @llvm.uadd.sat.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[ELT_SAT_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
uint32x2_t test_psaddu_u32x2(uint32x2_t a, uint32x2_t b) {
|
|
return __riscv_psaddu_u32x2(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pssub_i8x8(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
|
|
// RV32-NEXT: [[ELT_SAT_I:%.*]] = call <8 x i8> @llvm.ssub.sat.v8i8(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]])
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[ELT_SAT_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pssub_i8x8(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
|
|
// RV64-NEXT: [[ELT_SAT_I:%.*]] = call <8 x i8> @llvm.ssub.sat.v8i8(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]])
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[ELT_SAT_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
int8x8_t test_pssub_i8x8(int8x8_t a, int8x8_t b) {
|
|
return __riscv_pssub_i8x8(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pssub_i16x4(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[ELT_SAT_I:%.*]] = call <4 x i16> @llvm.ssub.sat.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[ELT_SAT_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pssub_i16x4(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[ELT_SAT_I:%.*]] = call <4 x i16> @llvm.ssub.sat.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[ELT_SAT_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
int16x4_t test_pssub_i16x4(int16x4_t a, int16x4_t b) {
|
|
return __riscv_pssub_i16x4(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pssub_i32x2(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
|
|
// RV32-NEXT: [[ELT_SAT_I:%.*]] = call <2 x i32> @llvm.ssub.sat.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[ELT_SAT_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pssub_i32x2(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
|
|
// RV64-NEXT: [[ELT_SAT_I:%.*]] = call <2 x i32> @llvm.ssub.sat.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[ELT_SAT_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
int32x2_t test_pssub_i32x2(int32x2_t a, int32x2_t b) {
|
|
return __riscv_pssub_i32x2(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pssubu_u8x8(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
|
|
// RV32-NEXT: [[ELT_SAT_I:%.*]] = call <8 x i8> @llvm.usub.sat.v8i8(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]])
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[ELT_SAT_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pssubu_u8x8(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
|
|
// RV64-NEXT: [[ELT_SAT_I:%.*]] = call <8 x i8> @llvm.usub.sat.v8i8(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]])
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[ELT_SAT_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
uint8x8_t test_pssubu_u8x8(uint8x8_t a, uint8x8_t b) {
|
|
return __riscv_pssubu_u8x8(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pssubu_u16x4(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[ELT_SAT_I:%.*]] = call <4 x i16> @llvm.usub.sat.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[ELT_SAT_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pssubu_u16x4(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[ELT_SAT_I:%.*]] = call <4 x i16> @llvm.usub.sat.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[ELT_SAT_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
uint16x4_t test_pssubu_u16x4(uint16x4_t a, uint16x4_t b) {
|
|
return __riscv_pssubu_u16x4(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pssubu_u32x2(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
|
|
// RV32-NEXT: [[ELT_SAT_I:%.*]] = call <2 x i32> @llvm.usub.sat.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[ELT_SAT_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pssubu_u32x2(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
|
|
// RV64-NEXT: [[ELT_SAT_I:%.*]] = call <2 x i32> @llvm.usub.sat.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[ELT_SAT_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
uint32x2_t test_pssubu_u32x2(uint32x2_t a, uint32x2_t b) {
|
|
return __riscv_pssubu_u32x2(a, b);
|
|
}
|
|
|
|
/* Packed Shift-Add (32-bit) */
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_psh1add_i16x2(
|
|
// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
|
|
// RV32-NEXT: [[SHL_I:%.*]] = shl <2 x i16> [[TMP0]], splat (i16 1)
|
|
// RV32-NEXT: [[ADD_I:%.*]] = add <2 x i16> [[SHL_I]], [[TMP1]]
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[ADD_I]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_psh1add_i16x2(
|
|
// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
|
|
// RV64-NEXT: [[SHL_I:%.*]] = shl <2 x i16> [[TMP0]], splat (i16 1)
|
|
// RV64-NEXT: [[ADD_I:%.*]] = add <2 x i16> [[SHL_I]], [[TMP1]]
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[ADD_I]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
int16x2_t test_psh1add_i16x2(int16x2_t a, int16x2_t b) {
|
|
return __riscv_psh1add_i16x2(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_psh1add_u16x2(
|
|
// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
|
|
// RV32-NEXT: [[SHL_I:%.*]] = shl <2 x i16> [[TMP0]], splat (i16 1)
|
|
// RV32-NEXT: [[ADD_I:%.*]] = add <2 x i16> [[SHL_I]], [[TMP1]]
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[ADD_I]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_psh1add_u16x2(
|
|
// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
|
|
// RV64-NEXT: [[SHL_I:%.*]] = shl <2 x i16> [[TMP0]], splat (i16 1)
|
|
// RV64-NEXT: [[ADD_I:%.*]] = add <2 x i16> [[SHL_I]], [[TMP1]]
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[ADD_I]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
uint16x2_t test_psh1add_u16x2(uint16x2_t a, uint16x2_t b) {
|
|
return __riscv_psh1add_u16x2(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_pssh1sadd_i16x2(
|
|
// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
|
|
// RV32-NEXT: [[ELT_SAT_I:%.*]] = call <2 x i16> @llvm.sadd.sat.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP0]])
|
|
// RV32-NEXT: [[ELT_SAT3_I:%.*]] = call <2 x i16> @llvm.sadd.sat.v2i16(<2 x i16> [[ELT_SAT_I]], <2 x i16> [[TMP1]])
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[ELT_SAT3_I]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_pssh1sadd_i16x2(
|
|
// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
|
|
// RV64-NEXT: [[ELT_SAT_I:%.*]] = call <2 x i16> @llvm.sadd.sat.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP0]])
|
|
// RV64-NEXT: [[ELT_SAT3_I:%.*]] = call <2 x i16> @llvm.sadd.sat.v2i16(<2 x i16> [[ELT_SAT_I]], <2 x i16> [[TMP1]])
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[ELT_SAT3_I]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
int16x2_t test_pssh1sadd_i16x2(int16x2_t a, int16x2_t b) {
|
|
return __riscv_pssh1sadd_i16x2(a, b);
|
|
}
|
|
|
|
/* Packed Shift-Add (64-bit) */
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_psh1add_i16x4(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[SHL_I:%.*]] = shl <4 x i16> [[TMP0]], splat (i16 1)
|
|
// RV32-NEXT: [[ADD_I:%.*]] = add <4 x i16> [[SHL_I]], [[TMP1]]
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[ADD_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_psh1add_i16x4(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[SHL_I:%.*]] = shl <4 x i16> [[TMP0]], splat (i16 1)
|
|
// RV64-NEXT: [[ADD_I:%.*]] = add <4 x i16> [[SHL_I]], [[TMP1]]
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[ADD_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
int16x4_t test_psh1add_i16x4(int16x4_t a, int16x4_t b) {
|
|
return __riscv_psh1add_i16x4(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_psh1add_u16x4(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[SHL_I:%.*]] = shl <4 x i16> [[TMP0]], splat (i16 1)
|
|
// RV32-NEXT: [[ADD_I:%.*]] = add <4 x i16> [[SHL_I]], [[TMP1]]
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[ADD_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_psh1add_u16x4(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[SHL_I:%.*]] = shl <4 x i16> [[TMP0]], splat (i16 1)
|
|
// RV64-NEXT: [[ADD_I:%.*]] = add <4 x i16> [[SHL_I]], [[TMP1]]
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[ADD_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
uint16x4_t test_psh1add_u16x4(uint16x4_t a, uint16x4_t b) {
|
|
return __riscv_psh1add_u16x4(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_psh1add_i32x2(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
|
|
// RV32-NEXT: [[SHL_I:%.*]] = shl <2 x i32> [[TMP0]], splat (i32 1)
|
|
// RV32-NEXT: [[ADD_I:%.*]] = add <2 x i32> [[SHL_I]], [[TMP1]]
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[ADD_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_psh1add_i32x2(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
|
|
// RV64-NEXT: [[SHL_I:%.*]] = shl <2 x i32> [[TMP0]], splat (i32 1)
|
|
// RV64-NEXT: [[ADD_I:%.*]] = add <2 x i32> [[SHL_I]], [[TMP1]]
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[ADD_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
int32x2_t test_psh1add_i32x2(int32x2_t a, int32x2_t b) {
|
|
return __riscv_psh1add_i32x2(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_psh1add_u32x2(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
|
|
// RV32-NEXT: [[SHL_I:%.*]] = shl <2 x i32> [[TMP0]], splat (i32 1)
|
|
// RV32-NEXT: [[ADD_I:%.*]] = add <2 x i32> [[SHL_I]], [[TMP1]]
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[ADD_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_psh1add_u32x2(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
|
|
// RV64-NEXT: [[SHL_I:%.*]] = shl <2 x i32> [[TMP0]], splat (i32 1)
|
|
// RV64-NEXT: [[ADD_I:%.*]] = add <2 x i32> [[SHL_I]], [[TMP1]]
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[ADD_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
uint32x2_t test_psh1add_u32x2(uint32x2_t a, uint32x2_t b) {
|
|
return __riscv_psh1add_u32x2(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pssh1sadd_i16x4(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[ELT_SAT_I:%.*]] = call <4 x i16> @llvm.sadd.sat.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP0]])
|
|
// RV32-NEXT: [[ELT_SAT3_I:%.*]] = call <4 x i16> @llvm.sadd.sat.v4i16(<4 x i16> [[ELT_SAT_I]], <4 x i16> [[TMP1]])
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[ELT_SAT3_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pssh1sadd_i16x4(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[ELT_SAT_I:%.*]] = call <4 x i16> @llvm.sadd.sat.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP0]])
|
|
// RV64-NEXT: [[ELT_SAT3_I:%.*]] = call <4 x i16> @llvm.sadd.sat.v4i16(<4 x i16> [[ELT_SAT_I]], <4 x i16> [[TMP1]])
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[ELT_SAT3_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
int16x4_t test_pssh1sadd_i16x4(int16x4_t a, int16x4_t b) {
|
|
return __riscv_pssh1sadd_i16x4(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pssh1sadd_i32x2(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
|
|
// RV32-NEXT: [[ELT_SAT_I:%.*]] = call <2 x i32> @llvm.sadd.sat.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP0]])
|
|
// RV32-NEXT: [[ELT_SAT3_I:%.*]] = call <2 x i32> @llvm.sadd.sat.v2i32(<2 x i32> [[ELT_SAT_I]], <2 x i32> [[TMP1]])
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[ELT_SAT3_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pssh1sadd_i32x2(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
|
|
// RV64-NEXT: [[ELT_SAT_I:%.*]] = call <2 x i32> @llvm.sadd.sat.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP0]])
|
|
// RV64-NEXT: [[ELT_SAT3_I:%.*]] = call <2 x i32> @llvm.sadd.sat.v2i32(<2 x i32> [[ELT_SAT_I]], <2 x i32> [[TMP1]])
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[ELT_SAT3_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
int32x2_t test_pssh1sadd_i32x2(int32x2_t a, int32x2_t b) {
|
|
return __riscv_pssh1sadd_i32x2(a, b);
|
|
}
|
|
|
|
/* Packed Exchanged Addition and Subtraction (32-bit) */
|
|
// RV32-LABEL: define dso_local i32 @test_pas_x_i16x2(
|
|
// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
|
|
// RV32-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.pas.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
|
|
// RV32-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP3]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_pas_x_i16x2(
|
|
// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
|
|
// RV64-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.pas.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
|
|
// RV64-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP3]]
|
|
//
|
|
int16x2_t test_pas_x_i16x2(int16x2_t a, int16x2_t b) {
|
|
return __riscv_pas_x_i16x2(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_psa_x_i16x2(
|
|
// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
|
|
// RV32-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.psa.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
|
|
// RV32-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP3]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_psa_x_i16x2(
|
|
// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
|
|
// RV64-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.psa.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
|
|
// RV64-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP3]]
|
|
//
|
|
int16x2_t test_psa_x_i16x2(int16x2_t a, int16x2_t b) {
|
|
return __riscv_psa_x_i16x2(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_psas_x_i16x2(
|
|
// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
|
|
// RV32-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.psas.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
|
|
// RV32-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP3]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_psas_x_i16x2(
|
|
// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
|
|
// RV64-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.psas.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
|
|
// RV64-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP3]]
|
|
//
|
|
int16x2_t test_psas_x_i16x2(int16x2_t a, int16x2_t b) {
|
|
return __riscv_psas_x_i16x2(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_pssa_x_i16x2(
|
|
// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
|
|
// RV32-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.pssa.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
|
|
// RV32-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP3]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_pssa_x_i16x2(
|
|
// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
|
|
// RV64-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.pssa.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
|
|
// RV64-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP3]]
|
|
//
|
|
int16x2_t test_pssa_x_i16x2(int16x2_t a, int16x2_t b) {
|
|
return __riscv_pssa_x_i16x2(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_paas_x_i16x2(
|
|
// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
|
|
// RV32-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.paas.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
|
|
// RV32-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP3]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_paas_x_i16x2(
|
|
// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
|
|
// RV64-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.paas.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
|
|
// RV64-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP3]]
|
|
//
|
|
int16x2_t test_paas_x_i16x2(int16x2_t a, int16x2_t b) {
|
|
return __riscv_paas_x_i16x2(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_pasa_x_i16x2(
|
|
// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
|
|
// RV32-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.pasa.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
|
|
// RV32-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP3]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_pasa_x_i16x2(
|
|
// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
|
|
// RV64-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.pasa.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
|
|
// RV64-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP3]]
|
|
//
|
|
int16x2_t test_pasa_x_i16x2(int16x2_t a, int16x2_t b) {
|
|
return __riscv_pasa_x_i16x2(a, b);
|
|
}
|
|
|
|
/* Packed Exchanged Addition and Subtraction (64-bit) */
|
|
// RV32-LABEL: define dso_local i64 @test_pas_x_i16x4(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.pas.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
|
|
// RV32-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP3]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pas_x_i16x4(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.pas.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
|
|
// RV64-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP3]]
|
|
//
|
|
int16x4_t test_pas_x_i16x4(int16x4_t a, int16x4_t b) {
|
|
return __riscv_pas_x_i16x4(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_psa_x_i16x4(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.psa.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
|
|
// RV32-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP3]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_psa_x_i16x4(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.psa.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
|
|
// RV64-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP3]]
|
|
//
|
|
int16x4_t test_psa_x_i16x4(int16x4_t a, int16x4_t b) {
|
|
return __riscv_psa_x_i16x4(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_psas_x_i16x4(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.psas.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
|
|
// RV32-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP3]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_psas_x_i16x4(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.psas.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
|
|
// RV64-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP3]]
|
|
//
|
|
int16x4_t test_psas_x_i16x4(int16x4_t a, int16x4_t b) {
|
|
return __riscv_psas_x_i16x4(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pssa_x_i16x4(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.pssa.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
|
|
// RV32-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP3]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pssa_x_i16x4(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.pssa.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
|
|
// RV64-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP3]]
|
|
//
|
|
int16x4_t test_pssa_x_i16x4(int16x4_t a, int16x4_t b) {
|
|
return __riscv_pssa_x_i16x4(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_paas_x_i16x4(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.paas.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
|
|
// RV32-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP3]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_paas_x_i16x4(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.paas.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
|
|
// RV64-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP3]]
|
|
//
|
|
int16x4_t test_paas_x_i16x4(int16x4_t a, int16x4_t b) {
|
|
return __riscv_paas_x_i16x4(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pasa_x_i16x4(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.pasa.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
|
|
// RV32-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP3]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pasa_x_i16x4(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.pasa.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
|
|
// RV64-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP3]]
|
|
//
|
|
int16x4_t test_pasa_x_i16x4(int16x4_t a, int16x4_t b) {
|
|
return __riscv_pasa_x_i16x4(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pas_x_i32x2(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
|
|
// RV32-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.pas.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
|
|
// RV32-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP3]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pas_x_i32x2(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
|
|
// RV64-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.pas.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
|
|
// RV64-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP3]]
|
|
//
|
|
int32x2_t test_pas_x_i32x2(int32x2_t a, int32x2_t b) {
|
|
return __riscv_pas_x_i32x2(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_psa_x_i32x2(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
|
|
// RV32-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.psa.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
|
|
// RV32-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP3]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_psa_x_i32x2(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
|
|
// RV64-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.psa.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
|
|
// RV64-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP3]]
|
|
//
|
|
int32x2_t test_psa_x_i32x2(int32x2_t a, int32x2_t b) {
|
|
return __riscv_psa_x_i32x2(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_psas_x_i32x2(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
|
|
// RV32-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.psas.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
|
|
// RV32-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP3]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_psas_x_i32x2(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
|
|
// RV64-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.psas.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
|
|
// RV64-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP3]]
|
|
//
|
|
int32x2_t test_psas_x_i32x2(int32x2_t a, int32x2_t b) {
|
|
return __riscv_psas_x_i32x2(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pssa_x_i32x2(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
|
|
// RV32-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.pssa.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
|
|
// RV32-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP3]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pssa_x_i32x2(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
|
|
// RV64-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.pssa.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
|
|
// RV64-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP3]]
|
|
//
|
|
int32x2_t test_pssa_x_i32x2(int32x2_t a, int32x2_t b) {
|
|
return __riscv_pssa_x_i32x2(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_paas_x_i32x2(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
|
|
// RV32-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.paas.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
|
|
// RV32-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP3]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_paas_x_i32x2(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
|
|
// RV64-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.paas.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
|
|
// RV64-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP3]]
|
|
//
|
|
int32x2_t test_paas_x_i32x2(int32x2_t a, int32x2_t b) {
|
|
return __riscv_paas_x_i32x2(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pasa_x_i32x2(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
|
|
// RV32-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.pasa.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
|
|
// RV32-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP3]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pasa_x_i32x2(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
|
|
// RV64-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.pasa.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
|
|
// RV64-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP3]]
|
|
//
|
|
int32x2_t test_pasa_x_i32x2(int32x2_t a, int32x2_t b) {
|
|
return __riscv_pasa_x_i32x2(a, b);
|
|
}
|
|
|
|
/* Packed Minimum and Maximum (32-bit) */
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_pmin_i8x4(
|
|
// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
|
|
// RV32-NEXT: [[ELT_MIN_I:%.*]] = call <4 x i8> @llvm.smin.v4i8(<4 x i8> [[TMP0]], <4 x i8> [[TMP1]])
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[ELT_MIN_I]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_pmin_i8x4(
|
|
// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
|
|
// RV64-NEXT: [[ELT_MIN_I:%.*]] = call <4 x i8> @llvm.smin.v4i8(<4 x i8> [[TMP0]], <4 x i8> [[TMP1]])
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[ELT_MIN_I]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
int8x4_t test_pmin_i8x4(int8x4_t a, int8x4_t b) {
|
|
return __riscv_pmin_i8x4(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_pmin_i16x2(
|
|
// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
|
|
// RV32-NEXT: [[ELT_MIN_I:%.*]] = call <2 x i16> @llvm.smin.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[ELT_MIN_I]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_pmin_i16x2(
|
|
// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
|
|
// RV64-NEXT: [[ELT_MIN_I:%.*]] = call <2 x i16> @llvm.smin.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[ELT_MIN_I]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
int16x2_t test_pmin_i16x2(int16x2_t a, int16x2_t b) {
|
|
return __riscv_pmin_i16x2(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_pminu_u8x4(
|
|
// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
|
|
// RV32-NEXT: [[ELT_MIN_I:%.*]] = call <4 x i8> @llvm.umin.v4i8(<4 x i8> [[TMP0]], <4 x i8> [[TMP1]])
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[ELT_MIN_I]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_pminu_u8x4(
|
|
// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
|
|
// RV64-NEXT: [[ELT_MIN_I:%.*]] = call <4 x i8> @llvm.umin.v4i8(<4 x i8> [[TMP0]], <4 x i8> [[TMP1]])
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[ELT_MIN_I]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
uint8x4_t test_pminu_u8x4(uint8x4_t a, uint8x4_t b) {
|
|
return __riscv_pminu_u8x4(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_pminu_u16x2(
|
|
// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
|
|
// RV32-NEXT: [[ELT_MIN_I:%.*]] = call <2 x i16> @llvm.umin.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[ELT_MIN_I]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_pminu_u16x2(
|
|
// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
|
|
// RV64-NEXT: [[ELT_MIN_I:%.*]] = call <2 x i16> @llvm.umin.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[ELT_MIN_I]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
uint16x2_t test_pminu_u16x2(uint16x2_t a, uint16x2_t b) {
|
|
return __riscv_pminu_u16x2(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_pmax_i8x4(
|
|
// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
|
|
// RV32-NEXT: [[ELT_MAX_I:%.*]] = call <4 x i8> @llvm.smax.v4i8(<4 x i8> [[TMP0]], <4 x i8> [[TMP1]])
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[ELT_MAX_I]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_pmax_i8x4(
|
|
// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
|
|
// RV64-NEXT: [[ELT_MAX_I:%.*]] = call <4 x i8> @llvm.smax.v4i8(<4 x i8> [[TMP0]], <4 x i8> [[TMP1]])
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[ELT_MAX_I]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
int8x4_t test_pmax_i8x4(int8x4_t a, int8x4_t b) {
|
|
return __riscv_pmax_i8x4(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_pmax_i16x2(
|
|
// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
|
|
// RV32-NEXT: [[ELT_MAX_I:%.*]] = call <2 x i16> @llvm.smax.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[ELT_MAX_I]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_pmax_i16x2(
|
|
// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
|
|
// RV64-NEXT: [[ELT_MAX_I:%.*]] = call <2 x i16> @llvm.smax.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[ELT_MAX_I]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
int16x2_t test_pmax_i16x2(int16x2_t a, int16x2_t b) {
|
|
return __riscv_pmax_i16x2(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_pmaxu_u8x4(
|
|
// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
|
|
// RV32-NEXT: [[ELT_MAX_I:%.*]] = call <4 x i8> @llvm.umax.v4i8(<4 x i8> [[TMP0]], <4 x i8> [[TMP1]])
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[ELT_MAX_I]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_pmaxu_u8x4(
|
|
// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
|
|
// RV64-NEXT: [[ELT_MAX_I:%.*]] = call <4 x i8> @llvm.umax.v4i8(<4 x i8> [[TMP0]], <4 x i8> [[TMP1]])
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[ELT_MAX_I]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
uint8x4_t test_pmaxu_u8x4(uint8x4_t a, uint8x4_t b) {
|
|
return __riscv_pmaxu_u8x4(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_pmaxu_u16x2(
|
|
// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
|
|
// RV32-NEXT: [[ELT_MAX_I:%.*]] = call <2 x i16> @llvm.umax.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[ELT_MAX_I]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_pmaxu_u16x2(
|
|
// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
|
|
// RV64-NEXT: [[ELT_MAX_I:%.*]] = call <2 x i16> @llvm.umax.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[ELT_MAX_I]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
uint16x2_t test_pmaxu_u16x2(uint16x2_t a, uint16x2_t b) {
|
|
return __riscv_pmaxu_u16x2(a, b);
|
|
}
|
|
|
|
/* Packed Minimum and Maximum (64-bit) */
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pmin_i8x8(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
|
|
// RV32-NEXT: [[ELT_MIN_I:%.*]] = call <8 x i8> @llvm.smin.v8i8(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]])
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[ELT_MIN_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pmin_i8x8(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
|
|
// RV64-NEXT: [[ELT_MIN_I:%.*]] = call <8 x i8> @llvm.smin.v8i8(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]])
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[ELT_MIN_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
int8x8_t test_pmin_i8x8(int8x8_t a, int8x8_t b) {
|
|
return __riscv_pmin_i8x8(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pmin_i16x4(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[ELT_MIN_I:%.*]] = call <4 x i16> @llvm.smin.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[ELT_MIN_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pmin_i16x4(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[ELT_MIN_I:%.*]] = call <4 x i16> @llvm.smin.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[ELT_MIN_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
int16x4_t test_pmin_i16x4(int16x4_t a, int16x4_t b) {
|
|
return __riscv_pmin_i16x4(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pmin_i32x2(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
|
|
// RV32-NEXT: [[ELT_MIN_I:%.*]] = call <2 x i32> @llvm.smin.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[ELT_MIN_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pmin_i32x2(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
|
|
// RV64-NEXT: [[ELT_MIN_I:%.*]] = call <2 x i32> @llvm.smin.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[ELT_MIN_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
int32x2_t test_pmin_i32x2(int32x2_t a, int32x2_t b) {
|
|
return __riscv_pmin_i32x2(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pminu_u8x8(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
|
|
// RV32-NEXT: [[ELT_MIN_I:%.*]] = call <8 x i8> @llvm.umin.v8i8(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]])
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[ELT_MIN_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pminu_u8x8(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
|
|
// RV64-NEXT: [[ELT_MIN_I:%.*]] = call <8 x i8> @llvm.umin.v8i8(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]])
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[ELT_MIN_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
uint8x8_t test_pminu_u8x8(uint8x8_t a, uint8x8_t b) {
|
|
return __riscv_pminu_u8x8(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pminu_u16x4(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[ELT_MIN_I:%.*]] = call <4 x i16> @llvm.umin.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[ELT_MIN_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pminu_u16x4(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[ELT_MIN_I:%.*]] = call <4 x i16> @llvm.umin.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[ELT_MIN_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
uint16x4_t test_pminu_u16x4(uint16x4_t a, uint16x4_t b) {
|
|
return __riscv_pminu_u16x4(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pminu_u32x2(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
|
|
// RV32-NEXT: [[ELT_MIN_I:%.*]] = call <2 x i32> @llvm.umin.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[ELT_MIN_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pminu_u32x2(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
|
|
// RV64-NEXT: [[ELT_MIN_I:%.*]] = call <2 x i32> @llvm.umin.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[ELT_MIN_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
uint32x2_t test_pminu_u32x2(uint32x2_t a, uint32x2_t b) {
|
|
return __riscv_pminu_u32x2(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pmax_i8x8(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
|
|
// RV32-NEXT: [[ELT_MAX_I:%.*]] = call <8 x i8> @llvm.smax.v8i8(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]])
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[ELT_MAX_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pmax_i8x8(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
|
|
// RV64-NEXT: [[ELT_MAX_I:%.*]] = call <8 x i8> @llvm.smax.v8i8(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]])
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[ELT_MAX_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
int8x8_t test_pmax_i8x8(int8x8_t a, int8x8_t b) {
|
|
return __riscv_pmax_i8x8(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pmax_i16x4(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[ELT_MAX_I:%.*]] = call <4 x i16> @llvm.smax.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[ELT_MAX_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pmax_i16x4(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[ELT_MAX_I:%.*]] = call <4 x i16> @llvm.smax.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[ELT_MAX_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
int16x4_t test_pmax_i16x4(int16x4_t a, int16x4_t b) {
|
|
return __riscv_pmax_i16x4(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pmax_i32x2(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
|
|
// RV32-NEXT: [[ELT_MAX_I:%.*]] = call <2 x i32> @llvm.smax.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[ELT_MAX_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pmax_i32x2(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
|
|
// RV64-NEXT: [[ELT_MAX_I:%.*]] = call <2 x i32> @llvm.smax.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[ELT_MAX_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
int32x2_t test_pmax_i32x2(int32x2_t a, int32x2_t b) {
|
|
return __riscv_pmax_i32x2(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pmaxu_u8x8(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
|
|
// RV32-NEXT: [[ELT_MAX_I:%.*]] = call <8 x i8> @llvm.umax.v8i8(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]])
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[ELT_MAX_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pmaxu_u8x8(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
|
|
// RV64-NEXT: [[ELT_MAX_I:%.*]] = call <8 x i8> @llvm.umax.v8i8(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]])
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[ELT_MAX_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
uint8x8_t test_pmaxu_u8x8(uint8x8_t a, uint8x8_t b) {
|
|
return __riscv_pmaxu_u8x8(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pmaxu_u16x4(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[ELT_MAX_I:%.*]] = call <4 x i16> @llvm.umax.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[ELT_MAX_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pmaxu_u16x4(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[ELT_MAX_I:%.*]] = call <4 x i16> @llvm.umax.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[ELT_MAX_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
uint16x4_t test_pmaxu_u16x4(uint16x4_t a, uint16x4_t b) {
|
|
return __riscv_pmaxu_u16x4(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pmaxu_u32x2(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
|
|
// RV32-NEXT: [[ELT_MAX_I:%.*]] = call <2 x i32> @llvm.umax.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[ELT_MAX_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pmaxu_u32x2(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
|
|
// RV64-NEXT: [[ELT_MAX_I:%.*]] = call <2 x i32> @llvm.umax.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[ELT_MAX_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
uint32x2_t test_pmaxu_u32x2(uint32x2_t a, uint32x2_t b) {
|
|
return __riscv_pmaxu_u32x2(a, b);
|
|
}
|
|
/* Packed Comparison (32-bit) */
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_pmseq_i8x4_u8x4(
|
|
// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
|
|
// RV32-NEXT: [[CMP_I:%.*]] = icmp eq <4 x i8> [[TMP0]], [[TMP1]]
|
|
// RV32-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i8>
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SEXT_I]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_pmseq_i8x4_u8x4(
|
|
// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
|
|
// RV64-NEXT: [[CMP_I:%.*]] = icmp eq <4 x i8> [[TMP0]], [[TMP1]]
|
|
// RV64-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i8>
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SEXT_I]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
uint8x4_t test_pmseq_i8x4_u8x4(int8x4_t a, int8x4_t b) {
|
|
return __riscv_pmseq_i8x4_u8x4(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_pmseq_u8x4_u8x4(
|
|
// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
|
|
// RV32-NEXT: [[CMP_I:%.*]] = icmp eq <4 x i8> [[TMP0]], [[TMP1]]
|
|
// RV32-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i8>
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SEXT_I]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_pmseq_u8x4_u8x4(
|
|
// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
|
|
// RV64-NEXT: [[CMP_I:%.*]] = icmp eq <4 x i8> [[TMP0]], [[TMP1]]
|
|
// RV64-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i8>
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SEXT_I]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
uint8x4_t test_pmseq_u8x4_u8x4(uint8x4_t a, uint8x4_t b) {
|
|
return __riscv_pmseq_u8x4_u8x4(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_pmsne_i8x4_u8x4(
|
|
// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
|
|
// RV32-NEXT: [[CMP_I:%.*]] = icmp ne <4 x i8> [[TMP0]], [[TMP1]]
|
|
// RV32-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i8>
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SEXT_I]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_pmsne_i8x4_u8x4(
|
|
// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
|
|
// RV64-NEXT: [[CMP_I:%.*]] = icmp ne <4 x i8> [[TMP0]], [[TMP1]]
|
|
// RV64-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i8>
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SEXT_I]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
uint8x4_t test_pmsne_i8x4_u8x4(int8x4_t a, int8x4_t b) {
|
|
return __riscv_pmsne_i8x4_u8x4(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_pmsne_u8x4_u8x4(
|
|
// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
|
|
// RV32-NEXT: [[CMP_I:%.*]] = icmp ne <4 x i8> [[TMP0]], [[TMP1]]
|
|
// RV32-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i8>
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SEXT_I]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_pmsne_u8x4_u8x4(
|
|
// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
|
|
// RV64-NEXT: [[CMP_I:%.*]] = icmp ne <4 x i8> [[TMP0]], [[TMP1]]
|
|
// RV64-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i8>
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SEXT_I]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
uint8x4_t test_pmsne_u8x4_u8x4(uint8x4_t a, uint8x4_t b) {
|
|
return __riscv_pmsne_u8x4_u8x4(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_pmslt_u8x4(
|
|
// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
|
|
// RV32-NEXT: [[CMP_I:%.*]] = icmp slt <4 x i8> [[TMP0]], [[TMP1]]
|
|
// RV32-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i8>
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SEXT_I]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_pmslt_u8x4(
|
|
// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
|
|
// RV64-NEXT: [[CMP_I:%.*]] = icmp slt <4 x i8> [[TMP0]], [[TMP1]]
|
|
// RV64-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i8>
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SEXT_I]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
uint8x4_t test_pmslt_u8x4(int8x4_t a, int8x4_t b) {
|
|
return __riscv_pmslt_u8x4(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_pmsltu_u8x4(
|
|
// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
|
|
// RV32-NEXT: [[CMP_I:%.*]] = icmp ult <4 x i8> [[TMP0]], [[TMP1]]
|
|
// RV32-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i8>
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SEXT_I]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_pmsltu_u8x4(
|
|
// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
|
|
// RV64-NEXT: [[CMP_I:%.*]] = icmp ult <4 x i8> [[TMP0]], [[TMP1]]
|
|
// RV64-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i8>
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SEXT_I]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
uint8x4_t test_pmsltu_u8x4(uint8x4_t a, uint8x4_t b) {
|
|
return __riscv_pmsltu_u8x4(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_pmsgt_u8x4(
|
|
// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
|
|
// RV32-NEXT: [[CMP_I:%.*]] = icmp sgt <4 x i8> [[TMP0]], [[TMP1]]
|
|
// RV32-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i8>
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SEXT_I]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_pmsgt_u8x4(
|
|
// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
|
|
// RV64-NEXT: [[CMP_I:%.*]] = icmp sgt <4 x i8> [[TMP0]], [[TMP1]]
|
|
// RV64-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i8>
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SEXT_I]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
uint8x4_t test_pmsgt_u8x4(int8x4_t a, int8x4_t b) {
|
|
return __riscv_pmsgt_u8x4(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_pmsgtu_u8x4(
|
|
// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
|
|
// RV32-NEXT: [[CMP_I:%.*]] = icmp ugt <4 x i8> [[TMP0]], [[TMP1]]
|
|
// RV32-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i8>
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SEXT_I]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_pmsgtu_u8x4(
|
|
// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
|
|
// RV64-NEXT: [[CMP_I:%.*]] = icmp ugt <4 x i8> [[TMP0]], [[TMP1]]
|
|
// RV64-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i8>
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SEXT_I]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
uint8x4_t test_pmsgtu_u8x4(uint8x4_t a, uint8x4_t b) {
|
|
return __riscv_pmsgtu_u8x4(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_pmsge_u8x4(
|
|
// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
|
|
// RV32-NEXT: [[CMP_I:%.*]] = icmp sge <4 x i8> [[TMP0]], [[TMP1]]
|
|
// RV32-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i8>
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SEXT_I]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_pmsge_u8x4(
|
|
// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
|
|
// RV64-NEXT: [[CMP_I:%.*]] = icmp sge <4 x i8> [[TMP0]], [[TMP1]]
|
|
// RV64-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i8>
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SEXT_I]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
uint8x4_t test_pmsge_u8x4(int8x4_t a, int8x4_t b) {
|
|
return __riscv_pmsge_u8x4(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_pmsgeu_u8x4(
|
|
// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
|
|
// RV32-NEXT: [[CMP_I:%.*]] = icmp uge <4 x i8> [[TMP0]], [[TMP1]]
|
|
// RV32-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i8>
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SEXT_I]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_pmsgeu_u8x4(
|
|
// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
|
|
// RV64-NEXT: [[CMP_I:%.*]] = icmp uge <4 x i8> [[TMP0]], [[TMP1]]
|
|
// RV64-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i8>
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SEXT_I]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
uint8x4_t test_pmsgeu_u8x4(uint8x4_t a, uint8x4_t b) {
|
|
return __riscv_pmsgeu_u8x4(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_pmsle_u8x4(
|
|
// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
|
|
// RV32-NEXT: [[CMP_I:%.*]] = icmp sle <4 x i8> [[TMP0]], [[TMP1]]
|
|
// RV32-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i8>
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SEXT_I]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_pmsle_u8x4(
|
|
// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
|
|
// RV64-NEXT: [[CMP_I:%.*]] = icmp sle <4 x i8> [[TMP0]], [[TMP1]]
|
|
// RV64-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i8>
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SEXT_I]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
uint8x4_t test_pmsle_u8x4(int8x4_t a, int8x4_t b) {
|
|
return __riscv_pmsle_u8x4(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_pmsleu_u8x4(
|
|
// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
|
|
// RV32-NEXT: [[CMP_I:%.*]] = icmp ule <4 x i8> [[TMP0]], [[TMP1]]
|
|
// RV32-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i8>
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SEXT_I]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_pmsleu_u8x4(
|
|
// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <4 x i8>
|
|
// RV64-NEXT: [[CMP_I:%.*]] = icmp ule <4 x i8> [[TMP0]], [[TMP1]]
|
|
// RV64-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i8>
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SEXT_I]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
uint8x4_t test_pmsleu_u8x4(uint8x4_t a, uint8x4_t b) {
|
|
return __riscv_pmsleu_u8x4(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_pmseq_i16x2_u16x2(
|
|
// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
|
|
// RV32-NEXT: [[CMP_I:%.*]] = icmp eq <2 x i16> [[TMP0]], [[TMP1]]
|
|
// RV32-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i16>
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[SEXT_I]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_pmseq_i16x2_u16x2(
|
|
// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
|
|
// RV64-NEXT: [[CMP_I:%.*]] = icmp eq <2 x i16> [[TMP0]], [[TMP1]]
|
|
// RV64-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i16>
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[SEXT_I]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
uint16x2_t test_pmseq_i16x2_u16x2(int16x2_t a, int16x2_t b) {
|
|
return __riscv_pmseq_i16x2_u16x2(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_pmseq_u16x2_u16x2(
|
|
// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
|
|
// RV32-NEXT: [[CMP_I:%.*]] = icmp eq <2 x i16> [[TMP0]], [[TMP1]]
|
|
// RV32-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i16>
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[SEXT_I]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_pmseq_u16x2_u16x2(
|
|
// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
|
|
// RV64-NEXT: [[CMP_I:%.*]] = icmp eq <2 x i16> [[TMP0]], [[TMP1]]
|
|
// RV64-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i16>
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[SEXT_I]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
uint16x2_t test_pmseq_u16x2_u16x2(uint16x2_t a, uint16x2_t b) {
|
|
return __riscv_pmseq_u16x2_u16x2(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_pmsne_i16x2_u16x2(
|
|
// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
|
|
// RV32-NEXT: [[CMP_I:%.*]] = icmp ne <2 x i16> [[TMP0]], [[TMP1]]
|
|
// RV32-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i16>
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[SEXT_I]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_pmsne_i16x2_u16x2(
|
|
// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
|
|
// RV64-NEXT: [[CMP_I:%.*]] = icmp ne <2 x i16> [[TMP0]], [[TMP1]]
|
|
// RV64-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i16>
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[SEXT_I]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
uint16x2_t test_pmsne_i16x2_u16x2(int16x2_t a, int16x2_t b) {
|
|
return __riscv_pmsne_i16x2_u16x2(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_pmsne_u16x2_u16x2(
|
|
// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
|
|
// RV32-NEXT: [[CMP_I:%.*]] = icmp ne <2 x i16> [[TMP0]], [[TMP1]]
|
|
// RV32-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i16>
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[SEXT_I]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_pmsne_u16x2_u16x2(
|
|
// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
|
|
// RV64-NEXT: [[CMP_I:%.*]] = icmp ne <2 x i16> [[TMP0]], [[TMP1]]
|
|
// RV64-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i16>
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[SEXT_I]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
uint16x2_t test_pmsne_u16x2_u16x2(uint16x2_t a, uint16x2_t b) {
|
|
return __riscv_pmsne_u16x2_u16x2(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_pmslt_u16x2(
|
|
// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
|
|
// RV32-NEXT: [[CMP_I:%.*]] = icmp slt <2 x i16> [[TMP0]], [[TMP1]]
|
|
// RV32-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i16>
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[SEXT_I]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_pmslt_u16x2(
|
|
// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
|
|
// RV64-NEXT: [[CMP_I:%.*]] = icmp slt <2 x i16> [[TMP0]], [[TMP1]]
|
|
// RV64-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i16>
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[SEXT_I]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
uint16x2_t test_pmslt_u16x2(int16x2_t a, int16x2_t b) {
|
|
return __riscv_pmslt_u16x2(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_pmsltu_u16x2(
|
|
// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
|
|
// RV32-NEXT: [[CMP_I:%.*]] = icmp ult <2 x i16> [[TMP0]], [[TMP1]]
|
|
// RV32-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i16>
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[SEXT_I]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_pmsltu_u16x2(
|
|
// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
|
|
// RV64-NEXT: [[CMP_I:%.*]] = icmp ult <2 x i16> [[TMP0]], [[TMP1]]
|
|
// RV64-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i16>
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[SEXT_I]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
uint16x2_t test_pmsltu_u16x2(uint16x2_t a, uint16x2_t b) {
|
|
return __riscv_pmsltu_u16x2(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_pmsgt_u16x2(
|
|
// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
|
|
// RV32-NEXT: [[CMP_I:%.*]] = icmp sgt <2 x i16> [[TMP0]], [[TMP1]]
|
|
// RV32-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i16>
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[SEXT_I]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_pmsgt_u16x2(
|
|
// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
|
|
// RV64-NEXT: [[CMP_I:%.*]] = icmp sgt <2 x i16> [[TMP0]], [[TMP1]]
|
|
// RV64-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i16>
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[SEXT_I]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
uint16x2_t test_pmsgt_u16x2(int16x2_t a, int16x2_t b) {
|
|
return __riscv_pmsgt_u16x2(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_pmsgtu_u16x2(
|
|
// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
|
|
// RV32-NEXT: [[CMP_I:%.*]] = icmp ugt <2 x i16> [[TMP0]], [[TMP1]]
|
|
// RV32-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i16>
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[SEXT_I]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_pmsgtu_u16x2(
|
|
// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
|
|
// RV64-NEXT: [[CMP_I:%.*]] = icmp ugt <2 x i16> [[TMP0]], [[TMP1]]
|
|
// RV64-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i16>
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[SEXT_I]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
uint16x2_t test_pmsgtu_u16x2(uint16x2_t a, uint16x2_t b) {
|
|
return __riscv_pmsgtu_u16x2(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_pmsge_u16x2(
|
|
// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
|
|
// RV32-NEXT: [[CMP_I:%.*]] = icmp sge <2 x i16> [[TMP0]], [[TMP1]]
|
|
// RV32-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i16>
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[SEXT_I]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_pmsge_u16x2(
|
|
// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
|
|
// RV64-NEXT: [[CMP_I:%.*]] = icmp sge <2 x i16> [[TMP0]], [[TMP1]]
|
|
// RV64-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i16>
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[SEXT_I]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
uint16x2_t test_pmsge_u16x2(int16x2_t a, int16x2_t b) {
|
|
return __riscv_pmsge_u16x2(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_pmsgeu_u16x2(
|
|
// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
|
|
// RV32-NEXT: [[CMP_I:%.*]] = icmp uge <2 x i16> [[TMP0]], [[TMP1]]
|
|
// RV32-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i16>
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[SEXT_I]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_pmsgeu_u16x2(
|
|
// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
|
|
// RV64-NEXT: [[CMP_I:%.*]] = icmp uge <2 x i16> [[TMP0]], [[TMP1]]
|
|
// RV64-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i16>
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[SEXT_I]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
uint16x2_t test_pmsgeu_u16x2(uint16x2_t a, uint16x2_t b) {
|
|
return __riscv_pmsgeu_u16x2(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_pmsle_u16x2(
|
|
// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
|
|
// RV32-NEXT: [[CMP_I:%.*]] = icmp sle <2 x i16> [[TMP0]], [[TMP1]]
|
|
// RV32-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i16>
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[SEXT_I]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_pmsle_u16x2(
|
|
// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
|
|
// RV64-NEXT: [[CMP_I:%.*]] = icmp sle <2 x i16> [[TMP0]], [[TMP1]]
|
|
// RV64-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i16>
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[SEXT_I]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
uint16x2_t test_pmsle_u16x2(int16x2_t a, int16x2_t b) {
|
|
return __riscv_pmsle_u16x2(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_pmsleu_u16x2(
|
|
// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
|
|
// RV32-NEXT: [[CMP_I:%.*]] = icmp ule <2 x i16> [[TMP0]], [[TMP1]]
|
|
// RV32-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i16>
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[SEXT_I]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_pmsleu_u16x2(
|
|
// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
|
|
// RV64-NEXT: [[CMP_I:%.*]] = icmp ule <2 x i16> [[TMP0]], [[TMP1]]
|
|
// RV64-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i16>
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[SEXT_I]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
uint16x2_t test_pmsleu_u16x2(uint16x2_t a, uint16x2_t b) {
|
|
return __riscv_pmsleu_u16x2(a, b);
|
|
}
|
|
|
|
/* Packed Comparison (64-bit) */
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pmseq_i8x8_u8x8(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
|
|
// RV32-NEXT: [[CMP_I:%.*]] = icmp eq <8 x i8> [[TMP0]], [[TMP1]]
|
|
// RV32-NEXT: [[SEXT_I:%.*]] = sext <8 x i1> [[CMP_I]] to <8 x i8>
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SEXT_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pmseq_i8x8_u8x8(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
|
|
// RV64-NEXT: [[CMP_I:%.*]] = icmp eq <8 x i8> [[TMP0]], [[TMP1]]
|
|
// RV64-NEXT: [[SEXT_I:%.*]] = sext <8 x i1> [[CMP_I]] to <8 x i8>
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SEXT_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
uint8x8_t test_pmseq_i8x8_u8x8(int8x8_t a, int8x8_t b) {
|
|
return __riscv_pmseq_i8x8_u8x8(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pmseq_u8x8_u8x8(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
|
|
// RV32-NEXT: [[CMP_I:%.*]] = icmp eq <8 x i8> [[TMP0]], [[TMP1]]
|
|
// RV32-NEXT: [[SEXT_I:%.*]] = sext <8 x i1> [[CMP_I]] to <8 x i8>
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SEXT_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pmseq_u8x8_u8x8(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
|
|
// RV64-NEXT: [[CMP_I:%.*]] = icmp eq <8 x i8> [[TMP0]], [[TMP1]]
|
|
// RV64-NEXT: [[SEXT_I:%.*]] = sext <8 x i1> [[CMP_I]] to <8 x i8>
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SEXT_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
uint8x8_t test_pmseq_u8x8_u8x8(uint8x8_t a, uint8x8_t b) {
|
|
return __riscv_pmseq_u8x8_u8x8(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pmsne_i8x8_u8x8(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
|
|
// RV32-NEXT: [[CMP_I:%.*]] = icmp ne <8 x i8> [[TMP0]], [[TMP1]]
|
|
// RV32-NEXT: [[SEXT_I:%.*]] = sext <8 x i1> [[CMP_I]] to <8 x i8>
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SEXT_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pmsne_i8x8_u8x8(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
|
|
// RV64-NEXT: [[CMP_I:%.*]] = icmp ne <8 x i8> [[TMP0]], [[TMP1]]
|
|
// RV64-NEXT: [[SEXT_I:%.*]] = sext <8 x i1> [[CMP_I]] to <8 x i8>
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SEXT_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
uint8x8_t test_pmsne_i8x8_u8x8(int8x8_t a, int8x8_t b) {
|
|
return __riscv_pmsne_i8x8_u8x8(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pmsne_u8x8_u8x8(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
|
|
// RV32-NEXT: [[CMP_I:%.*]] = icmp ne <8 x i8> [[TMP0]], [[TMP1]]
|
|
// RV32-NEXT: [[SEXT_I:%.*]] = sext <8 x i1> [[CMP_I]] to <8 x i8>
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SEXT_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pmsne_u8x8_u8x8(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
|
|
// RV64-NEXT: [[CMP_I:%.*]] = icmp ne <8 x i8> [[TMP0]], [[TMP1]]
|
|
// RV64-NEXT: [[SEXT_I:%.*]] = sext <8 x i1> [[CMP_I]] to <8 x i8>
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SEXT_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
uint8x8_t test_pmsne_u8x8_u8x8(uint8x8_t a, uint8x8_t b) {
|
|
return __riscv_pmsne_u8x8_u8x8(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pmslt_u8x8(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
|
|
// RV32-NEXT: [[CMP_I:%.*]] = icmp slt <8 x i8> [[TMP0]], [[TMP1]]
|
|
// RV32-NEXT: [[SEXT_I:%.*]] = sext <8 x i1> [[CMP_I]] to <8 x i8>
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SEXT_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pmslt_u8x8(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
|
|
// RV64-NEXT: [[CMP_I:%.*]] = icmp slt <8 x i8> [[TMP0]], [[TMP1]]
|
|
// RV64-NEXT: [[SEXT_I:%.*]] = sext <8 x i1> [[CMP_I]] to <8 x i8>
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SEXT_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
uint8x8_t test_pmslt_u8x8(int8x8_t a, int8x8_t b) {
|
|
return __riscv_pmslt_u8x8(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pmsltu_u8x8(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
|
|
// RV32-NEXT: [[CMP_I:%.*]] = icmp ult <8 x i8> [[TMP0]], [[TMP1]]
|
|
// RV32-NEXT: [[SEXT_I:%.*]] = sext <8 x i1> [[CMP_I]] to <8 x i8>
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SEXT_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pmsltu_u8x8(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
|
|
// RV64-NEXT: [[CMP_I:%.*]] = icmp ult <8 x i8> [[TMP0]], [[TMP1]]
|
|
// RV64-NEXT: [[SEXT_I:%.*]] = sext <8 x i1> [[CMP_I]] to <8 x i8>
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SEXT_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
uint8x8_t test_pmsltu_u8x8(uint8x8_t a, uint8x8_t b) {
|
|
return __riscv_pmsltu_u8x8(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pmsgt_u8x8(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
|
|
// RV32-NEXT: [[CMP_I:%.*]] = icmp sgt <8 x i8> [[TMP0]], [[TMP1]]
|
|
// RV32-NEXT: [[SEXT_I:%.*]] = sext <8 x i1> [[CMP_I]] to <8 x i8>
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SEXT_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pmsgt_u8x8(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
|
|
// RV64-NEXT: [[CMP_I:%.*]] = icmp sgt <8 x i8> [[TMP0]], [[TMP1]]
|
|
// RV64-NEXT: [[SEXT_I:%.*]] = sext <8 x i1> [[CMP_I]] to <8 x i8>
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SEXT_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
uint8x8_t test_pmsgt_u8x8(int8x8_t a, int8x8_t b) {
|
|
return __riscv_pmsgt_u8x8(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pmsgtu_u8x8(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
|
|
// RV32-NEXT: [[CMP_I:%.*]] = icmp ugt <8 x i8> [[TMP0]], [[TMP1]]
|
|
// RV32-NEXT: [[SEXT_I:%.*]] = sext <8 x i1> [[CMP_I]] to <8 x i8>
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SEXT_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pmsgtu_u8x8(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
|
|
// RV64-NEXT: [[CMP_I:%.*]] = icmp ugt <8 x i8> [[TMP0]], [[TMP1]]
|
|
// RV64-NEXT: [[SEXT_I:%.*]] = sext <8 x i1> [[CMP_I]] to <8 x i8>
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SEXT_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
uint8x8_t test_pmsgtu_u8x8(uint8x8_t a, uint8x8_t b) {
|
|
return __riscv_pmsgtu_u8x8(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pmsge_u8x8(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
|
|
// RV32-NEXT: [[CMP_I:%.*]] = icmp sge <8 x i8> [[TMP0]], [[TMP1]]
|
|
// RV32-NEXT: [[SEXT_I:%.*]] = sext <8 x i1> [[CMP_I]] to <8 x i8>
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SEXT_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pmsge_u8x8(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
|
|
// RV64-NEXT: [[CMP_I:%.*]] = icmp sge <8 x i8> [[TMP0]], [[TMP1]]
|
|
// RV64-NEXT: [[SEXT_I:%.*]] = sext <8 x i1> [[CMP_I]] to <8 x i8>
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SEXT_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
uint8x8_t test_pmsge_u8x8(int8x8_t a, int8x8_t b) {
|
|
return __riscv_pmsge_u8x8(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pmsgeu_u8x8(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
|
|
// RV32-NEXT: [[CMP_I:%.*]] = icmp uge <8 x i8> [[TMP0]], [[TMP1]]
|
|
// RV32-NEXT: [[SEXT_I:%.*]] = sext <8 x i1> [[CMP_I]] to <8 x i8>
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SEXT_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pmsgeu_u8x8(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
|
|
// RV64-NEXT: [[CMP_I:%.*]] = icmp uge <8 x i8> [[TMP0]], [[TMP1]]
|
|
// RV64-NEXT: [[SEXT_I:%.*]] = sext <8 x i1> [[CMP_I]] to <8 x i8>
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SEXT_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
uint8x8_t test_pmsgeu_u8x8(uint8x8_t a, uint8x8_t b) {
|
|
return __riscv_pmsgeu_u8x8(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pmsle_u8x8(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
|
|
// RV32-NEXT: [[CMP_I:%.*]] = icmp sle <8 x i8> [[TMP0]], [[TMP1]]
|
|
// RV32-NEXT: [[SEXT_I:%.*]] = sext <8 x i1> [[CMP_I]] to <8 x i8>
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SEXT_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pmsle_u8x8(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
|
|
// RV64-NEXT: [[CMP_I:%.*]] = icmp sle <8 x i8> [[TMP0]], [[TMP1]]
|
|
// RV64-NEXT: [[SEXT_I:%.*]] = sext <8 x i1> [[CMP_I]] to <8 x i8>
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SEXT_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
uint8x8_t test_pmsle_u8x8(int8x8_t a, int8x8_t b) {
|
|
return __riscv_pmsle_u8x8(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pmsleu_u8x8(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
|
|
// RV32-NEXT: [[CMP_I:%.*]] = icmp ule <8 x i8> [[TMP0]], [[TMP1]]
|
|
// RV32-NEXT: [[SEXT_I:%.*]] = sext <8 x i1> [[CMP_I]] to <8 x i8>
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SEXT_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pmsleu_u8x8(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <8 x i8>
|
|
// RV64-NEXT: [[CMP_I:%.*]] = icmp ule <8 x i8> [[TMP0]], [[TMP1]]
|
|
// RV64-NEXT: [[SEXT_I:%.*]] = sext <8 x i1> [[CMP_I]] to <8 x i8>
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SEXT_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
uint8x8_t test_pmsleu_u8x8(uint8x8_t a, uint8x8_t b) {
|
|
return __riscv_pmsleu_u8x8(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pmseq_i16x4_u16x4(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[CMP_I:%.*]] = icmp eq <4 x i16> [[TMP0]], [[TMP1]]
|
|
// RV32-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i16>
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SEXT_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pmseq_i16x4_u16x4(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[CMP_I:%.*]] = icmp eq <4 x i16> [[TMP0]], [[TMP1]]
|
|
// RV64-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i16>
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SEXT_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
uint16x4_t test_pmseq_i16x4_u16x4(int16x4_t a, int16x4_t b) {
|
|
return __riscv_pmseq_i16x4_u16x4(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pmseq_u16x4_u16x4(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[CMP_I:%.*]] = icmp eq <4 x i16> [[TMP0]], [[TMP1]]
|
|
// RV32-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i16>
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SEXT_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pmseq_u16x4_u16x4(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[CMP_I:%.*]] = icmp eq <4 x i16> [[TMP0]], [[TMP1]]
|
|
// RV64-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i16>
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SEXT_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
uint16x4_t test_pmseq_u16x4_u16x4(uint16x4_t a, uint16x4_t b) {
|
|
return __riscv_pmseq_u16x4_u16x4(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pmsne_i16x4_u16x4(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[CMP_I:%.*]] = icmp ne <4 x i16> [[TMP0]], [[TMP1]]
|
|
// RV32-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i16>
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SEXT_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pmsne_i16x4_u16x4(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[CMP_I:%.*]] = icmp ne <4 x i16> [[TMP0]], [[TMP1]]
|
|
// RV64-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i16>
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SEXT_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
uint16x4_t test_pmsne_i16x4_u16x4(int16x4_t a, int16x4_t b) {
|
|
return __riscv_pmsne_i16x4_u16x4(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pmsne_u16x4_u16x4(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[CMP_I:%.*]] = icmp ne <4 x i16> [[TMP0]], [[TMP1]]
|
|
// RV32-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i16>
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SEXT_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pmsne_u16x4_u16x4(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[CMP_I:%.*]] = icmp ne <4 x i16> [[TMP0]], [[TMP1]]
|
|
// RV64-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i16>
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SEXT_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
uint16x4_t test_pmsne_u16x4_u16x4(uint16x4_t a, uint16x4_t b) {
|
|
return __riscv_pmsne_u16x4_u16x4(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pmslt_u16x4(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[CMP_I:%.*]] = icmp slt <4 x i16> [[TMP0]], [[TMP1]]
|
|
// RV32-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i16>
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SEXT_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pmslt_u16x4(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[CMP_I:%.*]] = icmp slt <4 x i16> [[TMP0]], [[TMP1]]
|
|
// RV64-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i16>
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SEXT_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
uint16x4_t test_pmslt_u16x4(int16x4_t a, int16x4_t b) {
|
|
return __riscv_pmslt_u16x4(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pmsltu_u16x4(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[CMP_I:%.*]] = icmp ult <4 x i16> [[TMP0]], [[TMP1]]
|
|
// RV32-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i16>
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SEXT_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pmsltu_u16x4(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[CMP_I:%.*]] = icmp ult <4 x i16> [[TMP0]], [[TMP1]]
|
|
// RV64-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i16>
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SEXT_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
uint16x4_t test_pmsltu_u16x4(uint16x4_t a, uint16x4_t b) {
|
|
return __riscv_pmsltu_u16x4(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pmsgt_u16x4(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[CMP_I:%.*]] = icmp sgt <4 x i16> [[TMP0]], [[TMP1]]
|
|
// RV32-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i16>
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SEXT_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pmsgt_u16x4(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[CMP_I:%.*]] = icmp sgt <4 x i16> [[TMP0]], [[TMP1]]
|
|
// RV64-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i16>
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SEXT_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
uint16x4_t test_pmsgt_u16x4(int16x4_t a, int16x4_t b) {
|
|
return __riscv_pmsgt_u16x4(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pmsgtu_u16x4(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[CMP_I:%.*]] = icmp ugt <4 x i16> [[TMP0]], [[TMP1]]
|
|
// RV32-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i16>
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SEXT_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pmsgtu_u16x4(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[CMP_I:%.*]] = icmp ugt <4 x i16> [[TMP0]], [[TMP1]]
|
|
// RV64-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i16>
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SEXT_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
uint16x4_t test_pmsgtu_u16x4(uint16x4_t a, uint16x4_t b) {
|
|
return __riscv_pmsgtu_u16x4(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pmsge_u16x4(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[CMP_I:%.*]] = icmp sge <4 x i16> [[TMP0]], [[TMP1]]
|
|
// RV32-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i16>
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SEXT_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pmsge_u16x4(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[CMP_I:%.*]] = icmp sge <4 x i16> [[TMP0]], [[TMP1]]
|
|
// RV64-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i16>
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SEXT_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
uint16x4_t test_pmsge_u16x4(int16x4_t a, int16x4_t b) {
|
|
return __riscv_pmsge_u16x4(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pmsgeu_u16x4(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[CMP_I:%.*]] = icmp uge <4 x i16> [[TMP0]], [[TMP1]]
|
|
// RV32-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i16>
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SEXT_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pmsgeu_u16x4(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[CMP_I:%.*]] = icmp uge <4 x i16> [[TMP0]], [[TMP1]]
|
|
// RV64-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i16>
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SEXT_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
uint16x4_t test_pmsgeu_u16x4(uint16x4_t a, uint16x4_t b) {
|
|
return __riscv_pmsgeu_u16x4(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pmsle_u16x4(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[CMP_I:%.*]] = icmp sle <4 x i16> [[TMP0]], [[TMP1]]
|
|
// RV32-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i16>
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SEXT_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pmsle_u16x4(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[CMP_I:%.*]] = icmp sle <4 x i16> [[TMP0]], [[TMP1]]
|
|
// RV64-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i16>
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SEXT_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
uint16x4_t test_pmsle_u16x4(int16x4_t a, int16x4_t b) {
|
|
return __riscv_pmsle_u16x4(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pmsleu_u16x4(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[CMP_I:%.*]] = icmp ule <4 x i16> [[TMP0]], [[TMP1]]
|
|
// RV32-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i16>
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SEXT_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pmsleu_u16x4(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[CMP_I:%.*]] = icmp ule <4 x i16> [[TMP0]], [[TMP1]]
|
|
// RV64-NEXT: [[SEXT_I:%.*]] = sext <4 x i1> [[CMP_I]] to <4 x i16>
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SEXT_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
uint16x4_t test_pmsleu_u16x4(uint16x4_t a, uint16x4_t b) {
|
|
return __riscv_pmsleu_u16x4(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pmseq_i32x2_u32x2(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
|
|
// RV32-NEXT: [[CMP_I:%.*]] = icmp eq <2 x i32> [[TMP0]], [[TMP1]]
|
|
// RV32-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i32>
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[SEXT_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pmseq_i32x2_u32x2(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
|
|
// RV64-NEXT: [[CMP_I:%.*]] = icmp eq <2 x i32> [[TMP0]], [[TMP1]]
|
|
// RV64-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i32>
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[SEXT_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
uint32x2_t test_pmseq_i32x2_u32x2(int32x2_t a, int32x2_t b) {
|
|
return __riscv_pmseq_i32x2_u32x2(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pmseq_u32x2_u32x2(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
|
|
// RV32-NEXT: [[CMP_I:%.*]] = icmp eq <2 x i32> [[TMP0]], [[TMP1]]
|
|
// RV32-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i32>
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[SEXT_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pmseq_u32x2_u32x2(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
|
|
// RV64-NEXT: [[CMP_I:%.*]] = icmp eq <2 x i32> [[TMP0]], [[TMP1]]
|
|
// RV64-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i32>
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[SEXT_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
uint32x2_t test_pmseq_u32x2_u32x2(uint32x2_t a, uint32x2_t b) {
|
|
return __riscv_pmseq_u32x2_u32x2(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pmsne_i32x2_u32x2(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
|
|
// RV32-NEXT: [[CMP_I:%.*]] = icmp ne <2 x i32> [[TMP0]], [[TMP1]]
|
|
// RV32-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i32>
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[SEXT_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pmsne_i32x2_u32x2(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
|
|
// RV64-NEXT: [[CMP_I:%.*]] = icmp ne <2 x i32> [[TMP0]], [[TMP1]]
|
|
// RV64-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i32>
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[SEXT_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
uint32x2_t test_pmsne_i32x2_u32x2(int32x2_t a, int32x2_t b) {
|
|
return __riscv_pmsne_i32x2_u32x2(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pmsne_u32x2_u32x2(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
|
|
// RV32-NEXT: [[CMP_I:%.*]] = icmp ne <2 x i32> [[TMP0]], [[TMP1]]
|
|
// RV32-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i32>
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[SEXT_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pmsne_u32x2_u32x2(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
|
|
// RV64-NEXT: [[CMP_I:%.*]] = icmp ne <2 x i32> [[TMP0]], [[TMP1]]
|
|
// RV64-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i32>
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[SEXT_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
uint32x2_t test_pmsne_u32x2_u32x2(uint32x2_t a, uint32x2_t b) {
|
|
return __riscv_pmsne_u32x2_u32x2(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pmslt_u32x2(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
|
|
// RV32-NEXT: [[CMP_I:%.*]] = icmp slt <2 x i32> [[TMP0]], [[TMP1]]
|
|
// RV32-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i32>
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[SEXT_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pmslt_u32x2(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
|
|
// RV64-NEXT: [[CMP_I:%.*]] = icmp slt <2 x i32> [[TMP0]], [[TMP1]]
|
|
// RV64-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i32>
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[SEXT_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
uint32x2_t test_pmslt_u32x2(int32x2_t a, int32x2_t b) {
|
|
return __riscv_pmslt_u32x2(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pmsltu_u32x2(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
|
|
// RV32-NEXT: [[CMP_I:%.*]] = icmp ult <2 x i32> [[TMP0]], [[TMP1]]
|
|
// RV32-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i32>
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[SEXT_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pmsltu_u32x2(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
|
|
// RV64-NEXT: [[CMP_I:%.*]] = icmp ult <2 x i32> [[TMP0]], [[TMP1]]
|
|
// RV64-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i32>
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[SEXT_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
uint32x2_t test_pmsltu_u32x2(uint32x2_t a, uint32x2_t b) {
|
|
return __riscv_pmsltu_u32x2(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pmsgt_u32x2(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
|
|
// RV32-NEXT: [[CMP_I:%.*]] = icmp sgt <2 x i32> [[TMP0]], [[TMP1]]
|
|
// RV32-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i32>
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[SEXT_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pmsgt_u32x2(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
|
|
// RV64-NEXT: [[CMP_I:%.*]] = icmp sgt <2 x i32> [[TMP0]], [[TMP1]]
|
|
// RV64-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i32>
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[SEXT_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
uint32x2_t test_pmsgt_u32x2(int32x2_t a, int32x2_t b) {
|
|
return __riscv_pmsgt_u32x2(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pmsgtu_u32x2(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
|
|
// RV32-NEXT: [[CMP_I:%.*]] = icmp ugt <2 x i32> [[TMP0]], [[TMP1]]
|
|
// RV32-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i32>
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[SEXT_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pmsgtu_u32x2(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
|
|
// RV64-NEXT: [[CMP_I:%.*]] = icmp ugt <2 x i32> [[TMP0]], [[TMP1]]
|
|
// RV64-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i32>
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[SEXT_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
uint32x2_t test_pmsgtu_u32x2(uint32x2_t a, uint32x2_t b) {
|
|
return __riscv_pmsgtu_u32x2(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pmsge_u32x2(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
|
|
// RV32-NEXT: [[CMP_I:%.*]] = icmp sge <2 x i32> [[TMP0]], [[TMP1]]
|
|
// RV32-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i32>
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[SEXT_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pmsge_u32x2(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
|
|
// RV64-NEXT: [[CMP_I:%.*]] = icmp sge <2 x i32> [[TMP0]], [[TMP1]]
|
|
// RV64-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i32>
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[SEXT_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
uint32x2_t test_pmsge_u32x2(int32x2_t a, int32x2_t b) {
|
|
return __riscv_pmsge_u32x2(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pmsgeu_u32x2(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
|
|
// RV32-NEXT: [[CMP_I:%.*]] = icmp uge <2 x i32> [[TMP0]], [[TMP1]]
|
|
// RV32-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i32>
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[SEXT_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pmsgeu_u32x2(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
|
|
// RV64-NEXT: [[CMP_I:%.*]] = icmp uge <2 x i32> [[TMP0]], [[TMP1]]
|
|
// RV64-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i32>
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[SEXT_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
uint32x2_t test_pmsgeu_u32x2(uint32x2_t a, uint32x2_t b) {
|
|
return __riscv_pmsgeu_u32x2(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pmsle_u32x2(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
|
|
// RV32-NEXT: [[CMP_I:%.*]] = icmp sle <2 x i32> [[TMP0]], [[TMP1]]
|
|
// RV32-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i32>
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[SEXT_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pmsle_u32x2(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
|
|
// RV64-NEXT: [[CMP_I:%.*]] = icmp sle <2 x i32> [[TMP0]], [[TMP1]]
|
|
// RV64-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i32>
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[SEXT_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
uint32x2_t test_pmsle_u32x2(int32x2_t a, int32x2_t b) {
|
|
return __riscv_pmsle_u32x2(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pmsleu_u32x2(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
|
|
// RV32-NEXT: [[CMP_I:%.*]] = icmp ule <2 x i32> [[TMP0]], [[TMP1]]
|
|
// RV32-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i32>
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[SEXT_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pmsleu_u32x2(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <2 x i32>
|
|
// RV64-NEXT: [[CMP_I:%.*]] = icmp ule <2 x i32> [[TMP0]], [[TMP1]]
|
|
// RV64-NEXT: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i32>
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[SEXT_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
uint32x2_t test_pmsleu_u32x2(uint32x2_t a, uint32x2_t b) {
|
|
return __riscv_pmsleu_u32x2(a, b);
|
|
}
|
|
|
|
|
|
/* Packed Shifts (32-bit) */
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_psll_s_i8x4(
|
|
// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[SHAMT:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
|
|
// RV32-NEXT: [[TMP1:%.*]] = trunc i32 [[SHAMT]] to i8
|
|
// RV32-NEXT: [[TMP2:%.*]] = and i8 [[TMP1]], 7
|
|
// RV32-NEXT: [[TMP3:%.*]] = insertelement <4 x i8> poison, i8 [[TMP2]], i64 0
|
|
// RV32-NEXT: [[SH_PROM_I:%.*]] = shufflevector <4 x i8> [[TMP3]], <4 x i8> poison, <4 x i32> zeroinitializer
|
|
// RV32-NEXT: [[SHL_I:%.*]] = shl <4 x i8> [[TMP0]], [[SH_PROM_I]]
|
|
// RV32-NEXT: [[TMP4:%.*]] = bitcast <4 x i8> [[SHL_I]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP4]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_psll_s_i8x4(
|
|
// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef signext [[SHAMT:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
|
|
// RV64-NEXT: [[TMP1:%.*]] = trunc i32 [[SHAMT]] to i8
|
|
// RV64-NEXT: [[TMP2:%.*]] = and i8 [[TMP1]], 7
|
|
// RV64-NEXT: [[TMP3:%.*]] = insertelement <4 x i8> poison, i8 [[TMP2]], i64 0
|
|
// RV64-NEXT: [[SH_PROM_I:%.*]] = shufflevector <4 x i8> [[TMP3]], <4 x i8> poison, <4 x i32> zeroinitializer
|
|
// RV64-NEXT: [[SHL_I:%.*]] = shl <4 x i8> [[TMP0]], [[SH_PROM_I]]
|
|
// RV64-NEXT: [[TMP4:%.*]] = bitcast <4 x i8> [[SHL_I]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP4]]
|
|
//
|
|
int8x4_t test_psll_s_i8x4(int8x4_t a, unsigned shamt) {
|
|
return __riscv_psll_s_i8x4(a, shamt);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_psll_s_u8x4(
|
|
// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[SHAMT:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
|
|
// RV32-NEXT: [[TMP1:%.*]] = trunc i32 [[SHAMT]] to i8
|
|
// RV32-NEXT: [[TMP2:%.*]] = and i8 [[TMP1]], 7
|
|
// RV32-NEXT: [[TMP3:%.*]] = insertelement <4 x i8> poison, i8 [[TMP2]], i64 0
|
|
// RV32-NEXT: [[SH_PROM_I:%.*]] = shufflevector <4 x i8> [[TMP3]], <4 x i8> poison, <4 x i32> zeroinitializer
|
|
// RV32-NEXT: [[SHL_I:%.*]] = shl <4 x i8> [[TMP0]], [[SH_PROM_I]]
|
|
// RV32-NEXT: [[TMP4:%.*]] = bitcast <4 x i8> [[SHL_I]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP4]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_psll_s_u8x4(
|
|
// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef signext [[SHAMT:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
|
|
// RV64-NEXT: [[TMP1:%.*]] = trunc i32 [[SHAMT]] to i8
|
|
// RV64-NEXT: [[TMP2:%.*]] = and i8 [[TMP1]], 7
|
|
// RV64-NEXT: [[TMP3:%.*]] = insertelement <4 x i8> poison, i8 [[TMP2]], i64 0
|
|
// RV64-NEXT: [[SH_PROM_I:%.*]] = shufflevector <4 x i8> [[TMP3]], <4 x i8> poison, <4 x i32> zeroinitializer
|
|
// RV64-NEXT: [[SHL_I:%.*]] = shl <4 x i8> [[TMP0]], [[SH_PROM_I]]
|
|
// RV64-NEXT: [[TMP4:%.*]] = bitcast <4 x i8> [[SHL_I]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP4]]
|
|
//
|
|
uint8x4_t test_psll_s_u8x4(uint8x4_t a, unsigned shamt) {
|
|
return __riscv_psll_s_u8x4(a, shamt);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_psll_s_i16x2(
|
|
// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[SHAMT:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
|
|
// RV32-NEXT: [[TMP1:%.*]] = trunc i32 [[SHAMT]] to i16
|
|
// RV32-NEXT: [[TMP2:%.*]] = and i16 [[TMP1]], 15
|
|
// RV32-NEXT: [[TMP3:%.*]] = insertelement <2 x i16> poison, i16 [[TMP2]], i64 0
|
|
// RV32-NEXT: [[SH_PROM_I:%.*]] = shufflevector <2 x i16> [[TMP3]], <2 x i16> poison, <2 x i32> zeroinitializer
|
|
// RV32-NEXT: [[SHL_I:%.*]] = shl <2 x i16> [[TMP0]], [[SH_PROM_I]]
|
|
// RV32-NEXT: [[TMP4:%.*]] = bitcast <2 x i16> [[SHL_I]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP4]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_psll_s_i16x2(
|
|
// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef signext [[SHAMT:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
|
|
// RV64-NEXT: [[TMP1:%.*]] = trunc i32 [[SHAMT]] to i16
|
|
// RV64-NEXT: [[TMP2:%.*]] = and i16 [[TMP1]], 15
|
|
// RV64-NEXT: [[TMP3:%.*]] = insertelement <2 x i16> poison, i16 [[TMP2]], i64 0
|
|
// RV64-NEXT: [[SH_PROM_I:%.*]] = shufflevector <2 x i16> [[TMP3]], <2 x i16> poison, <2 x i32> zeroinitializer
|
|
// RV64-NEXT: [[SHL_I:%.*]] = shl <2 x i16> [[TMP0]], [[SH_PROM_I]]
|
|
// RV64-NEXT: [[TMP4:%.*]] = bitcast <2 x i16> [[SHL_I]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP4]]
|
|
//
|
|
int16x2_t test_psll_s_i16x2(int16x2_t a, unsigned shamt) {
|
|
return __riscv_psll_s_i16x2(a, shamt);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_psll_s_u16x2(
|
|
// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[SHAMT:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
|
|
// RV32-NEXT: [[TMP1:%.*]] = trunc i32 [[SHAMT]] to i16
|
|
// RV32-NEXT: [[TMP2:%.*]] = and i16 [[TMP1]], 15
|
|
// RV32-NEXT: [[TMP3:%.*]] = insertelement <2 x i16> poison, i16 [[TMP2]], i64 0
|
|
// RV32-NEXT: [[SH_PROM_I:%.*]] = shufflevector <2 x i16> [[TMP3]], <2 x i16> poison, <2 x i32> zeroinitializer
|
|
// RV32-NEXT: [[SHL_I:%.*]] = shl <2 x i16> [[TMP0]], [[SH_PROM_I]]
|
|
// RV32-NEXT: [[TMP4:%.*]] = bitcast <2 x i16> [[SHL_I]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP4]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_psll_s_u16x2(
|
|
// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef signext [[SHAMT:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
|
|
// RV64-NEXT: [[TMP1:%.*]] = trunc i32 [[SHAMT]] to i16
|
|
// RV64-NEXT: [[TMP2:%.*]] = and i16 [[TMP1]], 15
|
|
// RV64-NEXT: [[TMP3:%.*]] = insertelement <2 x i16> poison, i16 [[TMP2]], i64 0
|
|
// RV64-NEXT: [[SH_PROM_I:%.*]] = shufflevector <2 x i16> [[TMP3]], <2 x i16> poison, <2 x i32> zeroinitializer
|
|
// RV64-NEXT: [[SHL_I:%.*]] = shl <2 x i16> [[TMP0]], [[SH_PROM_I]]
|
|
// RV64-NEXT: [[TMP4:%.*]] = bitcast <2 x i16> [[SHL_I]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP4]]
|
|
//
|
|
uint16x2_t test_psll_s_u16x2(uint16x2_t a, unsigned shamt) {
|
|
return __riscv_psll_s_u16x2(a, shamt);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_psra_s_i8x4(
|
|
// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[SHAMT:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
|
|
// RV32-NEXT: [[TMP1:%.*]] = trunc i32 [[SHAMT]] to i8
|
|
// RV32-NEXT: [[TMP2:%.*]] = and i8 [[TMP1]], 7
|
|
// RV32-NEXT: [[TMP3:%.*]] = insertelement <4 x i8> poison, i8 [[TMP2]], i64 0
|
|
// RV32-NEXT: [[SH_PROM_I:%.*]] = shufflevector <4 x i8> [[TMP3]], <4 x i8> poison, <4 x i32> zeroinitializer
|
|
// RV32-NEXT: [[SHR_I:%.*]] = ashr <4 x i8> [[TMP0]], [[SH_PROM_I]]
|
|
// RV32-NEXT: [[TMP4:%.*]] = bitcast <4 x i8> [[SHR_I]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP4]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_psra_s_i8x4(
|
|
// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef signext [[SHAMT:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
|
|
// RV64-NEXT: [[TMP1:%.*]] = trunc i32 [[SHAMT]] to i8
|
|
// RV64-NEXT: [[TMP2:%.*]] = and i8 [[TMP1]], 7
|
|
// RV64-NEXT: [[TMP3:%.*]] = insertelement <4 x i8> poison, i8 [[TMP2]], i64 0
|
|
// RV64-NEXT: [[SH_PROM_I:%.*]] = shufflevector <4 x i8> [[TMP3]], <4 x i8> poison, <4 x i32> zeroinitializer
|
|
// RV64-NEXT: [[SHR_I:%.*]] = ashr <4 x i8> [[TMP0]], [[SH_PROM_I]]
|
|
// RV64-NEXT: [[TMP4:%.*]] = bitcast <4 x i8> [[SHR_I]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP4]]
|
|
//
|
|
int8x4_t test_psra_s_i8x4(int8x4_t a, unsigned shamt) {
|
|
return __riscv_psra_s_i8x4(a, shamt);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_psrl_s_u8x4(
|
|
// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[SHAMT:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
|
|
// RV32-NEXT: [[TMP1:%.*]] = trunc i32 [[SHAMT]] to i8
|
|
// RV32-NEXT: [[TMP2:%.*]] = and i8 [[TMP1]], 7
|
|
// RV32-NEXT: [[TMP3:%.*]] = insertelement <4 x i8> poison, i8 [[TMP2]], i64 0
|
|
// RV32-NEXT: [[SH_PROM_I:%.*]] = shufflevector <4 x i8> [[TMP3]], <4 x i8> poison, <4 x i32> zeroinitializer
|
|
// RV32-NEXT: [[SHR_I:%.*]] = lshr <4 x i8> [[TMP0]], [[SH_PROM_I]]
|
|
// RV32-NEXT: [[TMP4:%.*]] = bitcast <4 x i8> [[SHR_I]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP4]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_psrl_s_u8x4(
|
|
// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef signext [[SHAMT:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
|
|
// RV64-NEXT: [[TMP1:%.*]] = trunc i32 [[SHAMT]] to i8
|
|
// RV64-NEXT: [[TMP2:%.*]] = and i8 [[TMP1]], 7
|
|
// RV64-NEXT: [[TMP3:%.*]] = insertelement <4 x i8> poison, i8 [[TMP2]], i64 0
|
|
// RV64-NEXT: [[SH_PROM_I:%.*]] = shufflevector <4 x i8> [[TMP3]], <4 x i8> poison, <4 x i32> zeroinitializer
|
|
// RV64-NEXT: [[SHR_I:%.*]] = lshr <4 x i8> [[TMP0]], [[SH_PROM_I]]
|
|
// RV64-NEXT: [[TMP4:%.*]] = bitcast <4 x i8> [[SHR_I]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP4]]
|
|
//
|
|
uint8x4_t test_psrl_s_u8x4(uint8x4_t a, unsigned shamt) {
|
|
return __riscv_psrl_s_u8x4(a, shamt);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_psra_s_i16x2(
|
|
// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[SHAMT:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
|
|
// RV32-NEXT: [[TMP1:%.*]] = trunc i32 [[SHAMT]] to i16
|
|
// RV32-NEXT: [[TMP2:%.*]] = and i16 [[TMP1]], 15
|
|
// RV32-NEXT: [[TMP3:%.*]] = insertelement <2 x i16> poison, i16 [[TMP2]], i64 0
|
|
// RV32-NEXT: [[SH_PROM_I:%.*]] = shufflevector <2 x i16> [[TMP3]], <2 x i16> poison, <2 x i32> zeroinitializer
|
|
// RV32-NEXT: [[SHR_I:%.*]] = ashr <2 x i16> [[TMP0]], [[SH_PROM_I]]
|
|
// RV32-NEXT: [[TMP4:%.*]] = bitcast <2 x i16> [[SHR_I]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP4]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_psra_s_i16x2(
|
|
// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef signext [[SHAMT:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
|
|
// RV64-NEXT: [[TMP1:%.*]] = trunc i32 [[SHAMT]] to i16
|
|
// RV64-NEXT: [[TMP2:%.*]] = and i16 [[TMP1]], 15
|
|
// RV64-NEXT: [[TMP3:%.*]] = insertelement <2 x i16> poison, i16 [[TMP2]], i64 0
|
|
// RV64-NEXT: [[SH_PROM_I:%.*]] = shufflevector <2 x i16> [[TMP3]], <2 x i16> poison, <2 x i32> zeroinitializer
|
|
// RV64-NEXT: [[SHR_I:%.*]] = ashr <2 x i16> [[TMP0]], [[SH_PROM_I]]
|
|
// RV64-NEXT: [[TMP4:%.*]] = bitcast <2 x i16> [[SHR_I]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP4]]
|
|
//
|
|
int16x2_t test_psra_s_i16x2(int16x2_t a, unsigned shamt) {
|
|
return __riscv_psra_s_i16x2(a, shamt);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_psrl_s_u16x2(
|
|
// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[SHAMT:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
|
|
// RV32-NEXT: [[TMP1:%.*]] = trunc i32 [[SHAMT]] to i16
|
|
// RV32-NEXT: [[TMP2:%.*]] = and i16 [[TMP1]], 15
|
|
// RV32-NEXT: [[TMP3:%.*]] = insertelement <2 x i16> poison, i16 [[TMP2]], i64 0
|
|
// RV32-NEXT: [[SH_PROM_I:%.*]] = shufflevector <2 x i16> [[TMP3]], <2 x i16> poison, <2 x i32> zeroinitializer
|
|
// RV32-NEXT: [[SHR_I:%.*]] = lshr <2 x i16> [[TMP0]], [[SH_PROM_I]]
|
|
// RV32-NEXT: [[TMP4:%.*]] = bitcast <2 x i16> [[SHR_I]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP4]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_psrl_s_u16x2(
|
|
// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef signext [[SHAMT:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
|
|
// RV64-NEXT: [[TMP1:%.*]] = trunc i32 [[SHAMT]] to i16
|
|
// RV64-NEXT: [[TMP2:%.*]] = and i16 [[TMP1]], 15
|
|
// RV64-NEXT: [[TMP3:%.*]] = insertelement <2 x i16> poison, i16 [[TMP2]], i64 0
|
|
// RV64-NEXT: [[SH_PROM_I:%.*]] = shufflevector <2 x i16> [[TMP3]], <2 x i16> poison, <2 x i32> zeroinitializer
|
|
// RV64-NEXT: [[SHR_I:%.*]] = lshr <2 x i16> [[TMP0]], [[SH_PROM_I]]
|
|
// RV64-NEXT: [[TMP4:%.*]] = bitcast <2 x i16> [[SHR_I]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP4]]
|
|
//
|
|
uint16x2_t test_psrl_s_u16x2(uint16x2_t a, unsigned shamt) {
|
|
return __riscv_psrl_s_u16x2(a, shamt);
|
|
}
|
|
|
|
/* Packed Shifts (64-bit) */
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_psll_s_i8x8(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i32 noundef [[SHAMT:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
|
|
// RV32-NEXT: [[TMP1:%.*]] = trunc i32 [[SHAMT]] to i8
|
|
// RV32-NEXT: [[TMP2:%.*]] = and i8 [[TMP1]], 7
|
|
// RV32-NEXT: [[TMP3:%.*]] = insertelement <8 x i8> poison, i8 [[TMP2]], i64 0
|
|
// RV32-NEXT: [[SH_PROM_I:%.*]] = shufflevector <8 x i8> [[TMP3]], <8 x i8> poison, <8 x i32> zeroinitializer
|
|
// RV32-NEXT: [[SHL_I:%.*]] = shl <8 x i8> [[TMP0]], [[SH_PROM_I]]
|
|
// RV32-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[SHL_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP4]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_psll_s_i8x8(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i32 noundef signext [[SHAMT:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
|
|
// RV64-NEXT: [[TMP1:%.*]] = trunc i32 [[SHAMT]] to i8
|
|
// RV64-NEXT: [[TMP2:%.*]] = and i8 [[TMP1]], 7
|
|
// RV64-NEXT: [[TMP3:%.*]] = insertelement <8 x i8> poison, i8 [[TMP2]], i64 0
|
|
// RV64-NEXT: [[SH_PROM_I:%.*]] = shufflevector <8 x i8> [[TMP3]], <8 x i8> poison, <8 x i32> zeroinitializer
|
|
// RV64-NEXT: [[SHL_I:%.*]] = shl <8 x i8> [[TMP0]], [[SH_PROM_I]]
|
|
// RV64-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[SHL_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP4]]
|
|
//
|
|
int8x8_t test_psll_s_i8x8(int8x8_t a, unsigned shamt) {
|
|
return __riscv_psll_s_i8x8(a, shamt);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_psll_s_u8x8(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i32 noundef [[SHAMT:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
|
|
// RV32-NEXT: [[TMP1:%.*]] = trunc i32 [[SHAMT]] to i8
|
|
// RV32-NEXT: [[TMP2:%.*]] = and i8 [[TMP1]], 7
|
|
// RV32-NEXT: [[TMP3:%.*]] = insertelement <8 x i8> poison, i8 [[TMP2]], i64 0
|
|
// RV32-NEXT: [[SH_PROM_I:%.*]] = shufflevector <8 x i8> [[TMP3]], <8 x i8> poison, <8 x i32> zeroinitializer
|
|
// RV32-NEXT: [[SHL_I:%.*]] = shl <8 x i8> [[TMP0]], [[SH_PROM_I]]
|
|
// RV32-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[SHL_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP4]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_psll_s_u8x8(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i32 noundef signext [[SHAMT:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
|
|
// RV64-NEXT: [[TMP1:%.*]] = trunc i32 [[SHAMT]] to i8
|
|
// RV64-NEXT: [[TMP2:%.*]] = and i8 [[TMP1]], 7
|
|
// RV64-NEXT: [[TMP3:%.*]] = insertelement <8 x i8> poison, i8 [[TMP2]], i64 0
|
|
// RV64-NEXT: [[SH_PROM_I:%.*]] = shufflevector <8 x i8> [[TMP3]], <8 x i8> poison, <8 x i32> zeroinitializer
|
|
// RV64-NEXT: [[SHL_I:%.*]] = shl <8 x i8> [[TMP0]], [[SH_PROM_I]]
|
|
// RV64-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[SHL_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP4]]
|
|
//
|
|
uint8x8_t test_psll_s_u8x8(uint8x8_t a, unsigned shamt) {
|
|
return __riscv_psll_s_u8x8(a, shamt);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_psll_s_i16x4(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i32 noundef [[SHAMT:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[TMP1:%.*]] = trunc i32 [[SHAMT]] to i16
|
|
// RV32-NEXT: [[TMP2:%.*]] = and i16 [[TMP1]], 15
|
|
// RV32-NEXT: [[TMP3:%.*]] = insertelement <4 x i16> poison, i16 [[TMP2]], i64 0
|
|
// RV32-NEXT: [[SH_PROM_I:%.*]] = shufflevector <4 x i16> [[TMP3]], <4 x i16> poison, <4 x i32> zeroinitializer
|
|
// RV32-NEXT: [[SHL_I:%.*]] = shl <4 x i16> [[TMP0]], [[SH_PROM_I]]
|
|
// RV32-NEXT: [[TMP4:%.*]] = bitcast <4 x i16> [[SHL_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP4]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_psll_s_i16x4(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i32 noundef signext [[SHAMT:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[TMP1:%.*]] = trunc i32 [[SHAMT]] to i16
|
|
// RV64-NEXT: [[TMP2:%.*]] = and i16 [[TMP1]], 15
|
|
// RV64-NEXT: [[TMP3:%.*]] = insertelement <4 x i16> poison, i16 [[TMP2]], i64 0
|
|
// RV64-NEXT: [[SH_PROM_I:%.*]] = shufflevector <4 x i16> [[TMP3]], <4 x i16> poison, <4 x i32> zeroinitializer
|
|
// RV64-NEXT: [[SHL_I:%.*]] = shl <4 x i16> [[TMP0]], [[SH_PROM_I]]
|
|
// RV64-NEXT: [[TMP4:%.*]] = bitcast <4 x i16> [[SHL_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP4]]
|
|
//
|
|
int16x4_t test_psll_s_i16x4(int16x4_t a, unsigned shamt) {
|
|
return __riscv_psll_s_i16x4(a, shamt);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_psll_s_u16x4(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i32 noundef [[SHAMT:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[TMP1:%.*]] = trunc i32 [[SHAMT]] to i16
|
|
// RV32-NEXT: [[TMP2:%.*]] = and i16 [[TMP1]], 15
|
|
// RV32-NEXT: [[TMP3:%.*]] = insertelement <4 x i16> poison, i16 [[TMP2]], i64 0
|
|
// RV32-NEXT: [[SH_PROM_I:%.*]] = shufflevector <4 x i16> [[TMP3]], <4 x i16> poison, <4 x i32> zeroinitializer
|
|
// RV32-NEXT: [[SHL_I:%.*]] = shl <4 x i16> [[TMP0]], [[SH_PROM_I]]
|
|
// RV32-NEXT: [[TMP4:%.*]] = bitcast <4 x i16> [[SHL_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP4]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_psll_s_u16x4(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i32 noundef signext [[SHAMT:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[TMP1:%.*]] = trunc i32 [[SHAMT]] to i16
|
|
// RV64-NEXT: [[TMP2:%.*]] = and i16 [[TMP1]], 15
|
|
// RV64-NEXT: [[TMP3:%.*]] = insertelement <4 x i16> poison, i16 [[TMP2]], i64 0
|
|
// RV64-NEXT: [[SH_PROM_I:%.*]] = shufflevector <4 x i16> [[TMP3]], <4 x i16> poison, <4 x i32> zeroinitializer
|
|
// RV64-NEXT: [[SHL_I:%.*]] = shl <4 x i16> [[TMP0]], [[SH_PROM_I]]
|
|
// RV64-NEXT: [[TMP4:%.*]] = bitcast <4 x i16> [[SHL_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP4]]
|
|
//
|
|
uint16x4_t test_psll_s_u16x4(uint16x4_t a, unsigned shamt) {
|
|
return __riscv_psll_s_u16x4(a, shamt);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_psll_s_i32x2(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i32 noundef [[SHAMT:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
|
|
// RV32-NEXT: [[AND_I:%.*]] = and i32 [[SHAMT]], 31
|
|
// RV32-NEXT: [[SPLAT_SPLATINSERT_I:%.*]] = insertelement <2 x i32> poison, i32 [[AND_I]], i64 0
|
|
// RV32-NEXT: [[SPLAT_SPLAT_I:%.*]] = shufflevector <2 x i32> [[SPLAT_SPLATINSERT_I]], <2 x i32> poison, <2 x i32> zeroinitializer
|
|
// RV32-NEXT: [[SHL_I:%.*]] = shl <2 x i32> [[TMP0]], [[SPLAT_SPLAT_I]]
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[SHL_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP1]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_psll_s_i32x2(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i32 noundef signext [[SHAMT:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
|
|
// RV64-NEXT: [[AND_I:%.*]] = and i32 [[SHAMT]], 31
|
|
// RV64-NEXT: [[SPLAT_SPLATINSERT_I:%.*]] = insertelement <2 x i32> poison, i32 [[AND_I]], i64 0
|
|
// RV64-NEXT: [[SPLAT_SPLAT_I:%.*]] = shufflevector <2 x i32> [[SPLAT_SPLATINSERT_I]], <2 x i32> poison, <2 x i32> zeroinitializer
|
|
// RV64-NEXT: [[SHL_I:%.*]] = shl <2 x i32> [[TMP0]], [[SPLAT_SPLAT_I]]
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[SHL_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP1]]
|
|
//
|
|
int32x2_t test_psll_s_i32x2(int32x2_t a, unsigned shamt) {
|
|
return __riscv_psll_s_i32x2(a, shamt);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_psll_s_u32x2(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i32 noundef [[SHAMT:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
|
|
// RV32-NEXT: [[AND_I:%.*]] = and i32 [[SHAMT]], 31
|
|
// RV32-NEXT: [[SPLAT_SPLATINSERT_I:%.*]] = insertelement <2 x i32> poison, i32 [[AND_I]], i64 0
|
|
// RV32-NEXT: [[SPLAT_SPLAT_I:%.*]] = shufflevector <2 x i32> [[SPLAT_SPLATINSERT_I]], <2 x i32> poison, <2 x i32> zeroinitializer
|
|
// RV32-NEXT: [[SHL_I:%.*]] = shl <2 x i32> [[TMP0]], [[SPLAT_SPLAT_I]]
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[SHL_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP1]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_psll_s_u32x2(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i32 noundef signext [[SHAMT:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
|
|
// RV64-NEXT: [[AND_I:%.*]] = and i32 [[SHAMT]], 31
|
|
// RV64-NEXT: [[SPLAT_SPLATINSERT_I:%.*]] = insertelement <2 x i32> poison, i32 [[AND_I]], i64 0
|
|
// RV64-NEXT: [[SPLAT_SPLAT_I:%.*]] = shufflevector <2 x i32> [[SPLAT_SPLATINSERT_I]], <2 x i32> poison, <2 x i32> zeroinitializer
|
|
// RV64-NEXT: [[SHL_I:%.*]] = shl <2 x i32> [[TMP0]], [[SPLAT_SPLAT_I]]
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[SHL_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP1]]
|
|
//
|
|
uint32x2_t test_psll_s_u32x2(uint32x2_t a, unsigned shamt) {
|
|
return __riscv_psll_s_u32x2(a, shamt);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_psra_s_i8x8(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i32 noundef [[SHAMT:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
|
|
// RV32-NEXT: [[TMP1:%.*]] = trunc i32 [[SHAMT]] to i8
|
|
// RV32-NEXT: [[TMP2:%.*]] = and i8 [[TMP1]], 7
|
|
// RV32-NEXT: [[TMP3:%.*]] = insertelement <8 x i8> poison, i8 [[TMP2]], i64 0
|
|
// RV32-NEXT: [[SH_PROM_I:%.*]] = shufflevector <8 x i8> [[TMP3]], <8 x i8> poison, <8 x i32> zeroinitializer
|
|
// RV32-NEXT: [[SHR_I:%.*]] = ashr <8 x i8> [[TMP0]], [[SH_PROM_I]]
|
|
// RV32-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[SHR_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP4]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_psra_s_i8x8(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i32 noundef signext [[SHAMT:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
|
|
// RV64-NEXT: [[TMP1:%.*]] = trunc i32 [[SHAMT]] to i8
|
|
// RV64-NEXT: [[TMP2:%.*]] = and i8 [[TMP1]], 7
|
|
// RV64-NEXT: [[TMP3:%.*]] = insertelement <8 x i8> poison, i8 [[TMP2]], i64 0
|
|
// RV64-NEXT: [[SH_PROM_I:%.*]] = shufflevector <8 x i8> [[TMP3]], <8 x i8> poison, <8 x i32> zeroinitializer
|
|
// RV64-NEXT: [[SHR_I:%.*]] = ashr <8 x i8> [[TMP0]], [[SH_PROM_I]]
|
|
// RV64-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[SHR_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP4]]
|
|
//
|
|
int8x8_t test_psra_s_i8x8(int8x8_t a, unsigned shamt) {
|
|
return __riscv_psra_s_i8x8(a, shamt);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_psrl_s_u8x8(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i32 noundef [[SHAMT:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
|
|
// RV32-NEXT: [[TMP1:%.*]] = trunc i32 [[SHAMT]] to i8
|
|
// RV32-NEXT: [[TMP2:%.*]] = and i8 [[TMP1]], 7
|
|
// RV32-NEXT: [[TMP3:%.*]] = insertelement <8 x i8> poison, i8 [[TMP2]], i64 0
|
|
// RV32-NEXT: [[SH_PROM_I:%.*]] = shufflevector <8 x i8> [[TMP3]], <8 x i8> poison, <8 x i32> zeroinitializer
|
|
// RV32-NEXT: [[SHR_I:%.*]] = lshr <8 x i8> [[TMP0]], [[SH_PROM_I]]
|
|
// RV32-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[SHR_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP4]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_psrl_s_u8x8(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i32 noundef signext [[SHAMT:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
|
|
// RV64-NEXT: [[TMP1:%.*]] = trunc i32 [[SHAMT]] to i8
|
|
// RV64-NEXT: [[TMP2:%.*]] = and i8 [[TMP1]], 7
|
|
// RV64-NEXT: [[TMP3:%.*]] = insertelement <8 x i8> poison, i8 [[TMP2]], i64 0
|
|
// RV64-NEXT: [[SH_PROM_I:%.*]] = shufflevector <8 x i8> [[TMP3]], <8 x i8> poison, <8 x i32> zeroinitializer
|
|
// RV64-NEXT: [[SHR_I:%.*]] = lshr <8 x i8> [[TMP0]], [[SH_PROM_I]]
|
|
// RV64-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[SHR_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP4]]
|
|
//
|
|
uint8x8_t test_psrl_s_u8x8(uint8x8_t a, unsigned shamt) {
|
|
return __riscv_psrl_s_u8x8(a, shamt);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_psra_s_i16x4(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i32 noundef [[SHAMT:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[TMP1:%.*]] = trunc i32 [[SHAMT]] to i16
|
|
// RV32-NEXT: [[TMP2:%.*]] = and i16 [[TMP1]], 15
|
|
// RV32-NEXT: [[TMP3:%.*]] = insertelement <4 x i16> poison, i16 [[TMP2]], i64 0
|
|
// RV32-NEXT: [[SH_PROM_I:%.*]] = shufflevector <4 x i16> [[TMP3]], <4 x i16> poison, <4 x i32> zeroinitializer
|
|
// RV32-NEXT: [[SHR_I:%.*]] = ashr <4 x i16> [[TMP0]], [[SH_PROM_I]]
|
|
// RV32-NEXT: [[TMP4:%.*]] = bitcast <4 x i16> [[SHR_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP4]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_psra_s_i16x4(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i32 noundef signext [[SHAMT:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[TMP1:%.*]] = trunc i32 [[SHAMT]] to i16
|
|
// RV64-NEXT: [[TMP2:%.*]] = and i16 [[TMP1]], 15
|
|
// RV64-NEXT: [[TMP3:%.*]] = insertelement <4 x i16> poison, i16 [[TMP2]], i64 0
|
|
// RV64-NEXT: [[SH_PROM_I:%.*]] = shufflevector <4 x i16> [[TMP3]], <4 x i16> poison, <4 x i32> zeroinitializer
|
|
// RV64-NEXT: [[SHR_I:%.*]] = ashr <4 x i16> [[TMP0]], [[SH_PROM_I]]
|
|
// RV64-NEXT: [[TMP4:%.*]] = bitcast <4 x i16> [[SHR_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP4]]
|
|
//
|
|
int16x4_t test_psra_s_i16x4(int16x4_t a, unsigned shamt) {
|
|
return __riscv_psra_s_i16x4(a, shamt);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_psrl_s_u16x4(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i32 noundef [[SHAMT:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[TMP1:%.*]] = trunc i32 [[SHAMT]] to i16
|
|
// RV32-NEXT: [[TMP2:%.*]] = and i16 [[TMP1]], 15
|
|
// RV32-NEXT: [[TMP3:%.*]] = insertelement <4 x i16> poison, i16 [[TMP2]], i64 0
|
|
// RV32-NEXT: [[SH_PROM_I:%.*]] = shufflevector <4 x i16> [[TMP3]], <4 x i16> poison, <4 x i32> zeroinitializer
|
|
// RV32-NEXT: [[SHR_I:%.*]] = lshr <4 x i16> [[TMP0]], [[SH_PROM_I]]
|
|
// RV32-NEXT: [[TMP4:%.*]] = bitcast <4 x i16> [[SHR_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP4]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_psrl_s_u16x4(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i32 noundef signext [[SHAMT:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[TMP1:%.*]] = trunc i32 [[SHAMT]] to i16
|
|
// RV64-NEXT: [[TMP2:%.*]] = and i16 [[TMP1]], 15
|
|
// RV64-NEXT: [[TMP3:%.*]] = insertelement <4 x i16> poison, i16 [[TMP2]], i64 0
|
|
// RV64-NEXT: [[SH_PROM_I:%.*]] = shufflevector <4 x i16> [[TMP3]], <4 x i16> poison, <4 x i32> zeroinitializer
|
|
// RV64-NEXT: [[SHR_I:%.*]] = lshr <4 x i16> [[TMP0]], [[SH_PROM_I]]
|
|
// RV64-NEXT: [[TMP4:%.*]] = bitcast <4 x i16> [[SHR_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP4]]
|
|
//
|
|
uint16x4_t test_psrl_s_u16x4(uint16x4_t a, unsigned shamt) {
|
|
return __riscv_psrl_s_u16x4(a, shamt);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_psra_s_i32x2(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i32 noundef [[SHAMT:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
|
|
// RV32-NEXT: [[AND_I:%.*]] = and i32 [[SHAMT]], 31
|
|
// RV32-NEXT: [[SPLAT_SPLATINSERT_I:%.*]] = insertelement <2 x i32> poison, i32 [[AND_I]], i64 0
|
|
// RV32-NEXT: [[SPLAT_SPLAT_I:%.*]] = shufflevector <2 x i32> [[SPLAT_SPLATINSERT_I]], <2 x i32> poison, <2 x i32> zeroinitializer
|
|
// RV32-NEXT: [[SHR_I:%.*]] = ashr <2 x i32> [[TMP0]], [[SPLAT_SPLAT_I]]
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[SHR_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP1]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_psra_s_i32x2(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i32 noundef signext [[SHAMT:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
|
|
// RV64-NEXT: [[AND_I:%.*]] = and i32 [[SHAMT]], 31
|
|
// RV64-NEXT: [[SPLAT_SPLATINSERT_I:%.*]] = insertelement <2 x i32> poison, i32 [[AND_I]], i64 0
|
|
// RV64-NEXT: [[SPLAT_SPLAT_I:%.*]] = shufflevector <2 x i32> [[SPLAT_SPLATINSERT_I]], <2 x i32> poison, <2 x i32> zeroinitializer
|
|
// RV64-NEXT: [[SHR_I:%.*]] = ashr <2 x i32> [[TMP0]], [[SPLAT_SPLAT_I]]
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[SHR_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP1]]
|
|
//
|
|
int32x2_t test_psra_s_i32x2(int32x2_t a, unsigned shamt) {
|
|
return __riscv_psra_s_i32x2(a, shamt);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_psrl_s_u32x2(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i32 noundef [[SHAMT:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
|
|
// RV32-NEXT: [[AND_I:%.*]] = and i32 [[SHAMT]], 31
|
|
// RV32-NEXT: [[SPLAT_SPLATINSERT_I:%.*]] = insertelement <2 x i32> poison, i32 [[AND_I]], i64 0
|
|
// RV32-NEXT: [[SPLAT_SPLAT_I:%.*]] = shufflevector <2 x i32> [[SPLAT_SPLATINSERT_I]], <2 x i32> poison, <2 x i32> zeroinitializer
|
|
// RV32-NEXT: [[SHR_I:%.*]] = lshr <2 x i32> [[TMP0]], [[SPLAT_SPLAT_I]]
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[SHR_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP1]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_psrl_s_u32x2(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i32 noundef signext [[SHAMT:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
|
|
// RV64-NEXT: [[AND_I:%.*]] = and i32 [[SHAMT]], 31
|
|
// RV64-NEXT: [[SPLAT_SPLATINSERT_I:%.*]] = insertelement <2 x i32> poison, i32 [[AND_I]], i64 0
|
|
// RV64-NEXT: [[SPLAT_SPLAT_I:%.*]] = shufflevector <2 x i32> [[SPLAT_SPLATINSERT_I]], <2 x i32> poison, <2 x i32> zeroinitializer
|
|
// RV64-NEXT: [[SHR_I:%.*]] = lshr <2 x i32> [[TMP0]], [[SPLAT_SPLAT_I]]
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[SHR_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP1]]
|
|
//
|
|
uint32x2_t test_psrl_s_u32x2(uint32x2_t a, unsigned shamt) {
|
|
return __riscv_psrl_s_u32x2(a, shamt);
|
|
}
|
|
|
|
/* Packed Logical Operations (32-bit) */
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_pand_i8x4(
|
|
// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[AND_I1:%.*]] = and i32 [[A_COERCE]], [[B_COERCE]]
|
|
// RV32-NEXT: ret i32 [[AND_I1]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_pand_i8x4(
|
|
// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[AND_I1:%.*]] = and i32 [[A_COERCE]], [[B_COERCE]]
|
|
// RV64-NEXT: ret i32 [[AND_I1]]
|
|
//
|
|
int8x4_t test_pand_i8x4(int8x4_t a, int8x4_t b) {
|
|
return __riscv_pand_i8x4(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_pand_u8x4(
|
|
// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[AND_I1:%.*]] = and i32 [[A_COERCE]], [[B_COERCE]]
|
|
// RV32-NEXT: ret i32 [[AND_I1]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_pand_u8x4(
|
|
// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[AND_I1:%.*]] = and i32 [[A_COERCE]], [[B_COERCE]]
|
|
// RV64-NEXT: ret i32 [[AND_I1]]
|
|
//
|
|
uint8x4_t test_pand_u8x4(uint8x4_t a, uint8x4_t b) {
|
|
return __riscv_pand_u8x4(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_pand_i16x2(
|
|
// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[AND_I1:%.*]] = and i32 [[A_COERCE]], [[B_COERCE]]
|
|
// RV32-NEXT: ret i32 [[AND_I1]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_pand_i16x2(
|
|
// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[AND_I1:%.*]] = and i32 [[A_COERCE]], [[B_COERCE]]
|
|
// RV64-NEXT: ret i32 [[AND_I1]]
|
|
//
|
|
int16x2_t test_pand_i16x2(int16x2_t a, int16x2_t b) {
|
|
return __riscv_pand_i16x2(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_pand_u16x2(
|
|
// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[AND_I1:%.*]] = and i32 [[A_COERCE]], [[B_COERCE]]
|
|
// RV32-NEXT: ret i32 [[AND_I1]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_pand_u16x2(
|
|
// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[AND_I1:%.*]] = and i32 [[A_COERCE]], [[B_COERCE]]
|
|
// RV64-NEXT: ret i32 [[AND_I1]]
|
|
//
|
|
uint16x2_t test_pand_u16x2(uint16x2_t a, uint16x2_t b) {
|
|
return __riscv_pand_u16x2(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_por_i8x4(
|
|
// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[OR_I1:%.*]] = or i32 [[A_COERCE]], [[B_COERCE]]
|
|
// RV32-NEXT: ret i32 [[OR_I1]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_por_i8x4(
|
|
// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[OR_I1:%.*]] = or i32 [[A_COERCE]], [[B_COERCE]]
|
|
// RV64-NEXT: ret i32 [[OR_I1]]
|
|
//
|
|
int8x4_t test_por_i8x4(int8x4_t a, int8x4_t b) {
|
|
return __riscv_por_i8x4(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_por_u8x4(
|
|
// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[OR_I1:%.*]] = or i32 [[A_COERCE]], [[B_COERCE]]
|
|
// RV32-NEXT: ret i32 [[OR_I1]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_por_u8x4(
|
|
// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[OR_I1:%.*]] = or i32 [[A_COERCE]], [[B_COERCE]]
|
|
// RV64-NEXT: ret i32 [[OR_I1]]
|
|
//
|
|
uint8x4_t test_por_u8x4(uint8x4_t a, uint8x4_t b) {
|
|
return __riscv_por_u8x4(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_por_i16x2(
|
|
// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[OR_I1:%.*]] = or i32 [[A_COERCE]], [[B_COERCE]]
|
|
// RV32-NEXT: ret i32 [[OR_I1]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_por_i16x2(
|
|
// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[OR_I1:%.*]] = or i32 [[A_COERCE]], [[B_COERCE]]
|
|
// RV64-NEXT: ret i32 [[OR_I1]]
|
|
//
|
|
int16x2_t test_por_i16x2(int16x2_t a, int16x2_t b) {
|
|
return __riscv_por_i16x2(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_por_u16x2(
|
|
// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[OR_I1:%.*]] = or i32 [[A_COERCE]], [[B_COERCE]]
|
|
// RV32-NEXT: ret i32 [[OR_I1]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_por_u16x2(
|
|
// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[OR_I1:%.*]] = or i32 [[A_COERCE]], [[B_COERCE]]
|
|
// RV64-NEXT: ret i32 [[OR_I1]]
|
|
//
|
|
uint16x2_t test_por_u16x2(uint16x2_t a, uint16x2_t b) {
|
|
return __riscv_por_u16x2(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_pxor_i8x4(
|
|
// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[XOR_I1:%.*]] = xor i32 [[A_COERCE]], [[B_COERCE]]
|
|
// RV32-NEXT: ret i32 [[XOR_I1]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_pxor_i8x4(
|
|
// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[XOR_I1:%.*]] = xor i32 [[A_COERCE]], [[B_COERCE]]
|
|
// RV64-NEXT: ret i32 [[XOR_I1]]
|
|
//
|
|
int8x4_t test_pxor_i8x4(int8x4_t a, int8x4_t b) {
|
|
return __riscv_pxor_i8x4(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_pxor_u8x4(
|
|
// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[XOR_I1:%.*]] = xor i32 [[A_COERCE]], [[B_COERCE]]
|
|
// RV32-NEXT: ret i32 [[XOR_I1]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_pxor_u8x4(
|
|
// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[XOR_I1:%.*]] = xor i32 [[A_COERCE]], [[B_COERCE]]
|
|
// RV64-NEXT: ret i32 [[XOR_I1]]
|
|
//
|
|
uint8x4_t test_pxor_u8x4(uint8x4_t a, uint8x4_t b) {
|
|
return __riscv_pxor_u8x4(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_pxor_i16x2(
|
|
// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[XOR_I1:%.*]] = xor i32 [[A_COERCE]], [[B_COERCE]]
|
|
// RV32-NEXT: ret i32 [[XOR_I1]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_pxor_i16x2(
|
|
// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[XOR_I1:%.*]] = xor i32 [[A_COERCE]], [[B_COERCE]]
|
|
// RV64-NEXT: ret i32 [[XOR_I1]]
|
|
//
|
|
int16x2_t test_pxor_i16x2(int16x2_t a, int16x2_t b) {
|
|
return __riscv_pxor_i16x2(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_pxor_u16x2(
|
|
// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[XOR_I1:%.*]] = xor i32 [[A_COERCE]], [[B_COERCE]]
|
|
// RV32-NEXT: ret i32 [[XOR_I1]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_pxor_u16x2(
|
|
// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[XOR_I1:%.*]] = xor i32 [[A_COERCE]], [[B_COERCE]]
|
|
// RV64-NEXT: ret i32 [[XOR_I1]]
|
|
//
|
|
uint16x2_t test_pxor_u16x2(uint16x2_t a, uint16x2_t b) {
|
|
return __riscv_pxor_u16x2(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_pnot_i8x4(
|
|
// RV32-SAME: i32 noundef [[A_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
|
|
// RV32-NEXT: [[NOT_I:%.*]] = xor <4 x i8> [[TMP0]], splat (i8 -1)
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast <4 x i8> [[NOT_I]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP1]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_pnot_i8x4(
|
|
// RV64-SAME: i32 noundef [[A_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
|
|
// RV64-NEXT: [[NOT_I:%.*]] = xor <4 x i8> [[TMP0]], splat (i8 -1)
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast <4 x i8> [[NOT_I]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP1]]
|
|
//
|
|
int8x4_t test_pnot_i8x4(int8x4_t a) {
|
|
return __riscv_pnot_i8x4(a);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_pnot_u8x4(
|
|
// RV32-SAME: i32 noundef [[A_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
|
|
// RV32-NEXT: [[NOT_I:%.*]] = xor <4 x i8> [[TMP0]], splat (i8 -1)
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast <4 x i8> [[NOT_I]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP1]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_pnot_u8x4(
|
|
// RV64-SAME: i32 noundef [[A_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <4 x i8>
|
|
// RV64-NEXT: [[NOT_I:%.*]] = xor <4 x i8> [[TMP0]], splat (i8 -1)
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast <4 x i8> [[NOT_I]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP1]]
|
|
//
|
|
uint8x4_t test_pnot_u8x4(uint8x4_t a) {
|
|
return __riscv_pnot_u8x4(a);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_pnot_i16x2(
|
|
// RV32-SAME: i32 noundef [[A_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
|
|
// RV32-NEXT: [[NOT_I:%.*]] = xor <2 x i16> [[TMP0]], splat (i16 -1)
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast <2 x i16> [[NOT_I]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP1]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_pnot_i16x2(
|
|
// RV64-SAME: i32 noundef [[A_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
|
|
// RV64-NEXT: [[NOT_I:%.*]] = xor <2 x i16> [[TMP0]], splat (i16 -1)
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast <2 x i16> [[NOT_I]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP1]]
|
|
//
|
|
int16x2_t test_pnot_i16x2(int16x2_t a) {
|
|
return __riscv_pnot_i16x2(a);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_pnot_u16x2(
|
|
// RV32-SAME: i32 noundef [[A_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
|
|
// RV32-NEXT: [[NOT_I:%.*]] = xor <2 x i16> [[TMP0]], splat (i16 -1)
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast <2 x i16> [[NOT_I]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP1]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_pnot_u16x2(
|
|
// RV64-SAME: i32 noundef [[A_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
|
|
// RV64-NEXT: [[NOT_I:%.*]] = xor <2 x i16> [[TMP0]], splat (i16 -1)
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast <2 x i16> [[NOT_I]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP1]]
|
|
//
|
|
uint16x2_t test_pnot_u16x2(uint16x2_t a) {
|
|
return __riscv_pnot_u16x2(a);
|
|
}
|
|
|
|
/* Packed Logical Operations (64-bit) */
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pand_i8x8(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[AND_I1:%.*]] = and i64 [[A_COERCE]], [[B_COERCE]]
|
|
// RV32-NEXT: ret i64 [[AND_I1]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pand_i8x8(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[AND_I1:%.*]] = and i64 [[A_COERCE]], [[B_COERCE]]
|
|
// RV64-NEXT: ret i64 [[AND_I1]]
|
|
//
|
|
int8x8_t test_pand_i8x8(int8x8_t a, int8x8_t b) {
|
|
return __riscv_pand_i8x8(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pand_u8x8(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[AND_I1:%.*]] = and i64 [[A_COERCE]], [[B_COERCE]]
|
|
// RV32-NEXT: ret i64 [[AND_I1]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pand_u8x8(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[AND_I1:%.*]] = and i64 [[A_COERCE]], [[B_COERCE]]
|
|
// RV64-NEXT: ret i64 [[AND_I1]]
|
|
//
|
|
uint8x8_t test_pand_u8x8(uint8x8_t a, uint8x8_t b) {
|
|
return __riscv_pand_u8x8(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pand_i16x4(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[AND_I1:%.*]] = and i64 [[A_COERCE]], [[B_COERCE]]
|
|
// RV32-NEXT: ret i64 [[AND_I1]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pand_i16x4(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[AND_I1:%.*]] = and i64 [[A_COERCE]], [[B_COERCE]]
|
|
// RV64-NEXT: ret i64 [[AND_I1]]
|
|
//
|
|
int16x4_t test_pand_i16x4(int16x4_t a, int16x4_t b) {
|
|
return __riscv_pand_i16x4(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pand_u16x4(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[AND_I1:%.*]] = and i64 [[A_COERCE]], [[B_COERCE]]
|
|
// RV32-NEXT: ret i64 [[AND_I1]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pand_u16x4(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[AND_I1:%.*]] = and i64 [[A_COERCE]], [[B_COERCE]]
|
|
// RV64-NEXT: ret i64 [[AND_I1]]
|
|
//
|
|
uint16x4_t test_pand_u16x4(uint16x4_t a, uint16x4_t b) {
|
|
return __riscv_pand_u16x4(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pand_i32x2(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[AND_I1:%.*]] = and i64 [[A_COERCE]], [[B_COERCE]]
|
|
// RV32-NEXT: ret i64 [[AND_I1]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pand_i32x2(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[AND_I1:%.*]] = and i64 [[A_COERCE]], [[B_COERCE]]
|
|
// RV64-NEXT: ret i64 [[AND_I1]]
|
|
//
|
|
int32x2_t test_pand_i32x2(int32x2_t a, int32x2_t b) {
|
|
return __riscv_pand_i32x2(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pand_u32x2(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[AND_I1:%.*]] = and i64 [[A_COERCE]], [[B_COERCE]]
|
|
// RV32-NEXT: ret i64 [[AND_I1]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pand_u32x2(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[AND_I1:%.*]] = and i64 [[A_COERCE]], [[B_COERCE]]
|
|
// RV64-NEXT: ret i64 [[AND_I1]]
|
|
//
|
|
uint32x2_t test_pand_u32x2(uint32x2_t a, uint32x2_t b) {
|
|
return __riscv_pand_u32x2(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_por_i8x8(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[OR_I1:%.*]] = or i64 [[A_COERCE]], [[B_COERCE]]
|
|
// RV32-NEXT: ret i64 [[OR_I1]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_por_i8x8(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[OR_I1:%.*]] = or i64 [[A_COERCE]], [[B_COERCE]]
|
|
// RV64-NEXT: ret i64 [[OR_I1]]
|
|
//
|
|
int8x8_t test_por_i8x8(int8x8_t a, int8x8_t b) {
|
|
return __riscv_por_i8x8(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_por_u8x8(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[OR_I1:%.*]] = or i64 [[A_COERCE]], [[B_COERCE]]
|
|
// RV32-NEXT: ret i64 [[OR_I1]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_por_u8x8(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[OR_I1:%.*]] = or i64 [[A_COERCE]], [[B_COERCE]]
|
|
// RV64-NEXT: ret i64 [[OR_I1]]
|
|
//
|
|
uint8x8_t test_por_u8x8(uint8x8_t a, uint8x8_t b) {
|
|
return __riscv_por_u8x8(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_por_i16x4(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[OR_I1:%.*]] = or i64 [[A_COERCE]], [[B_COERCE]]
|
|
// RV32-NEXT: ret i64 [[OR_I1]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_por_i16x4(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[OR_I1:%.*]] = or i64 [[A_COERCE]], [[B_COERCE]]
|
|
// RV64-NEXT: ret i64 [[OR_I1]]
|
|
//
|
|
int16x4_t test_por_i16x4(int16x4_t a, int16x4_t b) {
|
|
return __riscv_por_i16x4(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_por_u16x4(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[OR_I1:%.*]] = or i64 [[A_COERCE]], [[B_COERCE]]
|
|
// RV32-NEXT: ret i64 [[OR_I1]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_por_u16x4(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[OR_I1:%.*]] = or i64 [[A_COERCE]], [[B_COERCE]]
|
|
// RV64-NEXT: ret i64 [[OR_I1]]
|
|
//
|
|
uint16x4_t test_por_u16x4(uint16x4_t a, uint16x4_t b) {
|
|
return __riscv_por_u16x4(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_por_i32x2(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[OR_I1:%.*]] = or i64 [[A_COERCE]], [[B_COERCE]]
|
|
// RV32-NEXT: ret i64 [[OR_I1]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_por_i32x2(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[OR_I1:%.*]] = or i64 [[A_COERCE]], [[B_COERCE]]
|
|
// RV64-NEXT: ret i64 [[OR_I1]]
|
|
//
|
|
int32x2_t test_por_i32x2(int32x2_t a, int32x2_t b) {
|
|
return __riscv_por_i32x2(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_por_u32x2(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[OR_I1:%.*]] = or i64 [[A_COERCE]], [[B_COERCE]]
|
|
// RV32-NEXT: ret i64 [[OR_I1]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_por_u32x2(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[OR_I1:%.*]] = or i64 [[A_COERCE]], [[B_COERCE]]
|
|
// RV64-NEXT: ret i64 [[OR_I1]]
|
|
//
|
|
uint32x2_t test_por_u32x2(uint32x2_t a, uint32x2_t b) {
|
|
return __riscv_por_u32x2(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pxor_i8x8(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[XOR_I1:%.*]] = xor i64 [[A_COERCE]], [[B_COERCE]]
|
|
// RV32-NEXT: ret i64 [[XOR_I1]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pxor_i8x8(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[XOR_I1:%.*]] = xor i64 [[A_COERCE]], [[B_COERCE]]
|
|
// RV64-NEXT: ret i64 [[XOR_I1]]
|
|
//
|
|
int8x8_t test_pxor_i8x8(int8x8_t a, int8x8_t b) {
|
|
return __riscv_pxor_i8x8(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pxor_u8x8(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[XOR_I1:%.*]] = xor i64 [[A_COERCE]], [[B_COERCE]]
|
|
// RV32-NEXT: ret i64 [[XOR_I1]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pxor_u8x8(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[XOR_I1:%.*]] = xor i64 [[A_COERCE]], [[B_COERCE]]
|
|
// RV64-NEXT: ret i64 [[XOR_I1]]
|
|
//
|
|
uint8x8_t test_pxor_u8x8(uint8x8_t a, uint8x8_t b) {
|
|
return __riscv_pxor_u8x8(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pxor_i16x4(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[XOR_I1:%.*]] = xor i64 [[A_COERCE]], [[B_COERCE]]
|
|
// RV32-NEXT: ret i64 [[XOR_I1]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pxor_i16x4(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[XOR_I1:%.*]] = xor i64 [[A_COERCE]], [[B_COERCE]]
|
|
// RV64-NEXT: ret i64 [[XOR_I1]]
|
|
//
|
|
int16x4_t test_pxor_i16x4(int16x4_t a, int16x4_t b) {
|
|
return __riscv_pxor_i16x4(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pxor_u16x4(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[XOR_I1:%.*]] = xor i64 [[A_COERCE]], [[B_COERCE]]
|
|
// RV32-NEXT: ret i64 [[XOR_I1]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pxor_u16x4(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[XOR_I1:%.*]] = xor i64 [[A_COERCE]], [[B_COERCE]]
|
|
// RV64-NEXT: ret i64 [[XOR_I1]]
|
|
//
|
|
uint16x4_t test_pxor_u16x4(uint16x4_t a, uint16x4_t b) {
|
|
return __riscv_pxor_u16x4(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pxor_i32x2(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[XOR_I1:%.*]] = xor i64 [[A_COERCE]], [[B_COERCE]]
|
|
// RV32-NEXT: ret i64 [[XOR_I1]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pxor_i32x2(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[XOR_I1:%.*]] = xor i64 [[A_COERCE]], [[B_COERCE]]
|
|
// RV64-NEXT: ret i64 [[XOR_I1]]
|
|
//
|
|
int32x2_t test_pxor_i32x2(int32x2_t a, int32x2_t b) {
|
|
return __riscv_pxor_i32x2(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pxor_u32x2(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[XOR_I1:%.*]] = xor i64 [[A_COERCE]], [[B_COERCE]]
|
|
// RV32-NEXT: ret i64 [[XOR_I1]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pxor_u32x2(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[XOR_I1:%.*]] = xor i64 [[A_COERCE]], [[B_COERCE]]
|
|
// RV64-NEXT: ret i64 [[XOR_I1]]
|
|
//
|
|
uint32x2_t test_pxor_u32x2(uint32x2_t a, uint32x2_t b) {
|
|
return __riscv_pxor_u32x2(a, b);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pnot_i8x8(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
|
|
// RV32-NEXT: [[NOT_I:%.*]] = xor <8 x i8> [[TMP0]], splat (i8 -1)
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[NOT_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP1]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pnot_i8x8(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
|
|
// RV64-NEXT: [[NOT_I:%.*]] = xor <8 x i8> [[TMP0]], splat (i8 -1)
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[NOT_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP1]]
|
|
//
|
|
int8x8_t test_pnot_i8x8(int8x8_t a) {
|
|
return __riscv_pnot_i8x8(a);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pnot_u8x8(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
|
|
// RV32-NEXT: [[NOT_I:%.*]] = xor <8 x i8> [[TMP0]], splat (i8 -1)
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[NOT_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP1]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pnot_u8x8(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <8 x i8>
|
|
// RV64-NEXT: [[NOT_I:%.*]] = xor <8 x i8> [[TMP0]], splat (i8 -1)
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[NOT_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP1]]
|
|
//
|
|
uint8x8_t test_pnot_u8x8(uint8x8_t a) {
|
|
return __riscv_pnot_u8x8(a);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pnot_i16x4(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[NOT_I:%.*]] = xor <4 x i16> [[TMP0]], splat (i16 -1)
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[NOT_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP1]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pnot_i16x4(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[NOT_I:%.*]] = xor <4 x i16> [[TMP0]], splat (i16 -1)
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[NOT_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP1]]
|
|
//
|
|
int16x4_t test_pnot_i16x4(int16x4_t a) {
|
|
return __riscv_pnot_i16x4(a);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pnot_u16x4(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[NOT_I:%.*]] = xor <4 x i16> [[TMP0]], splat (i16 -1)
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[NOT_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP1]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pnot_u16x4(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[NOT_I:%.*]] = xor <4 x i16> [[TMP0]], splat (i16 -1)
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[NOT_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP1]]
|
|
//
|
|
uint16x4_t test_pnot_u16x4(uint16x4_t a) {
|
|
return __riscv_pnot_u16x4(a);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pnot_i32x2(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
|
|
// RV32-NEXT: [[NOT_I:%.*]] = xor <2 x i32> [[TMP0]], splat (i32 -1)
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[NOT_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP1]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pnot_i32x2(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
|
|
// RV64-NEXT: [[NOT_I:%.*]] = xor <2 x i32> [[TMP0]], splat (i32 -1)
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[NOT_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP1]]
|
|
//
|
|
int32x2_t test_pnot_i32x2(int32x2_t a) {
|
|
return __riscv_pnot_i32x2(a);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pnot_u32x2(
|
|
// RV32-SAME: i64 noundef [[A_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
|
|
// RV32-NEXT: [[NOT_I:%.*]] = xor <2 x i32> [[TMP0]], splat (i32 -1)
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[NOT_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP1]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pnot_u32x2(
|
|
// RV64-SAME: i64 noundef [[A_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <2 x i32>
|
|
// RV64-NEXT: [[NOT_I:%.*]] = xor <2 x i32> [[TMP0]], splat (i32 -1)
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[NOT_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP1]]
|
|
//
|
|
uint32x2_t test_pnot_u32x2(uint32x2_t a) {
|
|
return __riscv_pnot_u32x2(a);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_paadd_i8x4(
|
|
// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
|
|
// RV32-NEXT: [[TMP2:%.*]] = call <4 x i8> @llvm.riscv.paadd.v4i8(<4 x i8> [[TMP0]], <4 x i8> [[TMP1]])
|
|
// RV32-NEXT: [[TMP3:%.*]] = bitcast <4 x i8> [[TMP2]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP3]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_paadd_i8x4(
|
|
// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
|
|
// RV64-NEXT: [[TMP2:%.*]] = call <4 x i8> @llvm.riscv.paadd.v4i8(<4 x i8> [[TMP0]], <4 x i8> [[TMP1]])
|
|
// RV64-NEXT: [[TMP3:%.*]] = bitcast <4 x i8> [[TMP2]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP3]]
|
|
//
|
|
int8x4_t test_paadd_i8x4(int8x4_t rs1, int8x4_t rs2) {
|
|
return __riscv_paadd_i8x4(rs1, rs2);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_paadd_i16x2(
|
|
// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
|
|
// RV32-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.paadd.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
|
|
// RV32-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP3]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_paadd_i16x2(
|
|
// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
|
|
// RV64-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.paadd.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
|
|
// RV64-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP3]]
|
|
//
|
|
int16x2_t test_paadd_i16x2(int16x2_t rs1, int16x2_t rs2) {
|
|
return __riscv_paadd_i16x2(rs1, rs2);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_paaddu_u8x4(
|
|
// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
|
|
// RV32-NEXT: [[TMP2:%.*]] = call <4 x i8> @llvm.riscv.paaddu.v4i8(<4 x i8> [[TMP0]], <4 x i8> [[TMP1]])
|
|
// RV32-NEXT: [[TMP3:%.*]] = bitcast <4 x i8> [[TMP2]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP3]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_paaddu_u8x4(
|
|
// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
|
|
// RV64-NEXT: [[TMP2:%.*]] = call <4 x i8> @llvm.riscv.paaddu.v4i8(<4 x i8> [[TMP0]], <4 x i8> [[TMP1]])
|
|
// RV64-NEXT: [[TMP3:%.*]] = bitcast <4 x i8> [[TMP2]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP3]]
|
|
//
|
|
uint8x4_t test_paaddu_u8x4(uint8x4_t rs1, uint8x4_t rs2) {
|
|
return __riscv_paaddu_u8x4(rs1, rs2);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_paaddu_u16x2(
|
|
// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
|
|
// RV32-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.paaddu.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
|
|
// RV32-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP3]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_paaddu_u16x2(
|
|
// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
|
|
// RV64-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.paaddu.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
|
|
// RV64-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP3]]
|
|
//
|
|
uint16x2_t test_paaddu_u16x2(uint16x2_t rs1, uint16x2_t rs2) {
|
|
return __riscv_paaddu_u16x2(rs1, rs2);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_pasub_i8x4(
|
|
// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
|
|
// RV32-NEXT: [[TMP2:%.*]] = call <4 x i8> @llvm.riscv.pasub.v4i8(<4 x i8> [[TMP0]], <4 x i8> [[TMP1]])
|
|
// RV32-NEXT: [[TMP3:%.*]] = bitcast <4 x i8> [[TMP2]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP3]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_pasub_i8x4(
|
|
// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
|
|
// RV64-NEXT: [[TMP2:%.*]] = call <4 x i8> @llvm.riscv.pasub.v4i8(<4 x i8> [[TMP0]], <4 x i8> [[TMP1]])
|
|
// RV64-NEXT: [[TMP3:%.*]] = bitcast <4 x i8> [[TMP2]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP3]]
|
|
//
|
|
int8x4_t test_pasub_i8x4(int8x4_t rs1, int8x4_t rs2) {
|
|
return __riscv_pasub_i8x4(rs1, rs2);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_pasub_i16x2(
|
|
// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
|
|
// RV32-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.pasub.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
|
|
// RV32-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP3]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_pasub_i16x2(
|
|
// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
|
|
// RV64-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.pasub.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
|
|
// RV64-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP3]]
|
|
//
|
|
int16x2_t test_pasub_i16x2(int16x2_t rs1, int16x2_t rs2) {
|
|
return __riscv_pasub_i16x2(rs1, rs2);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_pasubu_u8x4(
|
|
// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
|
|
// RV32-NEXT: [[TMP2:%.*]] = call <4 x i8> @llvm.riscv.pasubu.v4i8(<4 x i8> [[TMP0]], <4 x i8> [[TMP1]])
|
|
// RV32-NEXT: [[TMP3:%.*]] = bitcast <4 x i8> [[TMP2]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP3]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_pasubu_u8x4(
|
|
// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
|
|
// RV64-NEXT: [[TMP2:%.*]] = call <4 x i8> @llvm.riscv.pasubu.v4i8(<4 x i8> [[TMP0]], <4 x i8> [[TMP1]])
|
|
// RV64-NEXT: [[TMP3:%.*]] = bitcast <4 x i8> [[TMP2]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP3]]
|
|
//
|
|
uint8x4_t test_pasubu_u8x4(uint8x4_t rs1, uint8x4_t rs2) {
|
|
return __riscv_pasubu_u8x4(rs1, rs2);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_pasubu_u16x2(
|
|
// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
|
|
// RV32-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.pasubu.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
|
|
// RV32-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP3]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_pasubu_u16x2(
|
|
// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
|
|
// RV64-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.pasubu.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
|
|
// RV64-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP3]]
|
|
//
|
|
uint16x2_t test_pasubu_u16x2(uint16x2_t rs1, uint16x2_t rs2) {
|
|
return __riscv_pasubu_u16x2(rs1, rs2);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_paadd_i8x8(
|
|
// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
|
|
// RV32-NEXT: [[TMP2:%.*]] = call <8 x i8> @llvm.riscv.paadd.v8i8(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]])
|
|
// RV32-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP2]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP3]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_paadd_i8x8(
|
|
// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
|
|
// RV64-NEXT: [[TMP2:%.*]] = call <8 x i8> @llvm.riscv.paadd.v8i8(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]])
|
|
// RV64-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP2]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP3]]
|
|
//
|
|
int8x8_t test_paadd_i8x8(int8x8_t rs1, int8x8_t rs2) {
|
|
return __riscv_paadd_i8x8(rs1, rs2);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_paadd_i16x4(
|
|
// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.paadd.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
|
|
// RV32-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP3]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_paadd_i16x4(
|
|
// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.paadd.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
|
|
// RV64-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP3]]
|
|
//
|
|
int16x4_t test_paadd_i16x4(int16x4_t rs1, int16x4_t rs2) {
|
|
return __riscv_paadd_i16x4(rs1, rs2);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_paadd_i32x2(
|
|
// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <2 x i32>
|
|
// RV32-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.paadd.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
|
|
// RV32-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP3]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_paadd_i32x2(
|
|
// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <2 x i32>
|
|
// RV64-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.paadd.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
|
|
// RV64-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP3]]
|
|
//
|
|
int32x2_t test_paadd_i32x2(int32x2_t rs1, int32x2_t rs2) {
|
|
return __riscv_paadd_i32x2(rs1, rs2);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_paaddu_u8x8(
|
|
// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
|
|
// RV32-NEXT: [[TMP2:%.*]] = call <8 x i8> @llvm.riscv.paaddu.v8i8(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]])
|
|
// RV32-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP2]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP3]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_paaddu_u8x8(
|
|
// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
|
|
// RV64-NEXT: [[TMP2:%.*]] = call <8 x i8> @llvm.riscv.paaddu.v8i8(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]])
|
|
// RV64-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP2]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP3]]
|
|
//
|
|
uint8x8_t test_paaddu_u8x8(uint8x8_t rs1, uint8x8_t rs2) {
|
|
return __riscv_paaddu_u8x8(rs1, rs2);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_paaddu_u16x4(
|
|
// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.paaddu.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
|
|
// RV32-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP3]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_paaddu_u16x4(
|
|
// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.paaddu.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
|
|
// RV64-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP3]]
|
|
//
|
|
uint16x4_t test_paaddu_u16x4(uint16x4_t rs1, uint16x4_t rs2) {
|
|
return __riscv_paaddu_u16x4(rs1, rs2);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_paaddu_u32x2(
|
|
// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <2 x i32>
|
|
// RV32-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.paaddu.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
|
|
// RV32-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP3]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_paaddu_u32x2(
|
|
// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <2 x i32>
|
|
// RV64-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.paaddu.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
|
|
// RV64-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP3]]
|
|
//
|
|
uint32x2_t test_paaddu_u32x2(uint32x2_t rs1, uint32x2_t rs2) {
|
|
return __riscv_paaddu_u32x2(rs1, rs2);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pasub_i8x8(
|
|
// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
|
|
// RV32-NEXT: [[TMP2:%.*]] = call <8 x i8> @llvm.riscv.pasub.v8i8(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]])
|
|
// RV32-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP2]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP3]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pasub_i8x8(
|
|
// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
|
|
// RV64-NEXT: [[TMP2:%.*]] = call <8 x i8> @llvm.riscv.pasub.v8i8(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]])
|
|
// RV64-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP2]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP3]]
|
|
//
|
|
int8x8_t test_pasub_i8x8(int8x8_t rs1, int8x8_t rs2) {
|
|
return __riscv_pasub_i8x8(rs1, rs2);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pasub_i16x4(
|
|
// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.pasub.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
|
|
// RV32-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP3]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pasub_i16x4(
|
|
// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.pasub.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
|
|
// RV64-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP3]]
|
|
//
|
|
int16x4_t test_pasub_i16x4(int16x4_t rs1, int16x4_t rs2) {
|
|
return __riscv_pasub_i16x4(rs1, rs2);
|
|
}
|
|
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pasub_i32x2(
|
|
// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <2 x i32>
|
|
// RV32-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.pasub.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
|
|
// RV32-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP3]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pasub_i32x2(
|
|
// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <2 x i32>
|
|
// RV64-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.pasub.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
|
|
// RV64-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP3]]
|
|
//
|
|
int32x2_t test_pasub_i32x2(int32x2_t rs1, int32x2_t rs2) {
|
|
return __riscv_pasub_i32x2(rs1, rs2);
|
|
}
|
|
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pasubu_u8x8(
|
|
// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
|
|
// RV32-NEXT: [[TMP2:%.*]] = call <8 x i8> @llvm.riscv.pasubu.v8i8(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]])
|
|
// RV32-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP2]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP3]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pasubu_u8x8(
|
|
// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
|
|
// RV64-NEXT: [[TMP2:%.*]] = call <8 x i8> @llvm.riscv.pasubu.v8i8(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]])
|
|
// RV64-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP2]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP3]]
|
|
//
|
|
uint8x8_t test_pasubu_u8x8(uint8x8_t rs1, uint8x8_t rs2) {
|
|
return __riscv_pasubu_u8x8(rs1, rs2);
|
|
}
|
|
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pasubu_u16x4(
|
|
// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.pasubu.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
|
|
// RV32-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP3]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pasubu_u16x4(
|
|
// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.pasubu.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
|
|
// RV64-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP3]]
|
|
//
|
|
uint16x4_t test_pasubu_u16x4(uint16x4_t rs1, uint16x4_t rs2) {
|
|
return __riscv_pasubu_u16x4(rs1, rs2);
|
|
}
|
|
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pasubu_u32x2(
|
|
// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <2 x i32>
|
|
// RV32-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.pasubu.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
|
|
// RV32-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP3]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pasubu_u32x2(
|
|
// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <2 x i32>
|
|
// RV64-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.pasubu.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
|
|
// RV64-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP3]]
|
|
//
|
|
uint32x2_t test_pasubu_u32x2(uint32x2_t rs1, uint32x2_t rs2) {
|
|
return __riscv_pasubu_u32x2(rs1, rs2);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_pabs_i8x4(
|
|
// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
|
|
// RV32-NEXT: [[ELT_ABS_I:%.*]] = call <4 x i8> @llvm.abs.v4i8(<4 x i8> [[TMP0]], i1 false)
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast <4 x i8> [[ELT_ABS_I]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP1]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_pabs_i8x4(
|
|
// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
|
|
// RV64-NEXT: [[ELT_ABS_I:%.*]] = call <4 x i8> @llvm.abs.v4i8(<4 x i8> [[TMP0]], i1 false)
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast <4 x i8> [[ELT_ABS_I]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP1]]
|
|
//
|
|
uint8x4_t test_pabs_i8x4(int8x4_t rs1) {
|
|
return __riscv_pabs_i8x4(rs1);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_pabs_i16x2(
|
|
// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
|
|
// RV32-NEXT: [[ELT_ABS_I:%.*]] = call <2 x i16> @llvm.abs.v2i16(<2 x i16> [[TMP0]], i1 false)
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast <2 x i16> [[ELT_ABS_I]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP1]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_pabs_i16x2(
|
|
// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
|
|
// RV64-NEXT: [[ELT_ABS_I:%.*]] = call <2 x i16> @llvm.abs.v2i16(<2 x i16> [[TMP0]], i1 false)
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast <2 x i16> [[ELT_ABS_I]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP1]]
|
|
//
|
|
uint16x2_t test_pabs_i16x2(int16x2_t rs1) {
|
|
return __riscv_pabs_i16x2(rs1);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_pabd_i8x4(
|
|
// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
|
|
// RV32-NEXT: [[TMP2:%.*]] = call <4 x i8> @llvm.riscv.pabd.v4i8(<4 x i8> [[TMP0]], <4 x i8> [[TMP1]])
|
|
// RV32-NEXT: [[TMP3:%.*]] = bitcast <4 x i8> [[TMP2]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP3]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_pabd_i8x4(
|
|
// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
|
|
// RV64-NEXT: [[TMP2:%.*]] = call <4 x i8> @llvm.riscv.pabd.v4i8(<4 x i8> [[TMP0]], <4 x i8> [[TMP1]])
|
|
// RV64-NEXT: [[TMP3:%.*]] = bitcast <4 x i8> [[TMP2]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP3]]
|
|
//
|
|
uint8x4_t test_pabd_i8x4(int8x4_t rs1, int8x4_t rs2) {
|
|
return __riscv_pabd_i8x4(rs1, rs2);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_pabd_i16x2(
|
|
// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
|
|
// RV32-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.pabd.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
|
|
// RV32-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP3]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_pabd_i16x2(
|
|
// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
|
|
// RV64-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.pabd.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
|
|
// RV64-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP3]]
|
|
//
|
|
uint16x2_t test_pabd_i16x2(int16x2_t rs1, int16x2_t rs2) {
|
|
return __riscv_pabd_i16x2(rs1, rs2);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_pabdu_u8x4(
|
|
// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
|
|
// RV32-NEXT: [[TMP2:%.*]] = call <4 x i8> @llvm.riscv.pabdu.v4i8(<4 x i8> [[TMP0]], <4 x i8> [[TMP1]])
|
|
// RV32-NEXT: [[TMP3:%.*]] = bitcast <4 x i8> [[TMP2]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP3]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_pabdu_u8x4(
|
|
// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
|
|
// RV64-NEXT: [[TMP2:%.*]] = call <4 x i8> @llvm.riscv.pabdu.v4i8(<4 x i8> [[TMP0]], <4 x i8> [[TMP1]])
|
|
// RV64-NEXT: [[TMP3:%.*]] = bitcast <4 x i8> [[TMP2]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP3]]
|
|
//
|
|
uint8x4_t test_pabdu_u8x4(uint8x4_t rs1, uint8x4_t rs2) {
|
|
return __riscv_pabdu_u8x4(rs1, rs2);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_pabdu_u16x2(
|
|
// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
|
|
// RV32-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.pabdu.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
|
|
// RV32-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP3]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_pabdu_u16x2(
|
|
// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
|
|
// RV64-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.pabdu.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
|
|
// RV64-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP3]]
|
|
//
|
|
uint16x2_t test_pabdu_u16x2(uint16x2_t rs1, uint16x2_t rs2) {
|
|
return __riscv_pabdu_u16x2(rs1, rs2);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pabs_i8x8(
|
|
// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
|
|
// RV32-NEXT: [[ELT_ABS_I:%.*]] = call <8 x i8> @llvm.abs.v8i8(<8 x i8> [[TMP0]], i1 false)
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[ELT_ABS_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP1]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pabs_i8x8(
|
|
// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
|
|
// RV64-NEXT: [[ELT_ABS_I:%.*]] = call <8 x i8> @llvm.abs.v8i8(<8 x i8> [[TMP0]], i1 false)
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[ELT_ABS_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP1]]
|
|
//
|
|
uint8x8_t test_pabs_i8x8(int8x8_t rs1) {
|
|
return __riscv_pabs_i8x8(rs1);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pabs_i16x4(
|
|
// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[ELT_ABS_I:%.*]] = call <4 x i16> @llvm.abs.v4i16(<4 x i16> [[TMP0]], i1 false)
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[ELT_ABS_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP1]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pabs_i16x4(
|
|
// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[ELT_ABS_I:%.*]] = call <4 x i16> @llvm.abs.v4i16(<4 x i16> [[TMP0]], i1 false)
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[ELT_ABS_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP1]]
|
|
//
|
|
uint16x4_t test_pabs_i16x4(int16x4_t rs1) {
|
|
return __riscv_pabs_i16x4(rs1);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pabd_i8x8(
|
|
// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
|
|
// RV32-NEXT: [[TMP2:%.*]] = call <8 x i8> @llvm.riscv.pabd.v8i8(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]])
|
|
// RV32-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP2]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP3]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pabd_i8x8(
|
|
// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
|
|
// RV64-NEXT: [[TMP2:%.*]] = call <8 x i8> @llvm.riscv.pabd.v8i8(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]])
|
|
// RV64-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP2]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP3]]
|
|
//
|
|
uint8x8_t test_pabd_i8x8(int8x8_t rs1, int8x8_t rs2) {
|
|
return __riscv_pabd_i8x8(rs1, rs2);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pabd_i16x4(
|
|
// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.pabd.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
|
|
// RV32-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP3]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pabd_i16x4(
|
|
// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.pabd.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
|
|
// RV64-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP3]]
|
|
//
|
|
uint16x4_t test_pabd_i16x4(int16x4_t rs1, int16x4_t rs2) {
|
|
return __riscv_pabd_i16x4(rs1, rs2);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pabdu_u8x8(
|
|
// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
|
|
// RV32-NEXT: [[TMP2:%.*]] = call <8 x i8> @llvm.riscv.pabdu.v8i8(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]])
|
|
// RV32-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP2]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP3]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pabdu_u8x8(
|
|
// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
|
|
// RV64-NEXT: [[TMP2:%.*]] = call <8 x i8> @llvm.riscv.pabdu.v8i8(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]])
|
|
// RV64-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP2]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP3]]
|
|
//
|
|
uint8x8_t test_pabdu_u8x8(uint8x8_t rs1, uint8x8_t rs2) {
|
|
return __riscv_pabdu_u8x8(rs1, rs2);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pabdu_u16x4(
|
|
// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.pabdu.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
|
|
// RV32-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP3]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pabdu_u16x4(
|
|
// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.pabdu.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
|
|
// RV64-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP3]]
|
|
//
|
|
uint16x4_t test_pabdu_u16x4(uint16x4_t rs1, uint16x4_t rs2) {
|
|
return __riscv_pabdu_u16x4(rs1, rs2);
|
|
}
|
|
|
|
/* Packed Reduction Sum (32-bit) */
|
|
// RV32-LABEL: define dso_local i32 @test_predsum_i8x4_i32(
|
|
// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
|
|
// RV32-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.predsum.i32.v4i8(<4 x i8> [[TMP0]], i32 [[RS2]])
|
|
// RV32-NEXT: ret i32 [[TMP1]]
|
|
//
|
|
// RV64-LABEL: define dso_local signext i32 @test_predsum_i8x4_i32(
|
|
// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef signext [[RS2:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
|
|
// RV64-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.predsum.i32.v4i8(<4 x i8> [[TMP0]], i32 [[RS2]])
|
|
// RV64-NEXT: ret i32 [[TMP1]]
|
|
//
|
|
int32_t test_predsum_i8x4_i32(int8x4_t rs1, int32_t rs2) {
|
|
return __riscv_predsum_i8x4_i32(rs1, rs2);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_predsumu_u8x4_u32(
|
|
// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
|
|
// RV32-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.predsumu.i32.v4i8(<4 x i8> [[TMP0]], i32 [[RS2]])
|
|
// RV32-NEXT: ret i32 [[TMP1]]
|
|
//
|
|
// RV64-LABEL: define dso_local signext i32 @test_predsumu_u8x4_u32(
|
|
// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef signext [[RS2:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
|
|
// RV64-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.predsumu.i32.v4i8(<4 x i8> [[TMP0]], i32 [[RS2]])
|
|
// RV64-NEXT: ret i32 [[TMP1]]
|
|
//
|
|
uint32_t test_predsumu_u8x4_u32(uint8x4_t rs1, uint32_t rs2) {
|
|
return __riscv_predsumu_u8x4_u32(rs1, rs2);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_predsum_i16x2_i32(
|
|
// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
|
|
// RV32-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.predsum.i32.v2i16(<2 x i16> [[TMP0]], i32 [[RS2]])
|
|
// RV32-NEXT: ret i32 [[TMP1]]
|
|
//
|
|
// RV64-LABEL: define dso_local signext i32 @test_predsum_i16x2_i32(
|
|
// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef signext [[RS2:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
|
|
// RV64-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.predsum.i32.v2i16(<2 x i16> [[TMP0]], i32 [[RS2]])
|
|
// RV64-NEXT: ret i32 [[TMP1]]
|
|
//
|
|
int32_t test_predsum_i16x2_i32(int16x2_t rs1, int32_t rs2) {
|
|
return __riscv_predsum_i16x2_i32(rs1, rs2);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_predsumu_u16x2_u32(
|
|
// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
|
|
// RV32-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.predsumu.i32.v2i16(<2 x i16> [[TMP0]], i32 [[RS2]])
|
|
// RV32-NEXT: ret i32 [[TMP1]]
|
|
//
|
|
// RV64-LABEL: define dso_local signext i32 @test_predsumu_u16x2_u32(
|
|
// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef signext [[RS2:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
|
|
// RV64-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.predsumu.i32.v2i16(<2 x i16> [[TMP0]], i32 [[RS2]])
|
|
// RV64-NEXT: ret i32 [[TMP1]]
|
|
//
|
|
uint32_t test_predsumu_u16x2_u32(uint16x2_t rs1, uint32_t rs2) {
|
|
return __riscv_predsumu_u16x2_u32(rs1, rs2);
|
|
}
|
|
|
|
/* Packed Reduction Sum (64-bit) */
|
|
// RV32-LABEL: define dso_local i32 @test_predsum_i8x8_i32(
|
|
// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
|
|
// RV32-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.predsum.i32.v8i8(<8 x i8> [[TMP0]], i32 [[RS2]])
|
|
// RV32-NEXT: ret i32 [[TMP1]]
|
|
//
|
|
// RV64-LABEL: define dso_local signext i32 @test_predsum_i8x8_i32(
|
|
// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i32 noundef signext [[RS2:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
|
|
// RV64-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.predsum.i32.v8i8(<8 x i8> [[TMP0]], i32 [[RS2]])
|
|
// RV64-NEXT: ret i32 [[TMP1]]
|
|
//
|
|
int32_t test_predsum_i8x8_i32(int8x8_t rs1, int32_t rs2) {
|
|
return __riscv_predsum_i8x8_i32(rs1, rs2);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_predsumu_u8x8_u32(
|
|
// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
|
|
// RV32-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.predsumu.i32.v8i8(<8 x i8> [[TMP0]], i32 [[RS2]])
|
|
// RV32-NEXT: ret i32 [[TMP1]]
|
|
//
|
|
// RV64-LABEL: define dso_local signext i32 @test_predsumu_u8x8_u32(
|
|
// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i32 noundef signext [[RS2:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
|
|
// RV64-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.predsumu.i32.v8i8(<8 x i8> [[TMP0]], i32 [[RS2]])
|
|
// RV64-NEXT: ret i32 [[TMP1]]
|
|
//
|
|
uint32_t test_predsumu_u8x8_u32(uint8x8_t rs1, uint32_t rs2) {
|
|
return __riscv_predsumu_u8x8_u32(rs1, rs2);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_predsum_i16x4_i32(
|
|
// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.predsum.i32.v4i16(<4 x i16> [[TMP0]], i32 [[RS2]])
|
|
// RV32-NEXT: ret i32 [[TMP1]]
|
|
//
|
|
// RV64-LABEL: define dso_local signext i32 @test_predsum_i16x4_i32(
|
|
// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i32 noundef signext [[RS2:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.predsum.i32.v4i16(<4 x i16> [[TMP0]], i32 [[RS2]])
|
|
// RV64-NEXT: ret i32 [[TMP1]]
|
|
//
|
|
int32_t test_predsum_i16x4_i32(int16x4_t rs1, int32_t rs2) {
|
|
return __riscv_predsum_i16x4_i32(rs1, rs2);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_predsumu_u16x4_u32(
|
|
// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.predsumu.i32.v4i16(<4 x i16> [[TMP0]], i32 [[RS2]])
|
|
// RV32-NEXT: ret i32 [[TMP1]]
|
|
//
|
|
// RV64-LABEL: define dso_local signext i32 @test_predsumu_u16x4_u32(
|
|
// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i32 noundef signext [[RS2:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.predsumu.i32.v4i16(<4 x i16> [[TMP0]], i32 [[RS2]])
|
|
// RV64-NEXT: ret i32 [[TMP1]]
|
|
//
|
|
uint32_t test_predsumu_u16x4_u32(uint16x4_t rs1, uint32_t rs2) {
|
|
return __riscv_predsumu_u16x4_u32(rs1, rs2);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_predsum_i8x8_i64(
|
|
// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
|
|
// RV32-NEXT: [[TMP1:%.*]] = call i64 @llvm.riscv.predsum.i64.v8i8(<8 x i8> [[TMP0]], i64 [[RS2]])
|
|
// RV32-NEXT: ret i64 [[TMP1]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_predsum_i8x8_i64(
|
|
// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
|
|
// RV64-NEXT: [[TMP1:%.*]] = call i64 @llvm.riscv.predsum.i64.v8i8(<8 x i8> [[TMP0]], i64 [[RS2]])
|
|
// RV64-NEXT: ret i64 [[TMP1]]
|
|
//
|
|
int64_t test_predsum_i8x8_i64(int8x8_t rs1, int64_t rs2) {
|
|
return __riscv_predsum_i8x8_i64(rs1, rs2);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_predsumu_u8x8_u64(
|
|
// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
|
|
// RV32-NEXT: [[TMP1:%.*]] = call i64 @llvm.riscv.predsumu.i64.v8i8(<8 x i8> [[TMP0]], i64 [[RS2]])
|
|
// RV32-NEXT: ret i64 [[TMP1]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_predsumu_u8x8_u64(
|
|
// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
|
|
// RV64-NEXT: [[TMP1:%.*]] = call i64 @llvm.riscv.predsumu.i64.v8i8(<8 x i8> [[TMP0]], i64 [[RS2]])
|
|
// RV64-NEXT: ret i64 [[TMP1]]
|
|
//
|
|
uint64_t test_predsumu_u8x8_u64(uint8x8_t rs1, uint64_t rs2) {
|
|
return __riscv_predsumu_u8x8_u64(rs1, rs2);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_predsum_i16x4_i64(
|
|
// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[TMP1:%.*]] = call i64 @llvm.riscv.predsum.i64.v4i16(<4 x i16> [[TMP0]], i64 [[RS2]])
|
|
// RV32-NEXT: ret i64 [[TMP1]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_predsum_i16x4_i64(
|
|
// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[TMP1:%.*]] = call i64 @llvm.riscv.predsum.i64.v4i16(<4 x i16> [[TMP0]], i64 [[RS2]])
|
|
// RV64-NEXT: ret i64 [[TMP1]]
|
|
//
|
|
int64_t test_predsum_i16x4_i64(int16x4_t rs1, int64_t rs2) {
|
|
return __riscv_predsum_i16x4_i64(rs1, rs2);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_predsumu_u16x4_u64(
|
|
// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[TMP1:%.*]] = call i64 @llvm.riscv.predsumu.i64.v4i16(<4 x i16> [[TMP0]], i64 [[RS2]])
|
|
// RV32-NEXT: ret i64 [[TMP1]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_predsumu_u16x4_u64(
|
|
// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[TMP1:%.*]] = call i64 @llvm.riscv.predsumu.i64.v4i16(<4 x i16> [[TMP0]], i64 [[RS2]])
|
|
// RV64-NEXT: ret i64 [[TMP1]]
|
|
//
|
|
uint64_t test_predsumu_u16x4_u64(uint16x4_t rs1, uint64_t rs2) {
|
|
return __riscv_predsumu_u16x4_u64(rs1, rs2);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_predsum_i32x2_i64(
|
|
// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
|
|
// RV32-NEXT: [[TMP1:%.*]] = call i64 @llvm.riscv.predsum.i64.v2i32(<2 x i32> [[TMP0]], i64 [[RS2]])
|
|
// RV32-NEXT: ret i64 [[TMP1]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_predsum_i32x2_i64(
|
|
// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
|
|
// RV64-NEXT: [[TMP1:%.*]] = call i64 @llvm.riscv.predsum.i64.v2i32(<2 x i32> [[TMP0]], i64 [[RS2]])
|
|
// RV64-NEXT: ret i64 [[TMP1]]
|
|
//
|
|
int64_t test_predsum_i32x2_i64(int32x2_t rs1, int64_t rs2) {
|
|
return __riscv_predsum_i32x2_i64(rs1, rs2);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_predsumu_u32x2_u64(
|
|
// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
|
|
// RV32-NEXT: [[TMP1:%.*]] = call i64 @llvm.riscv.predsumu.i64.v2i32(<2 x i32> [[TMP0]], i64 [[RS2]])
|
|
// RV32-NEXT: ret i64 [[TMP1]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_predsumu_u32x2_u64(
|
|
// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
|
|
// RV64-NEXT: [[TMP1:%.*]] = call i64 @llvm.riscv.predsumu.i64.v2i32(<2 x i32> [[TMP0]], i64 [[RS2]])
|
|
// RV64-NEXT: ret i64 [[TMP1]]
|
|
//
|
|
uint64_t test_predsumu_u32x2_u64(uint32x2_t rs1, uint64_t rs2) {
|
|
return __riscv_predsumu_u32x2_u64(rs1, rs2);
|
|
}
|
|
|
|
// Packed Merge (32-bit)
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_pmerge_u8x4(
|
|
// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]], i32 noundef [[RD_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast i32 [[RD_COERCE]] to <4 x i8>
|
|
// RV32-NEXT: [[TMP3:%.*]] = call <4 x i8> @llvm.riscv.pmerge.v4i8(<4 x i8> [[TMP0]], <4 x i8> [[TMP1]], <4 x i8> [[TMP2]])
|
|
// RV32-NEXT: [[TMP4:%.*]] = bitcast <4 x i8> [[TMP3]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP4]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_pmerge_u8x4(
|
|
// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]], i32 noundef [[RD_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast i32 [[RD_COERCE]] to <4 x i8>
|
|
// RV64-NEXT: [[TMP3:%.*]] = call <4 x i8> @llvm.riscv.pmerge.v4i8(<4 x i8> [[TMP0]], <4 x i8> [[TMP1]], <4 x i8> [[TMP2]])
|
|
// RV64-NEXT: [[TMP4:%.*]] = bitcast <4 x i8> [[TMP3]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP4]]
|
|
//
|
|
uint8x4_t test_pmerge_u8x4(uint8x4_t rs1, uint8x4_t rs2, uint8x4_t rd) {
|
|
return __riscv_pmerge_u8x4(rs1, rs2, rd);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_pmerge_i8x4(
|
|
// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]], i32 noundef [[RD_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast i32 [[RD_COERCE]] to <4 x i8>
|
|
// RV32-NEXT: [[TMP3:%.*]] = call <4 x i8> @llvm.riscv.pmerge.v4i8(<4 x i8> [[TMP0]], <4 x i8> [[TMP1]], <4 x i8> [[TMP2]])
|
|
// RV32-NEXT: [[TMP4:%.*]] = bitcast <4 x i8> [[TMP3]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP4]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_pmerge_i8x4(
|
|
// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]], i32 noundef [[RD_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast i32 [[RD_COERCE]] to <4 x i8>
|
|
// RV64-NEXT: [[TMP3:%.*]] = call <4 x i8> @llvm.riscv.pmerge.v4i8(<4 x i8> [[TMP0]], <4 x i8> [[TMP1]], <4 x i8> [[TMP2]])
|
|
// RV64-NEXT: [[TMP4:%.*]] = bitcast <4 x i8> [[TMP3]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP4]]
|
|
//
|
|
int8x4_t test_pmerge_i8x4(int8x4_t rs1, int8x4_t rs2, uint8x4_t rd) {
|
|
return __riscv_pmerge_i8x4(rs1, rs2, rd);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_pmerge_u16x2(
|
|
// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]], i32 noundef [[RD_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast i32 [[RD_COERCE]] to <2 x i16>
|
|
// RV32-NEXT: [[TMP3:%.*]] = call <2 x i16> @llvm.riscv.pmerge.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]], <2 x i16> [[TMP2]])
|
|
// RV32-NEXT: [[TMP4:%.*]] = bitcast <2 x i16> [[TMP3]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP4]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_pmerge_u16x2(
|
|
// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]], i32 noundef [[RD_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast i32 [[RD_COERCE]] to <2 x i16>
|
|
// RV64-NEXT: [[TMP3:%.*]] = call <2 x i16> @llvm.riscv.pmerge.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]], <2 x i16> [[TMP2]])
|
|
// RV64-NEXT: [[TMP4:%.*]] = bitcast <2 x i16> [[TMP3]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP4]]
|
|
//
|
|
uint16x2_t test_pmerge_u16x2(uint16x2_t rs1, uint16x2_t rs2, uint16x2_t rd) {
|
|
return __riscv_pmerge_u16x2(rs1, rs2, rd);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_pmerge_i16x2(
|
|
// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]], i32 noundef [[RD_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast i32 [[RD_COERCE]] to <2 x i16>
|
|
// RV32-NEXT: [[TMP3:%.*]] = call <2 x i16> @llvm.riscv.pmerge.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]], <2 x i16> [[TMP2]])
|
|
// RV32-NEXT: [[TMP4:%.*]] = bitcast <2 x i16> [[TMP3]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP4]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_pmerge_i16x2(
|
|
// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]], i32 noundef [[RD_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast i32 [[RD_COERCE]] to <2 x i16>
|
|
// RV64-NEXT: [[TMP3:%.*]] = call <2 x i16> @llvm.riscv.pmerge.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]], <2 x i16> [[TMP2]])
|
|
// RV64-NEXT: [[TMP4:%.*]] = bitcast <2 x i16> [[TMP3]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP4]]
|
|
//
|
|
int16x2_t test_pmerge_i16x2(int16x2_t rs1, int16x2_t rs2, uint16x2_t rd) {
|
|
return __riscv_pmerge_i16x2(rs1, rs2, rd);
|
|
}
|
|
|
|
// Packed Merge (64-bit)
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pmerge_u8x8(
|
|
// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]], i64 noundef [[RD_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast i64 [[RD_COERCE]] to <8 x i8>
|
|
// RV32-NEXT: [[TMP3:%.*]] = call <8 x i8> @llvm.riscv.pmerge.v8i8(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]], <8 x i8> [[TMP2]])
|
|
// RV32-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP3]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP4]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pmerge_u8x8(
|
|
// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]], i64 noundef [[RD_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast i64 [[RD_COERCE]] to <8 x i8>
|
|
// RV64-NEXT: [[TMP3:%.*]] = call <8 x i8> @llvm.riscv.pmerge.v8i8(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]], <8 x i8> [[TMP2]])
|
|
// RV64-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP3]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP4]]
|
|
//
|
|
uint8x8_t test_pmerge_u8x8(uint8x8_t rs1, uint8x8_t rs2, uint8x8_t rd) {
|
|
return __riscv_pmerge_u8x8(rs1, rs2, rd);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pmerge_i8x8(
|
|
// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]], i64 noundef [[RD_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast i64 [[RD_COERCE]] to <8 x i8>
|
|
// RV32-NEXT: [[TMP3:%.*]] = call <8 x i8> @llvm.riscv.pmerge.v8i8(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]], <8 x i8> [[TMP2]])
|
|
// RV32-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP3]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP4]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pmerge_i8x8(
|
|
// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]], i64 noundef [[RD_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast i64 [[RD_COERCE]] to <8 x i8>
|
|
// RV64-NEXT: [[TMP3:%.*]] = call <8 x i8> @llvm.riscv.pmerge.v8i8(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]], <8 x i8> [[TMP2]])
|
|
// RV64-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP3]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP4]]
|
|
//
|
|
int8x8_t test_pmerge_i8x8(int8x8_t rs1, int8x8_t rs2, uint8x8_t rd) {
|
|
return __riscv_pmerge_i8x8(rs1, rs2, rd);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pmerge_u16x4(
|
|
// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]], i64 noundef [[RD_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast i64 [[RD_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[TMP3:%.*]] = call <4 x i16> @llvm.riscv.pmerge.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]], <4 x i16> [[TMP2]])
|
|
// RV32-NEXT: [[TMP4:%.*]] = bitcast <4 x i16> [[TMP3]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP4]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pmerge_u16x4(
|
|
// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]], i64 noundef [[RD_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast i64 [[RD_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[TMP3:%.*]] = call <4 x i16> @llvm.riscv.pmerge.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]], <4 x i16> [[TMP2]])
|
|
// RV64-NEXT: [[TMP4:%.*]] = bitcast <4 x i16> [[TMP3]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP4]]
|
|
//
|
|
uint16x4_t test_pmerge_u16x4(uint16x4_t rs1, uint16x4_t rs2, uint16x4_t rd) {
|
|
return __riscv_pmerge_u16x4(rs1, rs2, rd);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pmerge_i16x4(
|
|
// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]], i64 noundef [[RD_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast i64 [[RD_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[TMP3:%.*]] = call <4 x i16> @llvm.riscv.pmerge.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]], <4 x i16> [[TMP2]])
|
|
// RV32-NEXT: [[TMP4:%.*]] = bitcast <4 x i16> [[TMP3]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP4]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pmerge_i16x4(
|
|
// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]], i64 noundef [[RD_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast i64 [[RD_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[TMP3:%.*]] = call <4 x i16> @llvm.riscv.pmerge.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]], <4 x i16> [[TMP2]])
|
|
// RV64-NEXT: [[TMP4:%.*]] = bitcast <4 x i16> [[TMP3]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP4]]
|
|
//
|
|
int16x4_t test_pmerge_i16x4(int16x4_t rs1, int16x4_t rs2, uint16x4_t rd) {
|
|
return __riscv_pmerge_i16x4(rs1, rs2, rd);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pmerge_u32x2(
|
|
// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]], i64 noundef [[RD_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <2 x i32>
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast i64 [[RD_COERCE]] to <2 x i32>
|
|
// RV32-NEXT: [[TMP3:%.*]] = call <2 x i32> @llvm.riscv.pmerge.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]], <2 x i32> [[TMP2]])
|
|
// RV32-NEXT: [[TMP4:%.*]] = bitcast <2 x i32> [[TMP3]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP4]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pmerge_u32x2(
|
|
// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]], i64 noundef [[RD_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <2 x i32>
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast i64 [[RD_COERCE]] to <2 x i32>
|
|
// RV64-NEXT: [[TMP3:%.*]] = call <2 x i32> @llvm.riscv.pmerge.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]], <2 x i32> [[TMP2]])
|
|
// RV64-NEXT: [[TMP4:%.*]] = bitcast <2 x i32> [[TMP3]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP4]]
|
|
//
|
|
uint32x2_t test_pmerge_u32x2(uint32x2_t rs1, uint32x2_t rs2, uint32x2_t rd) {
|
|
return __riscv_pmerge_u32x2(rs1, rs2, rd);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pmerge_i32x2(
|
|
// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]], i64 noundef [[RD_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <2 x i32>
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast i64 [[RD_COERCE]] to <2 x i32>
|
|
// RV32-NEXT: [[TMP3:%.*]] = call <2 x i32> @llvm.riscv.pmerge.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]], <2 x i32> [[TMP2]])
|
|
// RV32-NEXT: [[TMP4:%.*]] = bitcast <2 x i32> [[TMP3]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP4]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pmerge_i32x2(
|
|
// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]], i64 noundef [[RD_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <2 x i32>
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast i64 [[RD_COERCE]] to <2 x i32>
|
|
// RV64-NEXT: [[TMP3:%.*]] = call <2 x i32> @llvm.riscv.pmerge.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]], <2 x i32> [[TMP2]])
|
|
// RV64-NEXT: [[TMP4:%.*]] = bitcast <2 x i32> [[TMP3]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP4]]
|
|
//
|
|
int32x2_t test_pmerge_i32x2(int32x2_t rs1, int32x2_t rs2, uint32x2_t rd) {
|
|
return __riscv_pmerge_i32x2(rs1, rs2, rd);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_prev_i8x4(
|
|
// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = call i32 @llvm.bswap.i32(i32 [[RS1_COERCE]])
|
|
// RV32-NEXT: ret i32 [[TMP0]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_prev_i8x4(
|
|
// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = call i32 @llvm.bswap.i32(i32 [[RS1_COERCE]])
|
|
// RV64-NEXT: ret i32 [[TMP0]]
|
|
//
|
|
int8x4_t test_prev_i8x4(int8x4_t rs1) {
|
|
return __riscv_prev_i8x4(rs1);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_prev_u8x4(
|
|
// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = call i32 @llvm.bswap.i32(i32 [[RS1_COERCE]])
|
|
// RV32-NEXT: ret i32 [[TMP0]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_prev_u8x4(
|
|
// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = call i32 @llvm.bswap.i32(i32 [[RS1_COERCE]])
|
|
// RV64-NEXT: ret i32 [[TMP0]]
|
|
//
|
|
uint8x4_t test_prev_u8x4(uint8x4_t rs1) {
|
|
return __riscv_prev_u8x4(rs1);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_prev_i16x2(
|
|
// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
|
|
// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <2 x i16> [[TMP0]], <2 x i16> poison, <2 x i32> <i32 1, i32 0>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast <2 x i16> [[SHUFFLE_I]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP1]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_prev_i16x2(
|
|
// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
|
|
// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <2 x i16> [[TMP0]], <2 x i16> poison, <2 x i32> <i32 1, i32 0>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast <2 x i16> [[SHUFFLE_I]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP1]]
|
|
//
|
|
int16x2_t test_prev_i16x2(int16x2_t rs1) {
|
|
return __riscv_prev_i16x2(rs1);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_prev_u16x2(
|
|
// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
|
|
// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <2 x i16> [[TMP0]], <2 x i16> poison, <2 x i32> <i32 1, i32 0>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast <2 x i16> [[SHUFFLE_I]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP1]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_prev_u16x2(
|
|
// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
|
|
// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <2 x i16> [[TMP0]], <2 x i16> poison, <2 x i32> <i32 1, i32 0>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast <2 x i16> [[SHUFFLE_I]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP1]]
|
|
//
|
|
uint16x2_t test_prev_u16x2(uint16x2_t rs1) {
|
|
return __riscv_prev_u16x2(rs1);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_prev_i8x8(
|
|
// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
|
|
// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> poison, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[SHUFFLE_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP1]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_prev_i8x8(
|
|
// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.bswap.i64(i64 [[RS1_COERCE]])
|
|
// RV64-NEXT: ret i64 [[TMP0]]
|
|
//
|
|
int8x8_t test_prev_i8x8(int8x8_t rs1) {
|
|
return __riscv_prev_i8x8(rs1);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_prev_u8x8(
|
|
// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
|
|
// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> poison, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[SHUFFLE_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP1]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_prev_u8x8(
|
|
// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.bswap.i64(i64 [[RS1_COERCE]])
|
|
// RV64-NEXT: ret i64 [[TMP0]]
|
|
//
|
|
uint8x8_t test_prev_u8x8(uint8x8_t rs1) {
|
|
return __riscv_prev_u8x8(rs1);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_prev_i16x4(
|
|
// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP1]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_prev_i16x4(
|
|
// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP1]]
|
|
//
|
|
int16x4_t test_prev_i16x4(int16x4_t rs1) {
|
|
return __riscv_prev_i16x4(rs1);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_prev_u16x4(
|
|
// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP1]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_prev_u16x4(
|
|
// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP1]]
|
|
//
|
|
uint16x4_t test_prev_u16x4(uint16x4_t rs1) {
|
|
return __riscv_prev_u16x4(rs1);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_prev_i32x2(
|
|
// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
|
|
// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <2 x i32> [[TMP0]], <2 x i32> poison, <2 x i32> <i32 1, i32 0>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP1]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_prev_i32x2(
|
|
// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
|
|
// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <2 x i32> [[TMP0]], <2 x i32> poison, <2 x i32> <i32 1, i32 0>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP1]]
|
|
//
|
|
int32x2_t test_prev_i32x2(int32x2_t rs1) {
|
|
return __riscv_prev_i32x2(rs1);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_prev_u32x2(
|
|
// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
|
|
// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <2 x i32> [[TMP0]], <2 x i32> poison, <2 x i32> <i32 1, i32 0>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP1]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_prev_u32x2(
|
|
// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
|
|
// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <2 x i32> [[TMP0]], <2 x i32> poison, <2 x i32> <i32 1, i32 0>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP1]]
|
|
//
|
|
uint32x2_t test_prev_u32x2(uint32x2_t rs1) {
|
|
return __riscv_prev_u32x2(rs1);
|
|
}
|
|
|
|
/* Packed Zip */
|
|
// RV32-LABEL: define dso_local i64 @test_pzip_i8x8(
|
|
// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
|
|
// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i8> [[TMP0]], <4 x i8> [[TMP1]], <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SHUFFLE_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pzip_i8x8(
|
|
// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
|
|
// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i8> [[TMP0]], <4 x i8> [[TMP1]], <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SHUFFLE_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
int8x8_t test_pzip_i8x8(int8x4_t rs1, int8x4_t rs2) {
|
|
return __riscv_pzip_i8x8(rs1, rs2);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pzip_u8x8(
|
|
// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
|
|
// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i8> [[TMP0]], <4 x i8> [[TMP1]], <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SHUFFLE_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pzip_u8x8(
|
|
// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
|
|
// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i8> [[TMP0]], <4 x i8> [[TMP1]], <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SHUFFLE_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
uint8x8_t test_pzip_u8x8(uint8x4_t rs1, uint8x4_t rs2) {
|
|
return __riscv_pzip_u8x8(rs1, rs2);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pzip_i16x4(
|
|
// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
|
|
// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <2 x i16> [[TMP0]], <2 x i16> [[TMP1]], <4 x i32> <i32 0, i32 2, i32 1, i32 3>
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pzip_i16x4(
|
|
// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
|
|
// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <2 x i16> [[TMP0]], <2 x i16> [[TMP1]], <4 x i32> <i32 0, i32 2, i32 1, i32 3>
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
int16x4_t test_pzip_i16x4(int16x2_t rs1, int16x2_t rs2) {
|
|
return __riscv_pzip_i16x4(rs1, rs2);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pzip_u16x4(
|
|
// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
|
|
// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <2 x i16> [[TMP0]], <2 x i16> [[TMP1]], <4 x i32> <i32 0, i32 2, i32 1, i32 3>
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pzip_u16x4(
|
|
// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
|
|
// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <2 x i16> [[TMP0]], <2 x i16> [[TMP1]], <4 x i32> <i32 0, i32 2, i32 1, i32 3>
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
uint16x4_t test_pzip_u16x4(uint16x2_t rs1, uint16x2_t rs2) {
|
|
return __riscv_pzip_u16x4(rs1, rs2);
|
|
}
|
|
|
|
/* Packed Unzip */
|
|
// RV32-LABEL: define dso_local i32 @test_punzipe_i8x4(
|
|
// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
|
|
// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast <4 x i8> [[SHUFFLE_I]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP1]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_punzipe_i8x4(
|
|
// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
|
|
// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast <4 x i8> [[SHUFFLE_I]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP1]]
|
|
//
|
|
int8x4_t test_punzipe_i8x4(int8x8_t rs1) {
|
|
return __riscv_punzipe_i8x4(rs1);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_punzipo_i8x4(
|
|
// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
|
|
// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast <4 x i8> [[SHUFFLE_I]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP1]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_punzipo_i8x4(
|
|
// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
|
|
// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast <4 x i8> [[SHUFFLE_I]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP1]]
|
|
//
|
|
int8x4_t test_punzipo_i8x4(int8x8_t rs1) {
|
|
return __riscv_punzipo_i8x4(rs1);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_punzipe_u8x4(
|
|
// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
|
|
// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast <4 x i8> [[SHUFFLE_I]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP1]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_punzipe_u8x4(
|
|
// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
|
|
// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast <4 x i8> [[SHUFFLE_I]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP1]]
|
|
//
|
|
uint8x4_t test_punzipe_u8x4(uint8x8_t rs1) {
|
|
return __riscv_punzipe_u8x4(rs1);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_punzipo_u8x4(
|
|
// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
|
|
// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast <4 x i8> [[SHUFFLE_I]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP1]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_punzipo_u8x4(
|
|
// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
|
|
// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast <4 x i8> [[SHUFFLE_I]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP1]]
|
|
//
|
|
uint8x4_t test_punzipo_u8x4(uint8x8_t rs1) {
|
|
return __riscv_punzipo_u8x4(rs1);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_punzipe_i16x2(
|
|
// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> poison, <2 x i32> <i32 0, i32 2>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast <2 x i16> [[SHUFFLE_I]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP1]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_punzipe_i16x2(
|
|
// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> poison, <2 x i32> <i32 0, i32 2>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast <2 x i16> [[SHUFFLE_I]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP1]]
|
|
//
|
|
int16x2_t test_punzipe_i16x2(int16x4_t rs1) {
|
|
return __riscv_punzipe_i16x2(rs1);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_punzipo_i16x2(
|
|
// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> poison, <2 x i32> <i32 1, i32 3>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast <2 x i16> [[SHUFFLE_I]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP1]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_punzipo_i16x2(
|
|
// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> poison, <2 x i32> <i32 1, i32 3>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast <2 x i16> [[SHUFFLE_I]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP1]]
|
|
//
|
|
int16x2_t test_punzipo_i16x2(int16x4_t rs1) {
|
|
return __riscv_punzipo_i16x2(rs1);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_punzipe_u16x2(
|
|
// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> poison, <2 x i32> <i32 0, i32 2>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast <2 x i16> [[SHUFFLE_I]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP1]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_punzipe_u16x2(
|
|
// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> poison, <2 x i32> <i32 0, i32 2>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast <2 x i16> [[SHUFFLE_I]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP1]]
|
|
//
|
|
uint16x2_t test_punzipe_u16x2(uint16x4_t rs1) {
|
|
return __riscv_punzipe_u16x2(rs1);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_punzipo_u16x2(
|
|
// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> poison, <2 x i32> <i32 1, i32 3>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast <2 x i16> [[SHUFFLE_I]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP1]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_punzipo_u16x2(
|
|
// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> poison, <2 x i32> <i32 1, i32 3>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast <2 x i16> [[SHUFFLE_I]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP1]]
|
|
//
|
|
uint16x2_t test_punzipo_u16x2(uint16x4_t rs1) {
|
|
return __riscv_punzipo_u16x2(rs1);
|
|
}
|
|
|
|
/* Packed Pair */
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_ppaire_i8x4(
|
|
// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
|
|
// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i8> [[TMP0]], <4 x i8> [[TMP1]], <4 x i32> <i32 0, i32 4, i32 2, i32 6>
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SHUFFLE_I]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_ppaire_i8x4(
|
|
// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
|
|
// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i8> [[TMP0]], <4 x i8> [[TMP1]], <4 x i32> <i32 0, i32 4, i32 2, i32 6>
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SHUFFLE_I]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
int8x4_t test_ppaire_i8x4(int8x4_t rs1, int8x4_t rs2) {
|
|
return __riscv_ppaire_i8x4(rs1, rs2);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_ppaire_u8x4(
|
|
// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
|
|
// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i8> [[TMP0]], <4 x i8> [[TMP1]], <4 x i32> <i32 0, i32 4, i32 2, i32 6>
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SHUFFLE_I]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_ppaire_u8x4(
|
|
// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
|
|
// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i8> [[TMP0]], <4 x i8> [[TMP1]], <4 x i32> <i32 0, i32 4, i32 2, i32 6>
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SHUFFLE_I]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
uint8x4_t test_ppaire_u8x4(uint8x4_t rs1, uint8x4_t rs2) {
|
|
return __riscv_ppaire_u8x4(rs1, rs2);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_ppaireo_i8x4(
|
|
// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
|
|
// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i8> [[TMP0]], <4 x i8> [[TMP1]], <4 x i32> <i32 0, i32 5, i32 2, i32 7>
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SHUFFLE_I]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_ppaireo_i8x4(
|
|
// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
|
|
// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i8> [[TMP0]], <4 x i8> [[TMP1]], <4 x i32> <i32 0, i32 5, i32 2, i32 7>
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SHUFFLE_I]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
int8x4_t test_ppaireo_i8x4(int8x4_t rs1, int8x4_t rs2) {
|
|
return __riscv_ppaireo_i8x4(rs1, rs2);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_ppaireo_u8x4(
|
|
// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
|
|
// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i8> [[TMP0]], <4 x i8> [[TMP1]], <4 x i32> <i32 0, i32 5, i32 2, i32 7>
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SHUFFLE_I]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_ppaireo_u8x4(
|
|
// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
|
|
// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i8> [[TMP0]], <4 x i8> [[TMP1]], <4 x i32> <i32 0, i32 5, i32 2, i32 7>
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SHUFFLE_I]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
uint8x4_t test_ppaireo_u8x4(uint8x4_t rs1, uint8x4_t rs2) {
|
|
return __riscv_ppaireo_u8x4(rs1, rs2);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_ppairoe_i8x4(
|
|
// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
|
|
// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i8> [[TMP0]], <4 x i8> [[TMP1]], <4 x i32> <i32 1, i32 4, i32 3, i32 6>
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SHUFFLE_I]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_ppairoe_i8x4(
|
|
// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
|
|
// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i8> [[TMP0]], <4 x i8> [[TMP1]], <4 x i32> <i32 1, i32 4, i32 3, i32 6>
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SHUFFLE_I]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
int8x4_t test_ppairoe_i8x4(int8x4_t rs1, int8x4_t rs2) {
|
|
return __riscv_ppairoe_i8x4(rs1, rs2);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_ppairoe_u8x4(
|
|
// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
|
|
// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i8> [[TMP0]], <4 x i8> [[TMP1]], <4 x i32> <i32 1, i32 4, i32 3, i32 6>
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SHUFFLE_I]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_ppairoe_u8x4(
|
|
// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
|
|
// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i8> [[TMP0]], <4 x i8> [[TMP1]], <4 x i32> <i32 1, i32 4, i32 3, i32 6>
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SHUFFLE_I]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
uint8x4_t test_ppairoe_u8x4(uint8x4_t rs1, uint8x4_t rs2) {
|
|
return __riscv_ppairoe_u8x4(rs1, rs2);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_ppairo_i8x4(
|
|
// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
|
|
// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i8> [[TMP0]], <4 x i8> [[TMP1]], <4 x i32> <i32 1, i32 5, i32 3, i32 7>
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SHUFFLE_I]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_ppairo_i8x4(
|
|
// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
|
|
// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i8> [[TMP0]], <4 x i8> [[TMP1]], <4 x i32> <i32 1, i32 5, i32 3, i32 7>
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SHUFFLE_I]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
int8x4_t test_ppairo_i8x4(int8x4_t rs1, int8x4_t rs2) {
|
|
return __riscv_ppairo_i8x4(rs1, rs2);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_ppairo_u8x4(
|
|
// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
|
|
// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i8> [[TMP0]], <4 x i8> [[TMP1]], <4 x i32> <i32 1, i32 5, i32 3, i32 7>
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SHUFFLE_I]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_ppairo_u8x4(
|
|
// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
|
|
// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i8> [[TMP0]], <4 x i8> [[TMP1]], <4 x i32> <i32 1, i32 5, i32 3, i32 7>
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SHUFFLE_I]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
uint8x4_t test_ppairo_u8x4(uint8x4_t rs1, uint8x4_t rs2) {
|
|
return __riscv_ppairo_u8x4(rs1, rs2);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_ppaire_i8x8(
|
|
// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
|
|
// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> [[TMP1]], <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14>
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SHUFFLE_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_ppaire_i8x8(
|
|
// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
|
|
// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> [[TMP1]], <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14>
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SHUFFLE_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
int8x8_t test_ppaire_i8x8(int8x8_t rs1, int8x8_t rs2) {
|
|
return __riscv_ppaire_i8x8(rs1, rs2);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_ppaire_u8x8(
|
|
// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
|
|
// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> [[TMP1]], <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14>
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SHUFFLE_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_ppaire_u8x8(
|
|
// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
|
|
// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> [[TMP1]], <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14>
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SHUFFLE_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
uint8x8_t test_ppaire_u8x8(uint8x8_t rs1, uint8x8_t rs2) {
|
|
return __riscv_ppaire_u8x8(rs1, rs2);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_ppaireo_i8x8(
|
|
// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
|
|
// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> [[TMP1]], <8 x i32> <i32 0, i32 9, i32 2, i32 11, i32 4, i32 13, i32 6, i32 15>
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SHUFFLE_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_ppaireo_i8x8(
|
|
// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
|
|
// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> [[TMP1]], <8 x i32> <i32 0, i32 9, i32 2, i32 11, i32 4, i32 13, i32 6, i32 15>
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SHUFFLE_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
int8x8_t test_ppaireo_i8x8(int8x8_t rs1, int8x8_t rs2) {
|
|
return __riscv_ppaireo_i8x8(rs1, rs2);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_ppaireo_u8x8(
|
|
// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
|
|
// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> [[TMP1]], <8 x i32> <i32 0, i32 9, i32 2, i32 11, i32 4, i32 13, i32 6, i32 15>
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SHUFFLE_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_ppaireo_u8x8(
|
|
// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
|
|
// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> [[TMP1]], <8 x i32> <i32 0, i32 9, i32 2, i32 11, i32 4, i32 13, i32 6, i32 15>
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SHUFFLE_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
uint8x8_t test_ppaireo_u8x8(uint8x8_t rs1, uint8x8_t rs2) {
|
|
return __riscv_ppaireo_u8x8(rs1, rs2);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_ppairoe_i8x8(
|
|
// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
|
|
// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> [[TMP1]], <8 x i32> <i32 1, i32 8, i32 3, i32 10, i32 5, i32 12, i32 7, i32 14>
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SHUFFLE_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_ppairoe_i8x8(
|
|
// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
|
|
// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> [[TMP1]], <8 x i32> <i32 1, i32 8, i32 3, i32 10, i32 5, i32 12, i32 7, i32 14>
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SHUFFLE_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
int8x8_t test_ppairoe_i8x8(int8x8_t rs1, int8x8_t rs2) {
|
|
return __riscv_ppairoe_i8x8(rs1, rs2);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_ppairoe_u8x8(
|
|
// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
|
|
// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> [[TMP1]], <8 x i32> <i32 1, i32 8, i32 3, i32 10, i32 5, i32 12, i32 7, i32 14>
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SHUFFLE_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_ppairoe_u8x8(
|
|
// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
|
|
// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> [[TMP1]], <8 x i32> <i32 1, i32 8, i32 3, i32 10, i32 5, i32 12, i32 7, i32 14>
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SHUFFLE_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
uint8x8_t test_ppairoe_u8x8(uint8x8_t rs1, uint8x8_t rs2) {
|
|
return __riscv_ppairoe_u8x8(rs1, rs2);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_ppairo_i8x8(
|
|
// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
|
|
// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> [[TMP1]], <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15>
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SHUFFLE_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_ppairo_i8x8(
|
|
// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
|
|
// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> [[TMP1]], <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15>
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SHUFFLE_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
int8x8_t test_ppairo_i8x8(int8x8_t rs1, int8x8_t rs2) {
|
|
return __riscv_ppairo_i8x8(rs1, rs2);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_ppairo_u8x8(
|
|
// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
|
|
// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> [[TMP1]], <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15>
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SHUFFLE_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_ppairo_u8x8(
|
|
// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
|
|
// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> [[TMP1]], <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15>
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SHUFFLE_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
uint8x8_t test_ppairo_u8x8(uint8x8_t rs1, uint8x8_t rs2) {
|
|
return __riscv_ppairo_u8x8(rs1, rs2);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_ppaire_i16x4(
|
|
// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> [[TMP1]], <4 x i32> <i32 0, i32 4, i32 2, i32 6>
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_ppaire_i16x4(
|
|
// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> [[TMP1]], <4 x i32> <i32 0, i32 4, i32 2, i32 6>
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
int16x4_t test_ppaire_i16x4(int16x4_t rs1, int16x4_t rs2) {
|
|
return __riscv_ppaire_i16x4(rs1, rs2);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_ppaire_u16x4(
|
|
// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> [[TMP1]], <4 x i32> <i32 0, i32 4, i32 2, i32 6>
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_ppaire_u16x4(
|
|
// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> [[TMP1]], <4 x i32> <i32 0, i32 4, i32 2, i32 6>
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
uint16x4_t test_ppaire_u16x4(uint16x4_t rs1, uint16x4_t rs2) {
|
|
return __riscv_ppaire_u16x4(rs1, rs2);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_ppaireo_i16x4(
|
|
// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> [[TMP1]], <4 x i32> <i32 0, i32 5, i32 2, i32 7>
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_ppaireo_i16x4(
|
|
// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> [[TMP1]], <4 x i32> <i32 0, i32 5, i32 2, i32 7>
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
int16x4_t test_ppaireo_i16x4(int16x4_t rs1, int16x4_t rs2) {
|
|
return __riscv_ppaireo_i16x4(rs1, rs2);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_ppaireo_u16x4(
|
|
// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> [[TMP1]], <4 x i32> <i32 0, i32 5, i32 2, i32 7>
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_ppaireo_u16x4(
|
|
// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> [[TMP1]], <4 x i32> <i32 0, i32 5, i32 2, i32 7>
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
uint16x4_t test_ppaireo_u16x4(uint16x4_t rs1, uint16x4_t rs2) {
|
|
return __riscv_ppaireo_u16x4(rs1, rs2);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_ppairoe_i16x4(
|
|
// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> [[TMP1]], <4 x i32> <i32 1, i32 4, i32 3, i32 6>
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_ppairoe_i16x4(
|
|
// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> [[TMP1]], <4 x i32> <i32 1, i32 4, i32 3, i32 6>
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
int16x4_t test_ppairoe_i16x4(int16x4_t rs1, int16x4_t rs2) {
|
|
return __riscv_ppairoe_i16x4(rs1, rs2);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_ppairoe_u16x4(
|
|
// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> [[TMP1]], <4 x i32> <i32 1, i32 4, i32 3, i32 6>
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_ppairoe_u16x4(
|
|
// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> [[TMP1]], <4 x i32> <i32 1, i32 4, i32 3, i32 6>
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
uint16x4_t test_ppairoe_u16x4(uint16x4_t rs1, uint16x4_t rs2) {
|
|
return __riscv_ppairoe_u16x4(rs1, rs2);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_ppairo_i16x4(
|
|
// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> [[TMP1]], <4 x i32> <i32 1, i32 5, i32 3, i32 7>
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_ppairo_i16x4(
|
|
// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> [[TMP1]], <4 x i32> <i32 1, i32 5, i32 3, i32 7>
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
int16x4_t test_ppairo_i16x4(int16x4_t rs1, int16x4_t rs2) {
|
|
return __riscv_ppairo_i16x4(rs1, rs2);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_ppairo_u16x4(
|
|
// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> [[TMP1]], <4 x i32> <i32 1, i32 5, i32 3, i32 7>
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_ppairo_u16x4(
|
|
// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> [[TMP1]], <4 x i32> <i32 1, i32 5, i32 3, i32 7>
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
uint16x4_t test_ppairo_u16x4(uint16x4_t rs1, uint16x4_t rs2) {
|
|
return __riscv_ppairo_u16x4(rs1, rs2);
|
|
}
|
|
|
|
/* Packed Absolute Difference Sum (32-bit) */
|
|
// RV32-LABEL: define dso_local i32 @test_pabdsumu_u8x4_u32(
|
|
// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
|
|
// RV32-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.pabdsumu.i32.v4i8(<4 x i8> [[TMP0]], <4 x i8> [[TMP1]])
|
|
// RV32-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local signext i32 @test_pabdsumu_u8x4_u32(
|
|
// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
|
|
// RV64-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.pabdsumu.i32.v4i8(<4 x i8> [[TMP0]], <4 x i8> [[TMP1]])
|
|
// RV64-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
uint32_t test_pabdsumu_u8x4_u32(uint8x4_t rs1, uint8x4_t rs2) {
|
|
return __riscv_pabdsumu_u8x4_u32(rs1, rs2);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_pabdsumau_u8x4_u32(
|
|
// RV32-SAME: i32 noundef [[RD:%.*]], i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
|
|
// RV32-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.pabdsumau.i32.v4i8(i32 [[RD]], <4 x i8> [[TMP0]], <4 x i8> [[TMP1]])
|
|
// RV32-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local signext i32 @test_pabdsumau_u8x4_u32(
|
|
// RV64-SAME: i32 noundef signext [[RD:%.*]], i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
|
|
// RV64-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.pabdsumau.i32.v4i8(i32 [[RD]], <4 x i8> [[TMP0]], <4 x i8> [[TMP1]])
|
|
// RV64-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
uint32_t test_pabdsumau_u8x4_u32(uint32_t rd, uint8x4_t rs1, uint8x4_t rs2) {
|
|
return __riscv_pabdsumau_u8x4_u32(rd, rs1, rs2);
|
|
}
|
|
|
|
/* Packed Absolute Difference Sum (64-bit) */
|
|
// RV32-LABEL: define dso_local i32 @test_pabdsumu_u8x8_u32(
|
|
// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
|
|
// RV32-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.pabdsumu.i32.v8i8(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]])
|
|
// RV32-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local signext i32 @test_pabdsumu_u8x8_u32(
|
|
// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
|
|
// RV64-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.pabdsumu.i32.v8i8(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]])
|
|
// RV64-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
uint32_t test_pabdsumu_u8x8_u32(uint8x8_t rs1, uint8x8_t rs2) {
|
|
return __riscv_pabdsumu_u8x8_u32(rs1, rs2);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pabdsumu_u8x8_u64(
|
|
// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
|
|
// RV32-NEXT: [[TMP2:%.*]] = call i64 @llvm.riscv.pabdsumu.i64.v8i8(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]])
|
|
// RV32-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pabdsumu_u8x8_u64(
|
|
// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
|
|
// RV64-NEXT: [[TMP2:%.*]] = call i64 @llvm.riscv.pabdsumu.i64.v8i8(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]])
|
|
// RV64-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
uint64_t test_pabdsumu_u8x8_u64(uint8x8_t rs1, uint8x8_t rs2) {
|
|
return __riscv_pabdsumu_u8x8_u64(rs1, rs2);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_pabdsumau_u8x8_u32(
|
|
// RV32-SAME: i32 noundef [[RD:%.*]], i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
|
|
// RV32-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.pabdsumau.i32.v8i8(i32 [[RD]], <8 x i8> [[TMP0]], <8 x i8> [[TMP1]])
|
|
// RV32-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local signext i32 @test_pabdsumau_u8x8_u32(
|
|
// RV64-SAME: i32 noundef signext [[RD:%.*]], i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
|
|
// RV64-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.pabdsumau.i32.v8i8(i32 [[RD]], <8 x i8> [[TMP0]], <8 x i8> [[TMP1]])
|
|
// RV64-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
uint32_t test_pabdsumau_u8x8_u32(uint32_t rd, uint8x8_t rs1, uint8x8_t rs2) {
|
|
return __riscv_pabdsumau_u8x8_u32(rd, rs1, rs2);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pabdsumau_u8x8_u64(
|
|
// RV32-SAME: i64 noundef [[RD:%.*]], i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
|
|
// RV32-NEXT: [[TMP2:%.*]] = call i64 @llvm.riscv.pabdsumau.i64.v8i8(i64 [[RD]], <8 x i8> [[TMP0]], <8 x i8> [[TMP1]])
|
|
// RV32-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pabdsumau_u8x8_u64(
|
|
// RV64-SAME: i64 noundef [[RD:%.*]], i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
|
|
// RV64-NEXT: [[TMP2:%.*]] = call i64 @llvm.riscv.pabdsumau.i64.v8i8(i64 [[RD]], <8 x i8> [[TMP0]], <8 x i8> [[TMP1]])
|
|
// RV64-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
uint64_t test_pabdsumau_u8x8_u64(uint64_t rd, uint8x8_t rs1, uint8x8_t rs2) {
|
|
return __riscv_pabdsumau_u8x8_u64(rd, rs1, rs2);
|
|
}
|
|
|
|
/* Packed Saturating Absolute Value (32-bit) */
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_psabs_i8x4(
|
|
// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
|
|
// RV32-NEXT: [[TMP1:%.*]] = call <4 x i8> @llvm.riscv.psabs.v4i8(<4 x i8> [[TMP0]])
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[TMP1]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_psabs_i8x4(
|
|
// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
|
|
// RV64-NEXT: [[TMP1:%.*]] = call <4 x i8> @llvm.riscv.psabs.v4i8(<4 x i8> [[TMP0]])
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[TMP1]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
int8x4_t test_psabs_i8x4(int8x4_t rs1) {
|
|
return __riscv_psabs_i8x4(rs1);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_psabs_i16x2(
|
|
// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
|
|
// RV32-NEXT: [[TMP1:%.*]] = call <2 x i16> @llvm.riscv.psabs.v2i16(<2 x i16> [[TMP0]])
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[TMP1]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_psabs_i16x2(
|
|
// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
|
|
// RV64-NEXT: [[TMP1:%.*]] = call <2 x i16> @llvm.riscv.psabs.v2i16(<2 x i16> [[TMP0]])
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <2 x i16> [[TMP1]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
int16x2_t test_psabs_i16x2(int16x2_t rs1) {
|
|
return __riscv_psabs_i16x2(rs1);
|
|
}
|
|
|
|
/* Packed Saturating Absolute Value (64-bit) */
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_psabs_i8x8(
|
|
// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
|
|
// RV32-NEXT: [[TMP1:%.*]] = call <8 x i8> @llvm.riscv.psabs.v8i8(<8 x i8> [[TMP0]])
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP1]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_psabs_i8x8(
|
|
// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
|
|
// RV64-NEXT: [[TMP1:%.*]] = call <8 x i8> @llvm.riscv.psabs.v8i8(<8 x i8> [[TMP0]])
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP1]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
int8x8_t test_psabs_i8x8(int8x8_t rs1) {
|
|
return __riscv_psabs_i8x8(rs1);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_psabs_i16x4(
|
|
// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[TMP1:%.*]] = call <4 x i16> @llvm.riscv.psabs.v4i16(<4 x i16> [[TMP0]])
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[TMP1]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_psabs_i16x4(
|
|
// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[TMP1:%.*]] = call <4 x i16> @llvm.riscv.psabs.v4i16(<4 x i16> [[TMP0]])
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[TMP1]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
int16x4_t test_psabs_i16x4(int16x4_t rs1) {
|
|
return __riscv_psabs_i16x4(rs1);
|
|
}
|
|
|
|
/* Packed Widening Convert */
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pwcvt_i16x4(
|
|
// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
|
|
// RV32-NEXT: [[CONV_I:%.*]] = sext <4 x i8> [[TMP0]] to <4 x i16>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[CONV_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP1]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pwcvt_i16x4(
|
|
// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
|
|
// RV64-NEXT: [[CONV_I:%.*]] = sext <4 x i8> [[TMP0]] to <4 x i16>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[CONV_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP1]]
|
|
//
|
|
int16x4_t test_pwcvt_i16x4(int8x4_t rs1) {
|
|
return __riscv_pwcvt_i16x4(rs1);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pwcvt_i32x2(
|
|
// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
|
|
// RV32-NEXT: [[CONV_I:%.*]] = sext <2 x i16> [[TMP0]] to <2 x i32>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[CONV_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP1]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pwcvt_i32x2(
|
|
// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
|
|
// RV64-NEXT: [[CONV_I:%.*]] = sext <2 x i16> [[TMP0]] to <2 x i32>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[CONV_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP1]]
|
|
//
|
|
int32x2_t test_pwcvt_i32x2(int16x2_t rs1) {
|
|
return __riscv_pwcvt_i32x2(rs1);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pwcvtu_u16x4(
|
|
// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
|
|
// RV32-NEXT: [[CONV_I:%.*]] = zext <4 x i8> [[TMP0]] to <4 x i16>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[CONV_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP1]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pwcvtu_u16x4(
|
|
// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
|
|
// RV64-NEXT: [[CONV_I:%.*]] = zext <4 x i8> [[TMP0]] to <4 x i16>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[CONV_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP1]]
|
|
//
|
|
uint16x4_t test_pwcvtu_u16x4(uint8x4_t rs1) {
|
|
return __riscv_pwcvtu_u16x4(rs1);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pwcvtu_u32x2(
|
|
// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
|
|
// RV32-NEXT: [[CONV_I:%.*]] = zext <2 x i16> [[TMP0]] to <2 x i32>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[CONV_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP1]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pwcvtu_u32x2(
|
|
// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
|
|
// RV64-NEXT: [[CONV_I:%.*]] = zext <2 x i16> [[TMP0]] to <2 x i32>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[CONV_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP1]]
|
|
//
|
|
uint32x2_t test_pwcvtu_u32x2(uint16x2_t rs1) {
|
|
return __riscv_pwcvtu_u32x2(rs1);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pwcvth_i16x4(
|
|
// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
|
|
// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i8> zeroinitializer, <4 x i8> [[TMP0]], <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[SHUFFLE_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP1]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pwcvth_i16x4(
|
|
// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
|
|
// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i8> zeroinitializer, <4 x i8> [[TMP0]], <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[SHUFFLE_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP1]]
|
|
//
|
|
int16x4_t test_pwcvth_i16x4(int8x4_t rs1) {
|
|
return __riscv_pwcvth_i16x4(rs1);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pwcvth_u16x4(
|
|
// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
|
|
// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i8> zeroinitializer, <4 x i8> [[TMP0]], <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[SHUFFLE_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP1]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pwcvth_u16x4(
|
|
// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
|
|
// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i8> zeroinitializer, <4 x i8> [[TMP0]], <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[SHUFFLE_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP1]]
|
|
//
|
|
uint16x4_t test_pwcvth_u16x4(uint8x4_t rs1) {
|
|
return __riscv_pwcvth_u16x4(rs1);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pwcvth_i32x2(
|
|
// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
|
|
// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <2 x i16> zeroinitializer, <2 x i16> [[TMP0]], <4 x i32> <i32 0, i32 2, i32 1, i32 3>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP1]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pwcvth_i32x2(
|
|
// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
|
|
// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <2 x i16> zeroinitializer, <2 x i16> [[TMP0]], <4 x i32> <i32 0, i32 2, i32 1, i32 3>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP1]]
|
|
//
|
|
int32x2_t test_pwcvth_i32x2(int16x2_t rs1) {
|
|
return __riscv_pwcvth_i32x2(rs1);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pwcvth_u32x2(
|
|
// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
|
|
// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <2 x i16> zeroinitializer, <2 x i16> [[TMP0]], <4 x i32> <i32 0, i32 2, i32 1, i32 3>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP1]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pwcvth_u32x2(
|
|
// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
|
|
// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <2 x i16> zeroinitializer, <2 x i16> [[TMP0]], <4 x i32> <i32 0, i32 2, i32 1, i32 3>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP1]]
|
|
//
|
|
uint32x2_t test_pwcvth_u32x2(uint16x2_t rs1) {
|
|
return __riscv_pwcvth_u32x2(rs1);
|
|
}
|
|
|
|
/* Packed Narrowing Convert */
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_pncvt_i8x4(
|
|
// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[CONV_I:%.*]] = trunc <4 x i16> [[TMP0]] to <4 x i8>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast <4 x i8> [[CONV_I]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP1]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_pncvt_i8x4(
|
|
// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[CONV_I:%.*]] = trunc <4 x i16> [[TMP0]] to <4 x i8>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast <4 x i8> [[CONV_I]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP1]]
|
|
//
|
|
int8x4_t test_pncvt_i8x4(int16x4_t rs1) { return __riscv_pncvt_i8x4(rs1); }
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_pncvt_u8x4(
|
|
// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[CONV_I:%.*]] = trunc <4 x i16> [[TMP0]] to <4 x i8>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast <4 x i8> [[CONV_I]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP1]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_pncvt_u8x4(
|
|
// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[CONV_I:%.*]] = trunc <4 x i16> [[TMP0]] to <4 x i8>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast <4 x i8> [[CONV_I]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP1]]
|
|
//
|
|
uint8x4_t test_pncvt_u8x4(uint16x4_t rs1) { return __riscv_pncvt_u8x4(rs1); }
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_pncvt_i16x2(
|
|
// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
|
|
// RV32-NEXT: [[CONV_I:%.*]] = trunc <2 x i32> [[TMP0]] to <2 x i16>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast <2 x i16> [[CONV_I]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP1]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_pncvt_i16x2(
|
|
// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
|
|
// RV64-NEXT: [[CONV_I:%.*]] = trunc <2 x i32> [[TMP0]] to <2 x i16>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast <2 x i16> [[CONV_I]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP1]]
|
|
//
|
|
int16x2_t test_pncvt_i16x2(int32x2_t rs1) { return __riscv_pncvt_i16x2(rs1); }
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_pncvt_u16x2(
|
|
// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
|
|
// RV32-NEXT: [[CONV_I:%.*]] = trunc <2 x i32> [[TMP0]] to <2 x i16>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast <2 x i16> [[CONV_I]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP1]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_pncvt_u16x2(
|
|
// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
|
|
// RV64-NEXT: [[CONV_I:%.*]] = trunc <2 x i32> [[TMP0]] to <2 x i16>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast <2 x i16> [[CONV_I]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP1]]
|
|
//
|
|
uint16x2_t test_pncvt_u16x2(uint32x2_t rs1) {
|
|
return __riscv_pncvt_u16x2(rs1);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_pncvth_i8x4(
|
|
// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
|
|
// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast <4 x i8> [[SHUFFLE_I]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP1]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_pncvth_i8x4(
|
|
// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
|
|
// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast <4 x i8> [[SHUFFLE_I]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP1]]
|
|
//
|
|
int8x4_t test_pncvth_i8x4(int16x4_t rs1) { return __riscv_pncvth_i8x4(rs1); }
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_pncvth_u8x4(
|
|
// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
|
|
// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast <4 x i8> [[SHUFFLE_I]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP1]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_pncvth_u8x4(
|
|
// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
|
|
// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast <4 x i8> [[SHUFFLE_I]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP1]]
|
|
//
|
|
uint8x4_t test_pncvth_u8x4(uint16x4_t rs1) {
|
|
return __riscv_pncvth_u8x4(rs1);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_pncvth_i16x2(
|
|
// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> poison, <2 x i32> <i32 1, i32 3>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast <2 x i16> [[SHUFFLE_I]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP1]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_pncvth_i16x2(
|
|
// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> poison, <2 x i32> <i32 1, i32 3>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast <2 x i16> [[SHUFFLE_I]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP1]]
|
|
//
|
|
int16x2_t test_pncvth_i16x2(int32x2_t rs1) {
|
|
return __riscv_pncvth_i16x2(rs1);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_pncvth_u16x2(
|
|
// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> poison, <2 x i32> <i32 1, i32 3>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast <2 x i16> [[SHUFFLE_I]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP1]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_pncvth_u16x2(
|
|
// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> poison, <2 x i32> <i32 1, i32 3>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast <2 x i16> [[SHUFFLE_I]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP1]]
|
|
//
|
|
uint16x2_t test_pncvth_u16x2(uint32x2_t rs1) {
|
|
return __riscv_pncvth_u16x2(rs1);
|
|
}
|
|
|
|
/* Packed "Q-format" Multiplication (32-bit) */
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_pmulq_i16x2(
|
|
// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
|
|
// RV32-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.pmulq.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
|
|
// RV32-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP3]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_pmulq_i16x2(
|
|
// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
|
|
// RV64-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.pmulq.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
|
|
// RV64-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP3]]
|
|
//
|
|
int16x2_t test_pmulq_i16x2(int16x2_t rs1, int16x2_t rs2) {
|
|
return __riscv_pmulq_i16x2(rs1, rs2);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_pmulqr_i16x2(
|
|
// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
|
|
// RV32-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.pmulqr.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
|
|
// RV32-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP3]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_pmulqr_i16x2(
|
|
// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
|
|
// RV64-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.pmulqr.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
|
|
// RV64-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP3]]
|
|
//
|
|
int16x2_t test_pmulqr_i16x2(int16x2_t rs1, int16x2_t rs2) {
|
|
return __riscv_pmulqr_i16x2(rs1, rs2);
|
|
}
|
|
|
|
/* Packed "Q-format" Multiplication (64-bit) */
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pmulq_i16x4(
|
|
// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.pmulq.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
|
|
// RV32-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP3]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pmulq_i16x4(
|
|
// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.pmulq.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
|
|
// RV64-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP3]]
|
|
//
|
|
int16x4_t test_pmulq_i16x4(int16x4_t rs1, int16x4_t rs2) {
|
|
return __riscv_pmulq_i16x4(rs1, rs2);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pmulqr_i16x4(
|
|
// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.pmulqr.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
|
|
// RV32-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP3]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pmulqr_i16x4(
|
|
// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.pmulqr.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
|
|
// RV64-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP3]]
|
|
//
|
|
int16x4_t test_pmulqr_i16x4(int16x4_t rs1, int16x4_t rs2) {
|
|
return __riscv_pmulqr_i16x4(rs1, rs2);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pmulq_i32x2(
|
|
// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <2 x i32>
|
|
// RV32-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.pmulq.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
|
|
// RV32-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP3]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pmulq_i32x2(
|
|
// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <2 x i32>
|
|
// RV64-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.pmulq.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
|
|
// RV64-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP3]]
|
|
//
|
|
int32x2_t test_pmulq_i32x2(int32x2_t rs1, int32x2_t rs2) {
|
|
return __riscv_pmulq_i32x2(rs1, rs2);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pmulqr_i32x2(
|
|
// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <2 x i32>
|
|
// RV32-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.pmulqr.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
|
|
// RV32-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP3]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pmulqr_i32x2(
|
|
// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <2 x i32>
|
|
// RV64-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.riscv.pmulqr.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
|
|
// RV64-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP3]]
|
|
//
|
|
int32x2_t test_pmulqr_i32x2(int32x2_t rs1, int32x2_t rs2) {
|
|
return __riscv_pmulqr_i32x2(rs1, rs2);
|
|
}
|
|
|
|
/* Reinterpret Casts, Packed <-> Scalar (32-bit) */
|
|
// RV32-LABEL: define dso_local i32 @test_preinterpret_u8x4_u32(
|
|
// RV32-SAME: i32 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: ret i32 [[X_COERCE]]
|
|
//
|
|
// RV64-LABEL: define dso_local signext i32 @test_preinterpret_u8x4_u32(
|
|
// RV64-SAME: i32 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: ret i32 [[X_COERCE]]
|
|
//
|
|
uint32_t test_preinterpret_u8x4_u32(uint8x4_t x) {
|
|
return __riscv_preinterpret_u8x4_u32(x);
|
|
}
|
|
// RV32-LABEL: define dso_local i32 @test_preinterpret_u16x2_u32(
|
|
// RV32-SAME: i32 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: ret i32 [[X_COERCE]]
|
|
//
|
|
// RV64-LABEL: define dso_local signext i32 @test_preinterpret_u16x2_u32(
|
|
// RV64-SAME: i32 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: ret i32 [[X_COERCE]]
|
|
//
|
|
uint32_t test_preinterpret_u16x2_u32(uint16x2_t x) {
|
|
return __riscv_preinterpret_u16x2_u32(x);
|
|
}
|
|
// RV32-LABEL: define dso_local i32 @test_preinterpret_i8x4_u32(
|
|
// RV32-SAME: i32 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: ret i32 [[X_COERCE]]
|
|
//
|
|
// RV64-LABEL: define dso_local signext i32 @test_preinterpret_i8x4_u32(
|
|
// RV64-SAME: i32 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: ret i32 [[X_COERCE]]
|
|
//
|
|
uint32_t test_preinterpret_i8x4_u32(int8x4_t x) {
|
|
return __riscv_preinterpret_i8x4_u32(x);
|
|
}
|
|
// RV32-LABEL: define dso_local i32 @test_preinterpret_i16x2_u32(
|
|
// RV32-SAME: i32 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: ret i32 [[X_COERCE]]
|
|
//
|
|
// RV64-LABEL: define dso_local signext i32 @test_preinterpret_i16x2_u32(
|
|
// RV64-SAME: i32 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: ret i32 [[X_COERCE]]
|
|
//
|
|
uint32_t test_preinterpret_i16x2_u32(int16x2_t x) {
|
|
return __riscv_preinterpret_i16x2_u32(x);
|
|
}
|
|
// RV32-LABEL: define dso_local i32 @test_preinterpret_u8x4_i32(
|
|
// RV32-SAME: i32 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: ret i32 [[X_COERCE]]
|
|
//
|
|
// RV64-LABEL: define dso_local signext i32 @test_preinterpret_u8x4_i32(
|
|
// RV64-SAME: i32 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: ret i32 [[X_COERCE]]
|
|
//
|
|
int32_t test_preinterpret_u8x4_i32(uint8x4_t x) {
|
|
return __riscv_preinterpret_u8x4_i32(x);
|
|
}
|
|
// RV32-LABEL: define dso_local i32 @test_preinterpret_u16x2_i32(
|
|
// RV32-SAME: i32 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: ret i32 [[X_COERCE]]
|
|
//
|
|
// RV64-LABEL: define dso_local signext i32 @test_preinterpret_u16x2_i32(
|
|
// RV64-SAME: i32 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: ret i32 [[X_COERCE]]
|
|
//
|
|
int32_t test_preinterpret_u16x2_i32(uint16x2_t x) {
|
|
return __riscv_preinterpret_u16x2_i32(x);
|
|
}
|
|
// RV32-LABEL: define dso_local i32 @test_preinterpret_i8x4_i32(
|
|
// RV32-SAME: i32 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: ret i32 [[X_COERCE]]
|
|
//
|
|
// RV64-LABEL: define dso_local signext i32 @test_preinterpret_i8x4_i32(
|
|
// RV64-SAME: i32 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: ret i32 [[X_COERCE]]
|
|
//
|
|
int32_t test_preinterpret_i8x4_i32(int8x4_t x) {
|
|
return __riscv_preinterpret_i8x4_i32(x);
|
|
}
|
|
// RV32-LABEL: define dso_local i32 @test_preinterpret_i16x2_i32(
|
|
// RV32-SAME: i32 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: ret i32 [[X_COERCE]]
|
|
//
|
|
// RV64-LABEL: define dso_local signext i32 @test_preinterpret_i16x2_i32(
|
|
// RV64-SAME: i32 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: ret i32 [[X_COERCE]]
|
|
//
|
|
int32_t test_preinterpret_i16x2_i32(int16x2_t x) {
|
|
return __riscv_preinterpret_i16x2_i32(x);
|
|
}
|
|
// RV32-LABEL: define dso_local i32 @test_preinterpret_u32_u8x4(
|
|
// RV32-SAME: i32 noundef [[X:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: ret i32 [[X]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_preinterpret_u32_u8x4(
|
|
// RV64-SAME: i32 noundef signext [[X:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: ret i32 [[X]]
|
|
//
|
|
uint8x4_t test_preinterpret_u32_u8x4(uint32_t x) {
|
|
return __riscv_preinterpret_u32_u8x4(x);
|
|
}
|
|
// RV32-LABEL: define dso_local i32 @test_preinterpret_u32_u16x2(
|
|
// RV32-SAME: i32 noundef [[X:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: ret i32 [[X]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_preinterpret_u32_u16x2(
|
|
// RV64-SAME: i32 noundef signext [[X:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: ret i32 [[X]]
|
|
//
|
|
uint16x2_t test_preinterpret_u32_u16x2(uint32_t x) {
|
|
return __riscv_preinterpret_u32_u16x2(x);
|
|
}
|
|
// RV32-LABEL: define dso_local i32 @test_preinterpret_u32_i8x4(
|
|
// RV32-SAME: i32 noundef [[X:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: ret i32 [[X]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_preinterpret_u32_i8x4(
|
|
// RV64-SAME: i32 noundef signext [[X:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: ret i32 [[X]]
|
|
//
|
|
int8x4_t test_preinterpret_u32_i8x4(uint32_t x) {
|
|
return __riscv_preinterpret_u32_i8x4(x);
|
|
}
|
|
// RV32-LABEL: define dso_local i32 @test_preinterpret_u32_i16x2(
|
|
// RV32-SAME: i32 noundef [[X:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: ret i32 [[X]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_preinterpret_u32_i16x2(
|
|
// RV64-SAME: i32 noundef signext [[X:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: ret i32 [[X]]
|
|
//
|
|
int16x2_t test_preinterpret_u32_i16x2(uint32_t x) {
|
|
return __riscv_preinterpret_u32_i16x2(x);
|
|
}
|
|
// RV32-LABEL: define dso_local i32 @test_preinterpret_i32_u8x4(
|
|
// RV32-SAME: i32 noundef [[X:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: ret i32 [[X]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_preinterpret_i32_u8x4(
|
|
// RV64-SAME: i32 noundef signext [[X:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: ret i32 [[X]]
|
|
//
|
|
uint8x4_t test_preinterpret_i32_u8x4(int32_t x) {
|
|
return __riscv_preinterpret_i32_u8x4(x);
|
|
}
|
|
// RV32-LABEL: define dso_local i32 @test_preinterpret_i32_u16x2(
|
|
// RV32-SAME: i32 noundef [[X:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: ret i32 [[X]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_preinterpret_i32_u16x2(
|
|
// RV64-SAME: i32 noundef signext [[X:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: ret i32 [[X]]
|
|
//
|
|
uint16x2_t test_preinterpret_i32_u16x2(int32_t x) {
|
|
return __riscv_preinterpret_i32_u16x2(x);
|
|
}
|
|
// RV32-LABEL: define dso_local i32 @test_preinterpret_i32_i8x4(
|
|
// RV32-SAME: i32 noundef [[X:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: ret i32 [[X]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_preinterpret_i32_i8x4(
|
|
// RV64-SAME: i32 noundef signext [[X:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: ret i32 [[X]]
|
|
//
|
|
int8x4_t test_preinterpret_i32_i8x4(int32_t x) {
|
|
return __riscv_preinterpret_i32_i8x4(x);
|
|
}
|
|
// RV32-LABEL: define dso_local i32 @test_preinterpret_i32_i16x2(
|
|
// RV32-SAME: i32 noundef [[X:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: ret i32 [[X]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_preinterpret_i32_i16x2(
|
|
// RV64-SAME: i32 noundef signext [[X:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: ret i32 [[X]]
|
|
//
|
|
int16x2_t test_preinterpret_i32_i16x2(int32_t x) {
|
|
return __riscv_preinterpret_i32_i16x2(x);
|
|
}
|
|
|
|
/* Reinterpret Casts, Packed <-> Scalar (64-bit) */
|
|
// RV32-LABEL: define dso_local i64 @test_preinterpret_u8x8_u64(
|
|
// RV32-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: ret i64 [[X_COERCE]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_preinterpret_u8x8_u64(
|
|
// RV64-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: ret i64 [[X_COERCE]]
|
|
//
|
|
uint64_t test_preinterpret_u8x8_u64(uint8x8_t x) {
|
|
return __riscv_preinterpret_u8x8_u64(x);
|
|
}
|
|
// RV32-LABEL: define dso_local i64 @test_preinterpret_u16x4_u64(
|
|
// RV32-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: ret i64 [[X_COERCE]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_preinterpret_u16x4_u64(
|
|
// RV64-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: ret i64 [[X_COERCE]]
|
|
//
|
|
uint64_t test_preinterpret_u16x4_u64(uint16x4_t x) {
|
|
return __riscv_preinterpret_u16x4_u64(x);
|
|
}
|
|
// RV32-LABEL: define dso_local i64 @test_preinterpret_u32x2_u64(
|
|
// RV32-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: ret i64 [[X_COERCE]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_preinterpret_u32x2_u64(
|
|
// RV64-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: ret i64 [[X_COERCE]]
|
|
//
|
|
uint64_t test_preinterpret_u32x2_u64(uint32x2_t x) {
|
|
return __riscv_preinterpret_u32x2_u64(x);
|
|
}
|
|
// RV32-LABEL: define dso_local i64 @test_preinterpret_i8x8_u64(
|
|
// RV32-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: ret i64 [[X_COERCE]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_preinterpret_i8x8_u64(
|
|
// RV64-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: ret i64 [[X_COERCE]]
|
|
//
|
|
uint64_t test_preinterpret_i8x8_u64(int8x8_t x) {
|
|
return __riscv_preinterpret_i8x8_u64(x);
|
|
}
|
|
// RV32-LABEL: define dso_local i64 @test_preinterpret_i16x4_u64(
|
|
// RV32-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: ret i64 [[X_COERCE]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_preinterpret_i16x4_u64(
|
|
// RV64-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: ret i64 [[X_COERCE]]
|
|
//
|
|
uint64_t test_preinterpret_i16x4_u64(int16x4_t x) {
|
|
return __riscv_preinterpret_i16x4_u64(x);
|
|
}
|
|
// RV32-LABEL: define dso_local i64 @test_preinterpret_i32x2_u64(
|
|
// RV32-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: ret i64 [[X_COERCE]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_preinterpret_i32x2_u64(
|
|
// RV64-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: ret i64 [[X_COERCE]]
|
|
//
|
|
uint64_t test_preinterpret_i32x2_u64(int32x2_t x) {
|
|
return __riscv_preinterpret_i32x2_u64(x);
|
|
}
|
|
// RV32-LABEL: define dso_local i64 @test_preinterpret_u8x8_i64(
|
|
// RV32-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: ret i64 [[X_COERCE]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_preinterpret_u8x8_i64(
|
|
// RV64-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: ret i64 [[X_COERCE]]
|
|
//
|
|
int64_t test_preinterpret_u8x8_i64(uint8x8_t x) {
|
|
return __riscv_preinterpret_u8x8_i64(x);
|
|
}
|
|
// RV32-LABEL: define dso_local i64 @test_preinterpret_u16x4_i64(
|
|
// RV32-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: ret i64 [[X_COERCE]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_preinterpret_u16x4_i64(
|
|
// RV64-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: ret i64 [[X_COERCE]]
|
|
//
|
|
int64_t test_preinterpret_u16x4_i64(uint16x4_t x) {
|
|
return __riscv_preinterpret_u16x4_i64(x);
|
|
}
|
|
// RV32-LABEL: define dso_local i64 @test_preinterpret_u32x2_i64(
|
|
// RV32-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: ret i64 [[X_COERCE]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_preinterpret_u32x2_i64(
|
|
// RV64-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: ret i64 [[X_COERCE]]
|
|
//
|
|
int64_t test_preinterpret_u32x2_i64(uint32x2_t x) {
|
|
return __riscv_preinterpret_u32x2_i64(x);
|
|
}
|
|
// RV32-LABEL: define dso_local i64 @test_preinterpret_i8x8_i64(
|
|
// RV32-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: ret i64 [[X_COERCE]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_preinterpret_i8x8_i64(
|
|
// RV64-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: ret i64 [[X_COERCE]]
|
|
//
|
|
int64_t test_preinterpret_i8x8_i64(int8x8_t x) {
|
|
return __riscv_preinterpret_i8x8_i64(x);
|
|
}
|
|
// RV32-LABEL: define dso_local i64 @test_preinterpret_i16x4_i64(
|
|
// RV32-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: ret i64 [[X_COERCE]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_preinterpret_i16x4_i64(
|
|
// RV64-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: ret i64 [[X_COERCE]]
|
|
//
|
|
int64_t test_preinterpret_i16x4_i64(int16x4_t x) {
|
|
return __riscv_preinterpret_i16x4_i64(x);
|
|
}
|
|
// RV32-LABEL: define dso_local i64 @test_preinterpret_i32x2_i64(
|
|
// RV32-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: ret i64 [[X_COERCE]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_preinterpret_i32x2_i64(
|
|
// RV64-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: ret i64 [[X_COERCE]]
|
|
//
|
|
int64_t test_preinterpret_i32x2_i64(int32x2_t x) {
|
|
return __riscv_preinterpret_i32x2_i64(x);
|
|
}
|
|
// RV32-LABEL: define dso_local i64 @test_preinterpret_u64_u8x8(
|
|
// RV32-SAME: i64 noundef [[X:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: ret i64 [[X]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_preinterpret_u64_u8x8(
|
|
// RV64-SAME: i64 noundef [[X:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: ret i64 [[X]]
|
|
//
|
|
uint8x8_t test_preinterpret_u64_u8x8(uint64_t x) {
|
|
return __riscv_preinterpret_u64_u8x8(x);
|
|
}
|
|
// RV32-LABEL: define dso_local i64 @test_preinterpret_u64_u16x4(
|
|
// RV32-SAME: i64 noundef [[X:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: ret i64 [[X]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_preinterpret_u64_u16x4(
|
|
// RV64-SAME: i64 noundef [[X:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: ret i64 [[X]]
|
|
//
|
|
uint16x4_t test_preinterpret_u64_u16x4(uint64_t x) {
|
|
return __riscv_preinterpret_u64_u16x4(x);
|
|
}
|
|
// RV32-LABEL: define dso_local i64 @test_preinterpret_u64_u32x2(
|
|
// RV32-SAME: i64 noundef [[X:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: ret i64 [[X]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_preinterpret_u64_u32x2(
|
|
// RV64-SAME: i64 noundef [[X:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: ret i64 [[X]]
|
|
//
|
|
uint32x2_t test_preinterpret_u64_u32x2(uint64_t x) {
|
|
return __riscv_preinterpret_u64_u32x2(x);
|
|
}
|
|
// RV32-LABEL: define dso_local i64 @test_preinterpret_u64_i8x8(
|
|
// RV32-SAME: i64 noundef [[X:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: ret i64 [[X]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_preinterpret_u64_i8x8(
|
|
// RV64-SAME: i64 noundef [[X:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: ret i64 [[X]]
|
|
//
|
|
int8x8_t test_preinterpret_u64_i8x8(uint64_t x) {
|
|
return __riscv_preinterpret_u64_i8x8(x);
|
|
}
|
|
// RV32-LABEL: define dso_local i64 @test_preinterpret_u64_i16x4(
|
|
// RV32-SAME: i64 noundef [[X:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: ret i64 [[X]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_preinterpret_u64_i16x4(
|
|
// RV64-SAME: i64 noundef [[X:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: ret i64 [[X]]
|
|
//
|
|
int16x4_t test_preinterpret_u64_i16x4(uint64_t x) {
|
|
return __riscv_preinterpret_u64_i16x4(x);
|
|
}
|
|
// RV32-LABEL: define dso_local i64 @test_preinterpret_u64_i32x2(
|
|
// RV32-SAME: i64 noundef [[X:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: ret i64 [[X]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_preinterpret_u64_i32x2(
|
|
// RV64-SAME: i64 noundef [[X:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: ret i64 [[X]]
|
|
//
|
|
int32x2_t test_preinterpret_u64_i32x2(uint64_t x) {
|
|
return __riscv_preinterpret_u64_i32x2(x);
|
|
}
|
|
// RV32-LABEL: define dso_local i64 @test_preinterpret_i64_u8x8(
|
|
// RV32-SAME: i64 noundef [[X:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: ret i64 [[X]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_preinterpret_i64_u8x8(
|
|
// RV64-SAME: i64 noundef [[X:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: ret i64 [[X]]
|
|
//
|
|
uint8x8_t test_preinterpret_i64_u8x8(int64_t x) {
|
|
return __riscv_preinterpret_i64_u8x8(x);
|
|
}
|
|
// RV32-LABEL: define dso_local i64 @test_preinterpret_i64_u16x4(
|
|
// RV32-SAME: i64 noundef [[X:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: ret i64 [[X]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_preinterpret_i64_u16x4(
|
|
// RV64-SAME: i64 noundef [[X:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: ret i64 [[X]]
|
|
//
|
|
uint16x4_t test_preinterpret_i64_u16x4(int64_t x) {
|
|
return __riscv_preinterpret_i64_u16x4(x);
|
|
}
|
|
// RV32-LABEL: define dso_local i64 @test_preinterpret_i64_u32x2(
|
|
// RV32-SAME: i64 noundef [[X:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: ret i64 [[X]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_preinterpret_i64_u32x2(
|
|
// RV64-SAME: i64 noundef [[X:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: ret i64 [[X]]
|
|
//
|
|
uint32x2_t test_preinterpret_i64_u32x2(int64_t x) {
|
|
return __riscv_preinterpret_i64_u32x2(x);
|
|
}
|
|
// RV32-LABEL: define dso_local i64 @test_preinterpret_i64_i8x8(
|
|
// RV32-SAME: i64 noundef [[X:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: ret i64 [[X]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_preinterpret_i64_i8x8(
|
|
// RV64-SAME: i64 noundef [[X:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: ret i64 [[X]]
|
|
//
|
|
int8x8_t test_preinterpret_i64_i8x8(int64_t x) {
|
|
return __riscv_preinterpret_i64_i8x8(x);
|
|
}
|
|
// RV32-LABEL: define dso_local i64 @test_preinterpret_i64_i16x4(
|
|
// RV32-SAME: i64 noundef [[X:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: ret i64 [[X]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_preinterpret_i64_i16x4(
|
|
// RV64-SAME: i64 noundef [[X:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: ret i64 [[X]]
|
|
//
|
|
int16x4_t test_preinterpret_i64_i16x4(int64_t x) {
|
|
return __riscv_preinterpret_i64_i16x4(x);
|
|
}
|
|
// RV32-LABEL: define dso_local i64 @test_preinterpret_i64_i32x2(
|
|
// RV32-SAME: i64 noundef [[X:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: ret i64 [[X]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_preinterpret_i64_i32x2(
|
|
// RV64-SAME: i64 noundef [[X:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: ret i64 [[X]]
|
|
//
|
|
int32x2_t test_preinterpret_i64_i32x2(int64_t x) {
|
|
return __riscv_preinterpret_i64_i32x2(x);
|
|
}
|
|
|
|
/* Reinterpret Casts, Packed <-> Packed (32-bit) */
|
|
// RV32-LABEL: define dso_local i32 @test_preinterpret_i8x4_u8x4(
|
|
// RV32-SAME: i32 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: ret i32 [[X_COERCE]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_preinterpret_i8x4_u8x4(
|
|
// RV64-SAME: i32 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: ret i32 [[X_COERCE]]
|
|
//
|
|
uint8x4_t test_preinterpret_i8x4_u8x4(int8x4_t x) {
|
|
return __riscv_preinterpret_i8x4_u8x4(x);
|
|
}
|
|
// RV32-LABEL: define dso_local i32 @test_preinterpret_u16x2_u8x4(
|
|
// RV32-SAME: i32 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: ret i32 [[X_COERCE]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_preinterpret_u16x2_u8x4(
|
|
// RV64-SAME: i32 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: ret i32 [[X_COERCE]]
|
|
//
|
|
uint8x4_t test_preinterpret_u16x2_u8x4(uint16x2_t x) {
|
|
return __riscv_preinterpret_u16x2_u8x4(x);
|
|
}
|
|
// RV32-LABEL: define dso_local i32 @test_preinterpret_i16x2_u8x4(
|
|
// RV32-SAME: i32 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: ret i32 [[X_COERCE]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_preinterpret_i16x2_u8x4(
|
|
// RV64-SAME: i32 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: ret i32 [[X_COERCE]]
|
|
//
|
|
uint8x4_t test_preinterpret_i16x2_u8x4(int16x2_t x) {
|
|
return __riscv_preinterpret_i16x2_u8x4(x);
|
|
}
|
|
// RV32-LABEL: define dso_local i32 @test_preinterpret_u8x4_i8x4(
|
|
// RV32-SAME: i32 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: ret i32 [[X_COERCE]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_preinterpret_u8x4_i8x4(
|
|
// RV64-SAME: i32 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: ret i32 [[X_COERCE]]
|
|
//
|
|
int8x4_t test_preinterpret_u8x4_i8x4(uint8x4_t x) {
|
|
return __riscv_preinterpret_u8x4_i8x4(x);
|
|
}
|
|
// RV32-LABEL: define dso_local i32 @test_preinterpret_u16x2_i8x4(
|
|
// RV32-SAME: i32 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: ret i32 [[X_COERCE]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_preinterpret_u16x2_i8x4(
|
|
// RV64-SAME: i32 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: ret i32 [[X_COERCE]]
|
|
//
|
|
int8x4_t test_preinterpret_u16x2_i8x4(uint16x2_t x) {
|
|
return __riscv_preinterpret_u16x2_i8x4(x);
|
|
}
|
|
// RV32-LABEL: define dso_local i32 @test_preinterpret_i16x2_i8x4(
|
|
// RV32-SAME: i32 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: ret i32 [[X_COERCE]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_preinterpret_i16x2_i8x4(
|
|
// RV64-SAME: i32 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: ret i32 [[X_COERCE]]
|
|
//
|
|
int8x4_t test_preinterpret_i16x2_i8x4(int16x2_t x) {
|
|
return __riscv_preinterpret_i16x2_i8x4(x);
|
|
}
|
|
// RV32-LABEL: define dso_local i32 @test_preinterpret_u8x4_u16x2(
|
|
// RV32-SAME: i32 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: ret i32 [[X_COERCE]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_preinterpret_u8x4_u16x2(
|
|
// RV64-SAME: i32 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: ret i32 [[X_COERCE]]
|
|
//
|
|
uint16x2_t test_preinterpret_u8x4_u16x2(uint8x4_t x) {
|
|
return __riscv_preinterpret_u8x4_u16x2(x);
|
|
}
|
|
// RV32-LABEL: define dso_local i32 @test_preinterpret_i8x4_u16x2(
|
|
// RV32-SAME: i32 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: ret i32 [[X_COERCE]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_preinterpret_i8x4_u16x2(
|
|
// RV64-SAME: i32 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: ret i32 [[X_COERCE]]
|
|
//
|
|
uint16x2_t test_preinterpret_i8x4_u16x2(int8x4_t x) {
|
|
return __riscv_preinterpret_i8x4_u16x2(x);
|
|
}
|
|
// RV32-LABEL: define dso_local i32 @test_preinterpret_i16x2_u16x2(
|
|
// RV32-SAME: i32 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: ret i32 [[X_COERCE]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_preinterpret_i16x2_u16x2(
|
|
// RV64-SAME: i32 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: ret i32 [[X_COERCE]]
|
|
//
|
|
uint16x2_t test_preinterpret_i16x2_u16x2(int16x2_t x) {
|
|
return __riscv_preinterpret_i16x2_u16x2(x);
|
|
}
|
|
// RV32-LABEL: define dso_local i32 @test_preinterpret_u8x4_i16x2(
|
|
// RV32-SAME: i32 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: ret i32 [[X_COERCE]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_preinterpret_u8x4_i16x2(
|
|
// RV64-SAME: i32 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: ret i32 [[X_COERCE]]
|
|
//
|
|
int16x2_t test_preinterpret_u8x4_i16x2(uint8x4_t x) {
|
|
return __riscv_preinterpret_u8x4_i16x2(x);
|
|
}
|
|
// RV32-LABEL: define dso_local i32 @test_preinterpret_i8x4_i16x2(
|
|
// RV32-SAME: i32 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: ret i32 [[X_COERCE]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_preinterpret_i8x4_i16x2(
|
|
// RV64-SAME: i32 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: ret i32 [[X_COERCE]]
|
|
//
|
|
int16x2_t test_preinterpret_i8x4_i16x2(int8x4_t x) {
|
|
return __riscv_preinterpret_i8x4_i16x2(x);
|
|
}
|
|
// RV32-LABEL: define dso_local i32 @test_preinterpret_u16x2_i16x2(
|
|
// RV32-SAME: i32 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: ret i32 [[X_COERCE]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_preinterpret_u16x2_i16x2(
|
|
// RV64-SAME: i32 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: ret i32 [[X_COERCE]]
|
|
//
|
|
int16x2_t test_preinterpret_u16x2_i16x2(uint16x2_t x) {
|
|
return __riscv_preinterpret_u16x2_i16x2(x);
|
|
}
|
|
|
|
/* Reinterpret Casts, Packed <-> Packed (64-bit) */
|
|
// RV32-LABEL: define dso_local i64 @test_preinterpret_i8x8_u8x8(
|
|
// RV32-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: ret i64 [[X_COERCE]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_preinterpret_i8x8_u8x8(
|
|
// RV64-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: ret i64 [[X_COERCE]]
|
|
//
|
|
uint8x8_t test_preinterpret_i8x8_u8x8(int8x8_t x) {
|
|
return __riscv_preinterpret_i8x8_u8x8(x);
|
|
}
|
|
// RV32-LABEL: define dso_local i64 @test_preinterpret_u16x4_u8x8(
|
|
// RV32-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: ret i64 [[X_COERCE]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_preinterpret_u16x4_u8x8(
|
|
// RV64-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: ret i64 [[X_COERCE]]
|
|
//
|
|
uint8x8_t test_preinterpret_u16x4_u8x8(uint16x4_t x) {
|
|
return __riscv_preinterpret_u16x4_u8x8(x);
|
|
}
|
|
// RV32-LABEL: define dso_local i64 @test_preinterpret_i16x4_u8x8(
|
|
// RV32-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: ret i64 [[X_COERCE]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_preinterpret_i16x4_u8x8(
|
|
// RV64-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: ret i64 [[X_COERCE]]
|
|
//
|
|
uint8x8_t test_preinterpret_i16x4_u8x8(int16x4_t x) {
|
|
return __riscv_preinterpret_i16x4_u8x8(x);
|
|
}
|
|
// RV32-LABEL: define dso_local i64 @test_preinterpret_u32x2_u8x8(
|
|
// RV32-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: ret i64 [[X_COERCE]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_preinterpret_u32x2_u8x8(
|
|
// RV64-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: ret i64 [[X_COERCE]]
|
|
//
|
|
uint8x8_t test_preinterpret_u32x2_u8x8(uint32x2_t x) {
|
|
return __riscv_preinterpret_u32x2_u8x8(x);
|
|
}
|
|
// RV32-LABEL: define dso_local i64 @test_preinterpret_i32x2_u8x8(
|
|
// RV32-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: ret i64 [[X_COERCE]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_preinterpret_i32x2_u8x8(
|
|
// RV64-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: ret i64 [[X_COERCE]]
|
|
//
|
|
uint8x8_t test_preinterpret_i32x2_u8x8(int32x2_t x) {
|
|
return __riscv_preinterpret_i32x2_u8x8(x);
|
|
}
|
|
// RV32-LABEL: define dso_local i64 @test_preinterpret_u8x8_i8x8(
|
|
// RV32-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: ret i64 [[X_COERCE]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_preinterpret_u8x8_i8x8(
|
|
// RV64-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: ret i64 [[X_COERCE]]
|
|
//
|
|
int8x8_t test_preinterpret_u8x8_i8x8(uint8x8_t x) {
|
|
return __riscv_preinterpret_u8x8_i8x8(x);
|
|
}
|
|
// RV32-LABEL: define dso_local i64 @test_preinterpret_u16x4_i8x8(
|
|
// RV32-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: ret i64 [[X_COERCE]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_preinterpret_u16x4_i8x8(
|
|
// RV64-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: ret i64 [[X_COERCE]]
|
|
//
|
|
int8x8_t test_preinterpret_u16x4_i8x8(uint16x4_t x) {
|
|
return __riscv_preinterpret_u16x4_i8x8(x);
|
|
}
|
|
// RV32-LABEL: define dso_local i64 @test_preinterpret_i16x4_i8x8(
|
|
// RV32-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: ret i64 [[X_COERCE]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_preinterpret_i16x4_i8x8(
|
|
// RV64-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: ret i64 [[X_COERCE]]
|
|
//
|
|
int8x8_t test_preinterpret_i16x4_i8x8(int16x4_t x) {
|
|
return __riscv_preinterpret_i16x4_i8x8(x);
|
|
}
|
|
// RV32-LABEL: define dso_local i64 @test_preinterpret_u32x2_i8x8(
|
|
// RV32-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: ret i64 [[X_COERCE]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_preinterpret_u32x2_i8x8(
|
|
// RV64-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: ret i64 [[X_COERCE]]
|
|
//
|
|
int8x8_t test_preinterpret_u32x2_i8x8(uint32x2_t x) {
|
|
return __riscv_preinterpret_u32x2_i8x8(x);
|
|
}
|
|
// RV32-LABEL: define dso_local i64 @test_preinterpret_i32x2_i8x8(
|
|
// RV32-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: ret i64 [[X_COERCE]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_preinterpret_i32x2_i8x8(
|
|
// RV64-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: ret i64 [[X_COERCE]]
|
|
//
|
|
int8x8_t test_preinterpret_i32x2_i8x8(int32x2_t x) {
|
|
return __riscv_preinterpret_i32x2_i8x8(x);
|
|
}
|
|
// RV32-LABEL: define dso_local i64 @test_preinterpret_u8x8_u16x4(
|
|
// RV32-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: ret i64 [[X_COERCE]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_preinterpret_u8x8_u16x4(
|
|
// RV64-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: ret i64 [[X_COERCE]]
|
|
//
|
|
uint16x4_t test_preinterpret_u8x8_u16x4(uint8x8_t x) {
|
|
return __riscv_preinterpret_u8x8_u16x4(x);
|
|
}
|
|
// RV32-LABEL: define dso_local i64 @test_preinterpret_i8x8_u16x4(
|
|
// RV32-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: ret i64 [[X_COERCE]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_preinterpret_i8x8_u16x4(
|
|
// RV64-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: ret i64 [[X_COERCE]]
|
|
//
|
|
uint16x4_t test_preinterpret_i8x8_u16x4(int8x8_t x) {
|
|
return __riscv_preinterpret_i8x8_u16x4(x);
|
|
}
|
|
// RV32-LABEL: define dso_local i64 @test_preinterpret_i16x4_u16x4(
|
|
// RV32-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: ret i64 [[X_COERCE]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_preinterpret_i16x4_u16x4(
|
|
// RV64-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: ret i64 [[X_COERCE]]
|
|
//
|
|
uint16x4_t test_preinterpret_i16x4_u16x4(int16x4_t x) {
|
|
return __riscv_preinterpret_i16x4_u16x4(x);
|
|
}
|
|
// RV32-LABEL: define dso_local i64 @test_preinterpret_u32x2_u16x4(
|
|
// RV32-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: ret i64 [[X_COERCE]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_preinterpret_u32x2_u16x4(
|
|
// RV64-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: ret i64 [[X_COERCE]]
|
|
//
|
|
uint16x4_t test_preinterpret_u32x2_u16x4(uint32x2_t x) {
|
|
return __riscv_preinterpret_u32x2_u16x4(x);
|
|
}
|
|
// RV32-LABEL: define dso_local i64 @test_preinterpret_i32x2_u16x4(
|
|
// RV32-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: ret i64 [[X_COERCE]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_preinterpret_i32x2_u16x4(
|
|
// RV64-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: ret i64 [[X_COERCE]]
|
|
//
|
|
uint16x4_t test_preinterpret_i32x2_u16x4(int32x2_t x) {
|
|
return __riscv_preinterpret_i32x2_u16x4(x);
|
|
}
|
|
// RV32-LABEL: define dso_local i64 @test_preinterpret_u8x8_i16x4(
|
|
// RV32-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: ret i64 [[X_COERCE]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_preinterpret_u8x8_i16x4(
|
|
// RV64-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: ret i64 [[X_COERCE]]
|
|
//
|
|
int16x4_t test_preinterpret_u8x8_i16x4(uint8x8_t x) {
|
|
return __riscv_preinterpret_u8x8_i16x4(x);
|
|
}
|
|
// RV32-LABEL: define dso_local i64 @test_preinterpret_i8x8_i16x4(
|
|
// RV32-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: ret i64 [[X_COERCE]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_preinterpret_i8x8_i16x4(
|
|
// RV64-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: ret i64 [[X_COERCE]]
|
|
//
|
|
int16x4_t test_preinterpret_i8x8_i16x4(int8x8_t x) {
|
|
return __riscv_preinterpret_i8x8_i16x4(x);
|
|
}
|
|
// RV32-LABEL: define dso_local i64 @test_preinterpret_u16x4_i16x4(
|
|
// RV32-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: ret i64 [[X_COERCE]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_preinterpret_u16x4_i16x4(
|
|
// RV64-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: ret i64 [[X_COERCE]]
|
|
//
|
|
int16x4_t test_preinterpret_u16x4_i16x4(uint16x4_t x) {
|
|
return __riscv_preinterpret_u16x4_i16x4(x);
|
|
}
|
|
// RV32-LABEL: define dso_local i64 @test_preinterpret_u32x2_i16x4(
|
|
// RV32-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: ret i64 [[X_COERCE]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_preinterpret_u32x2_i16x4(
|
|
// RV64-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: ret i64 [[X_COERCE]]
|
|
//
|
|
int16x4_t test_preinterpret_u32x2_i16x4(uint32x2_t x) {
|
|
return __riscv_preinterpret_u32x2_i16x4(x);
|
|
}
|
|
// RV32-LABEL: define dso_local i64 @test_preinterpret_i32x2_i16x4(
|
|
// RV32-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: ret i64 [[X_COERCE]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_preinterpret_i32x2_i16x4(
|
|
// RV64-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: ret i64 [[X_COERCE]]
|
|
//
|
|
int16x4_t test_preinterpret_i32x2_i16x4(int32x2_t x) {
|
|
return __riscv_preinterpret_i32x2_i16x4(x);
|
|
}
|
|
// RV32-LABEL: define dso_local i64 @test_preinterpret_u8x8_u32x2(
|
|
// RV32-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: ret i64 [[X_COERCE]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_preinterpret_u8x8_u32x2(
|
|
// RV64-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: ret i64 [[X_COERCE]]
|
|
//
|
|
uint32x2_t test_preinterpret_u8x8_u32x2(uint8x8_t x) {
|
|
return __riscv_preinterpret_u8x8_u32x2(x);
|
|
}
|
|
// RV32-LABEL: define dso_local i64 @test_preinterpret_i8x8_u32x2(
|
|
// RV32-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: ret i64 [[X_COERCE]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_preinterpret_i8x8_u32x2(
|
|
// RV64-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: ret i64 [[X_COERCE]]
|
|
//
|
|
uint32x2_t test_preinterpret_i8x8_u32x2(int8x8_t x) {
|
|
return __riscv_preinterpret_i8x8_u32x2(x);
|
|
}
|
|
// RV32-LABEL: define dso_local i64 @test_preinterpret_u16x4_u32x2(
|
|
// RV32-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: ret i64 [[X_COERCE]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_preinterpret_u16x4_u32x2(
|
|
// RV64-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: ret i64 [[X_COERCE]]
|
|
//
|
|
uint32x2_t test_preinterpret_u16x4_u32x2(uint16x4_t x) {
|
|
return __riscv_preinterpret_u16x4_u32x2(x);
|
|
}
|
|
// RV32-LABEL: define dso_local i64 @test_preinterpret_i16x4_u32x2(
|
|
// RV32-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: ret i64 [[X_COERCE]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_preinterpret_i16x4_u32x2(
|
|
// RV64-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: ret i64 [[X_COERCE]]
|
|
//
|
|
uint32x2_t test_preinterpret_i16x4_u32x2(int16x4_t x) {
|
|
return __riscv_preinterpret_i16x4_u32x2(x);
|
|
}
|
|
// RV32-LABEL: define dso_local i64 @test_preinterpret_i32x2_u32x2(
|
|
// RV32-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: ret i64 [[X_COERCE]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_preinterpret_i32x2_u32x2(
|
|
// RV64-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: ret i64 [[X_COERCE]]
|
|
//
|
|
uint32x2_t test_preinterpret_i32x2_u32x2(int32x2_t x) {
|
|
return __riscv_preinterpret_i32x2_u32x2(x);
|
|
}
|
|
// RV32-LABEL: define dso_local i64 @test_preinterpret_u8x8_i32x2(
|
|
// RV32-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: ret i64 [[X_COERCE]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_preinterpret_u8x8_i32x2(
|
|
// RV64-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: ret i64 [[X_COERCE]]
|
|
//
|
|
int32x2_t test_preinterpret_u8x8_i32x2(uint8x8_t x) {
|
|
return __riscv_preinterpret_u8x8_i32x2(x);
|
|
}
|
|
// RV32-LABEL: define dso_local i64 @test_preinterpret_i8x8_i32x2(
|
|
// RV32-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: ret i64 [[X_COERCE]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_preinterpret_i8x8_i32x2(
|
|
// RV64-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: ret i64 [[X_COERCE]]
|
|
//
|
|
int32x2_t test_preinterpret_i8x8_i32x2(int8x8_t x) {
|
|
return __riscv_preinterpret_i8x8_i32x2(x);
|
|
}
|
|
// RV32-LABEL: define dso_local i64 @test_preinterpret_u16x4_i32x2(
|
|
// RV32-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: ret i64 [[X_COERCE]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_preinterpret_u16x4_i32x2(
|
|
// RV64-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: ret i64 [[X_COERCE]]
|
|
//
|
|
int32x2_t test_preinterpret_u16x4_i32x2(uint16x4_t x) {
|
|
return __riscv_preinterpret_u16x4_i32x2(x);
|
|
}
|
|
// RV32-LABEL: define dso_local i64 @test_preinterpret_i16x4_i32x2(
|
|
// RV32-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: ret i64 [[X_COERCE]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_preinterpret_i16x4_i32x2(
|
|
// RV64-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: ret i64 [[X_COERCE]]
|
|
//
|
|
int32x2_t test_preinterpret_i16x4_i32x2(int16x4_t x) {
|
|
return __riscv_preinterpret_i16x4_i32x2(x);
|
|
}
|
|
// RV32-LABEL: define dso_local i64 @test_preinterpret_u32x2_i32x2(
|
|
// RV32-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: ret i64 [[X_COERCE]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_preinterpret_u32x2_i32x2(
|
|
// RV64-SAME: i64 noundef [[X_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: ret i64 [[X_COERCE]]
|
|
//
|
|
int32x2_t test_preinterpret_u32x2_i32x2(uint32x2_t x) {
|
|
return __riscv_preinterpret_u32x2_i32x2(x);
|
|
}
|
|
|
|
/* Packed Narrowing Zip */
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_pnzip_i8x4(
|
|
// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
|
|
// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i8> [[TMP0]], <4 x i8> [[TMP1]], <4 x i32> <i32 0, i32 4, i32 2, i32 6>
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SHUFFLE_I]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_pnzip_i8x4(
|
|
// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
|
|
// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i8> [[TMP0]], <4 x i8> [[TMP1]], <4 x i32> <i32 0, i32 4, i32 2, i32 6>
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SHUFFLE_I]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
int8x4_t test_pnzip_i8x4(int16x2_t rs1, int16x2_t rs2) {
|
|
return __riscv_pnzip_i8x4(rs1, rs2);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_pnzip_u8x4(
|
|
// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
|
|
// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i8> [[TMP0]], <4 x i8> [[TMP1]], <4 x i32> <i32 0, i32 4, i32 2, i32 6>
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SHUFFLE_I]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_pnzip_u8x4(
|
|
// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
|
|
// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i8> [[TMP0]], <4 x i8> [[TMP1]], <4 x i32> <i32 0, i32 4, i32 2, i32 6>
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SHUFFLE_I]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
uint8x4_t test_pnzip_u8x4(uint16x2_t rs1, uint16x2_t rs2) {
|
|
return __riscv_pnzip_u8x4(rs1, rs2);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_pnziph_i8x4(
|
|
// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
|
|
// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i8> [[TMP0]], <4 x i8> [[TMP1]], <4 x i32> <i32 1, i32 5, i32 3, i32 7>
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SHUFFLE_I]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_pnziph_i8x4(
|
|
// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
|
|
// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i8> [[TMP0]], <4 x i8> [[TMP1]], <4 x i32> <i32 1, i32 5, i32 3, i32 7>
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SHUFFLE_I]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
int8x4_t test_pnziph_i8x4(int16x2_t rs1, int16x2_t rs2) {
|
|
return __riscv_pnziph_i8x4(rs1, rs2);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i32 @test_pnziph_u8x4(
|
|
// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
|
|
// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i8> [[TMP0]], <4 x i8> [[TMP1]], <4 x i32> <i32 1, i32 5, i32 3, i32 7>
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SHUFFLE_I]] to i32
|
|
// RV32-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i32 @test_pnziph_u8x4(
|
|
// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8>
|
|
// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i8> [[TMP0]], <4 x i8> [[TMP1]], <4 x i32> <i32 1, i32 5, i32 3, i32 7>
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SHUFFLE_I]] to i32
|
|
// RV64-NEXT: ret i32 [[TMP2]]
|
|
//
|
|
uint8x4_t test_pnziph_u8x4(uint16x2_t rs1, uint16x2_t rs2) {
|
|
return __riscv_pnziph_u8x4(rs1, rs2);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pnzip_i8x8(
|
|
// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
|
|
// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> [[TMP1]], <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14>
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SHUFFLE_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pnzip_i8x8(
|
|
// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
|
|
// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> [[TMP1]], <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14>
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SHUFFLE_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
int8x8_t test_pnzip_i8x8(int16x4_t rs1, int16x4_t rs2) {
|
|
return __riscv_pnzip_i8x8(rs1, rs2);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pnzip_u8x8(
|
|
// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
|
|
// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> [[TMP1]], <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14>
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SHUFFLE_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pnzip_u8x8(
|
|
// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
|
|
// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> [[TMP1]], <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14>
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SHUFFLE_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
uint8x8_t test_pnzip_u8x8(uint16x4_t rs1, uint16x4_t rs2) {
|
|
return __riscv_pnzip_u8x8(rs1, rs2);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pnzip_i16x4(
|
|
// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> [[TMP1]], <4 x i32> <i32 0, i32 4, i32 2, i32 6>
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pnzip_i16x4(
|
|
// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> [[TMP1]], <4 x i32> <i32 0, i32 4, i32 2, i32 6>
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
int16x4_t test_pnzip_i16x4(int32x2_t rs1, int32x2_t rs2) {
|
|
return __riscv_pnzip_i16x4(rs1, rs2);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pnzip_u16x4(
|
|
// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> [[TMP1]], <4 x i32> <i32 0, i32 4, i32 2, i32 6>
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pnzip_u16x4(
|
|
// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> [[TMP1]], <4 x i32> <i32 0, i32 4, i32 2, i32 6>
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
uint16x4_t test_pnzip_u16x4(uint32x2_t rs1, uint32x2_t rs2) {
|
|
return __riscv_pnzip_u16x4(rs1, rs2);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pnziph_i8x8(
|
|
// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
|
|
// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> [[TMP1]], <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15>
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SHUFFLE_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pnziph_i8x8(
|
|
// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
|
|
// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> [[TMP1]], <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15>
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SHUFFLE_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
int8x8_t test_pnziph_i8x8(int16x4_t rs1, int16x4_t rs2) {
|
|
return __riscv_pnziph_i8x8(rs1, rs2);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pnziph_u8x8(
|
|
// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
|
|
// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> [[TMP1]], <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15>
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SHUFFLE_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pnziph_u8x8(
|
|
// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8>
|
|
// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> [[TMP1]], <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15>
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SHUFFLE_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
uint8x8_t test_pnziph_u8x8(uint16x4_t rs1, uint16x4_t rs2) {
|
|
return __riscv_pnziph_u8x8(rs1, rs2);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pnziph_i16x4(
|
|
// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> [[TMP1]], <4 x i32> <i32 1, i32 5, i32 3, i32 7>
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pnziph_i16x4(
|
|
// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> [[TMP1]], <4 x i32> <i32 1, i32 5, i32 3, i32 7>
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
int16x4_t test_pnziph_i16x4(int32x2_t rs1, int32x2_t rs2) {
|
|
return __riscv_pnziph_i16x4(rs1, rs2);
|
|
}
|
|
|
|
// RV32-LABEL: define dso_local i64 @test_pnziph_u16x4(
|
|
// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV32-NEXT: [[ENTRY:.*:]]
|
|
// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
|
|
// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> [[TMP1]], <4 x i32> <i32 1, i32 5, i32 3, i32 7>
|
|
// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64
|
|
// RV32-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
// RV64-LABEL: define dso_local i64 @test_pnziph_u16x4(
|
|
// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
|
|
// RV64-NEXT: [[ENTRY:.*:]]
|
|
// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
|
|
// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> [[TMP1]], <4 x i32> <i32 1, i32 5, i32 3, i32 7>
|
|
// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64
|
|
// RV64-NEXT: ret i64 [[TMP2]]
|
|
//
|
|
uint16x4_t test_pnziph_u16x4(uint32x2_t rs1, uint32x2_t rs2) {
|
|
return __riscv_pnziph_u16x4(rs1, rs2);
|
|
}
|