add extra cycle analyses from MachineLICM not preserving CI

Created using spr 1.3.8-wip

llvm/include/llvm/Analysis/BlockFrequencyInfo.h

@@ -26,7 +26,7 @@ namespace llvm {
 
 class BasicBlock;
 class BranchProbabilityInfo;
-class LoopInfo;
+class CycleInfo;
 class Module;
 class raw_ostream;
 template <class BlockT> class BlockFrequencyInfoImpl;
@@ -44,7 +44,7 @@ public:
   LLVM_ABI BlockFrequencyInfo();
   LLVM_ABI BlockFrequencyInfo(const Function &F,
                               const BranchProbabilityInfo &BPI,
-                              const LoopInfo &LI);
+                              const CycleInfo &CI);
   BlockFrequencyInfo(const BlockFrequencyInfo &) = delete;
   BlockFrequencyInfo &operator=(const BlockFrequencyInfo &) = delete;
   LLVM_ABI BlockFrequencyInfo(BlockFrequencyInfo &&Arg);
@@ -94,7 +94,7 @@ public:
 
   /// calculate - compute block frequency info for the given function.
   LLVM_ABI void calculate(const Function &F, const BranchProbabilityInfo &BPI,
-                          const LoopInfo &LI);
+                          const CycleInfo &CI);
 
   LLVM_ABI BlockFrequency getEntryFreq() const;
   LLVM_ABI void releaseMemory();

llvm/include/llvm/Analysis/BlockFrequencyInfoImpl.h

@@ -17,6 +17,7 @@
 #include "llvm/ADT/BitVector.h"
 #include "llvm/ADT/DenseMap.h"
 #include "llvm/ADT/DenseSet.h"
+#include "llvm/ADT/GenericCycleInfo.h"
 #include "llvm/ADT/GraphTraits.h"
 #include "llvm/ADT/PostOrderIterator.h"
 #include "llvm/ADT/SmallPtrSet.h"
@@ -59,14 +60,12 @@ extern LLVM_ABI llvm::cl::opt<unsigned> IterativeBFIMaxIterationsPerBlock;
 extern LLVM_ABI llvm::cl::opt<double> IterativeBFIPrecision;
 
 class BranchProbabilityInfo;
+class CycleInfo;
 class Function;
-class Loop;
-class LoopInfo;
 class MachineBasicBlock;
 class MachineBranchProbabilityInfo;
+class MachineCycleInfo;
 class MachineFunction;
-class MachineLoop;
-class MachineLoopInfo;
 
 namespace bfi_detail {
 
@@ -235,6 +234,13 @@ public:
     LoopData(LoopData *Parent, const BlockNode &Header)
       : Parent(Parent), Nodes(1, Header), BackedgeMass(1) {}
 
+    template <class It>
+    LoopData(LoopData *Parent, It FirstHeader, It LastHeader)
+        : Parent(Parent), Nodes(FirstHeader, LastHeader) {
+      NumHeaders = Nodes.size();
+      BackedgeMass.resize(NumHeaders);
+    }
+
     template <class It1, class It2>
     LoopData(LoopData *Parent, It1 FirstHeader, It1 LastHeader, It2 FirstOther,
              It2 LastOther)
@@ -536,15 +542,13 @@ template <> struct TypeMap<BasicBlock> {
   using BlockT = BasicBlock;
   using FunctionT = Function;
   using BranchProbabilityInfoT = BranchProbabilityInfo;
-  using LoopT = Loop;
-  using LoopInfoT = LoopInfo;
+  using CycleInfoT = CycleInfo;
 };
 template <> struct TypeMap<MachineBasicBlock> {
   using BlockT = MachineBasicBlock;
   using FunctionT = MachineFunction;
   using BranchProbabilityInfoT = MachineBranchProbabilityInfo;
-  using LoopT = MachineLoop;
-  using LoopInfoT = MachineLoopInfo;
+  using CycleInfoT = MachineCycleInfo;
 };
 
 /// Get the name of a MachineBasicBlock.
@@ -832,13 +836,12 @@ template <class BT> class BlockFrequencyInfoImpl : BlockFrequencyInfoImplBase {
   using FunctionT = typename bfi_detail::TypeMap<BT>::FunctionT;
   using BranchProbabilityInfoT =
       typename bfi_detail::TypeMap<BT>::BranchProbabilityInfoT;
-  using LoopT = typename bfi_detail::TypeMap<BT>::LoopT;
-  using LoopInfoT = typename bfi_detail::TypeMap<BT>::LoopInfoT;
+  using CycleInfoT = typename bfi_detail::TypeMap<BT>::CycleInfoT;
   using Successor = GraphTraits<const BlockT *>;
   using Predecessor = GraphTraits<Inverse<const BlockT *>>;
 
   const BranchProbabilityInfoT *BPI = nullptr;
-  const LoopInfoT *LI = nullptr;
+  const CycleInfoT *CI = nullptr;
   const FunctionT *F = nullptr;
 
   // All blocks in reverse postorder.
@@ -984,7 +987,7 @@ public:
   const FunctionT *getFunction() const { return F; }
 
   void calculate(const FunctionT &F, const BranchProbabilityInfoT &BPI,
-                 const LoopInfoT &LI);
+                 const CycleInfoT &CI);
 
   using BlockFrequencyInfoImplBase::getEntryFreq;
 
@@ -1035,10 +1038,10 @@ public:
 template <class BT>
 void BlockFrequencyInfoImpl<BT>::calculate(const FunctionT &F,
                                            const BranchProbabilityInfoT &BPI,
-                                           const LoopInfoT &LI) {
+                                           const CycleInfoT &CI) {
   // Save the parameters.
   this->BPI = &BPI;
-  this->LI = &LI;
+  this->CI = &CI;
   this->F = &F;
 
   // Clean up left-over data structures.
@@ -1121,27 +1124,45 @@ template <class BT> void BlockFrequencyInfoImpl<BT>::initializeRPOT() {
 
 template <class BT> void BlockFrequencyInfoImpl<BT>::initializeLoops() {
   LLVM_DEBUG(dbgs() << "loop-detection\n");
-  if (LI->empty())
-    return;
+
+  LLVM_DEBUG(CI->print(dbgs()));
+
+  // Whether \p C describes a loop for BFI. An entry of a cycle an edge
+  // re-enters heads a loop the forest does not represent, because the cycle
+  // absorbed it; which entry that is depends on the order the search found
+  // them in. Represent none of them, so that equal entries stay equal, and
+  // leave the region to the packaging computeIrreducibleMass does.
+  auto hasLoop = [&](CycleRef C) {
+    if (!CI->isReducible(C))
+      return false;
+    for (CycleRef A = CI->getParentCycle(C); A; A = CI->getParentCycle(A))
+      if (!CI->isReducible(A) && CI->isEntry(A, CI->getHeader(C)))
+        return false;
+    return true;
+  };
 
   // Visit loops top down and assign them an index.
-  std::deque<std::pair<const LoopT *, LoopData *>> Q;
-  for (const LoopT *L : *LI)
-    Q.emplace_back(L, nullptr);
+  std::deque<std::pair<CycleRef, LoopData *>> Q;
+  for (CycleRef C : CI->toplevel_cycles())
+    Q.emplace_back(C, nullptr);
+  if (Q.empty())
+    return; // Early exit if there are no cycles.
   while (!Q.empty()) {
-    const LoopT *Loop = Q.front().first;
+    CycleRef Cycle = Q.front().first;
     LoopData *Parent = Q.front().second;
     Q.pop_front();
 
-    BlockNode Header = getNode(Loop->getHeader());
-    assert(Header.isValid());
+    if (hasLoop(Cycle)) {
+      BlockNode Header = getNode(CI->getHeader(Cycle));
+      Loops.emplace_back(Parent, Header);
 
-    Loops.emplace_back(Parent, Header);
-    Working[Header.Index].Loop = &Loops.back();
-    LLVM_DEBUG(dbgs() << " - loop = " << getBlockName(Header) << "\n");
+      Working[Header.Index].Loop = &Loops.back();
+      LLVM_DEBUG(dbgs() << " - loop = " << getBlockName(Header) << "\n");
+      Parent = &Loops.back();
+    }
 
-    for (const LoopT *L : *Loop)
-      Q.emplace_back(L, &Loops.back());
+    for (CycleRef C : CI->children(Cycle))
+      Q.emplace_back(C, Parent);
   }
 
   // Visit nodes in reverse post-order and add them to their deepest containing
@@ -1155,12 +1176,14 @@ template <class BT> void BlockFrequencyInfoImpl<BT>::initializeLoops() {
       continue;
     }
 
-    const LoopT *Loop = LI->getLoopFor(RPOT[Index]);
-    if (!Loop)
+    CycleRef Cycle = CI->getCycle(RPOT[Index]);
+    while (Cycle && !hasLoop(Cycle))
+      Cycle = CI->getParentCycle(Cycle);
+    if (!Cycle)
       continue;
 
     // Add this node to its containing loop's member list.
-    BlockNode Header = getNode(Loop->getHeader());
+    BlockNode Header = getNode(CI->getHeader(Cycle));
     assert(Header.isValid());
     const auto &HeaderData = Working[Header.Index];
     assert(HeaderData.isLoopHeader());

llvm/include/llvm/Analysis/LazyBlockFrequencyInfo.h

@@ -22,32 +22,32 @@
 
 namespace llvm {
 class Function;
-class LoopInfo;
+class CycleInfo;
 
 /// Wraps a BFI to allow lazy computation of the block frequencies.
 ///
 /// A pass that only conditionally uses BFI can uncondtionally require the
 /// analysis without paying for the overhead if BFI doesn't end up being used.
 template <typename FunctionT, typename BranchProbabilityInfoPassT,
-          typename LoopInfoT, typename BlockFrequencyInfoT>
+          typename CycleInfoT, typename BlockFrequencyInfoT>
 class LazyBlockFrequencyInfo {
 public:
   LazyBlockFrequencyInfo() = default;
 
   /// Set up the per-function input.
   void setAnalysis(const FunctionT *F, BranchProbabilityInfoPassT *BPIPass,
-                   const LoopInfoT *LI) {
+                   const CycleInfoT *CI) {
     this->F = F;
     this->BPIPass = BPIPass;
-    this->LI = LI;
+    this->CI = CI;
   }
 
   /// Retrieve the BFI with the block frequencies computed.
   BlockFrequencyInfoT &getCalculated() {
     if (!Calculated) {
-      assert(F && BPIPass && LI && "call setAnalysis");
+      assert(F && BPIPass && CI && "call setAnalysis");
       BFI.calculate(
-          *F, BPIPassTrait<BranchProbabilityInfoPassT>::getBPI(BPIPass), *LI);
+          *F, BPIPassTrait<BranchProbabilityInfoPassT>::getBPI(BPIPass), *CI);
       Calculated = true;
     }
     return BFI;
@@ -68,7 +68,7 @@ private:
   bool Calculated = false;
   const FunctionT *F = nullptr;
   BranchProbabilityInfoPassT *BPIPass = nullptr;
-  const LoopInfoT *LI = nullptr;
+  const CycleInfoT *CI = nullptr;
 };
 
 /// This is an alternative analysis pass to
@@ -88,15 +88,15 @@ private:
 ///   LazyBlockFrequencyInfoPass::getLazyBFIAnalysisUsage(AU)
 ///
 /// 3. The computed BFI should be requested with
-///    getAnalysis<LazyBlockFrequencyInfoPass>().getBFI() before either LoopInfo
-///    or BPI could be invalidated for example by changing the CFG.
+///    getAnalysis<LazyBlockFrequencyInfoPass>().getBFI() before either
+///    CycleInfo or BPI could be invalidated for example by changing the CFG.
 ///
 /// Note that it is expected that we wouldn't need this functionality for the
 /// new PM since with the new PM, analyses are executed on demand.
 
 class LLVM_ABI LazyBlockFrequencyInfoPass : public FunctionPass {
 private:
-  LazyBlockFrequencyInfo<Function, LazyBranchProbabilityInfoPass, LoopInfo,
+  LazyBlockFrequencyInfo<Function, LazyBranchProbabilityInfoPass, CycleInfo,
                          BlockFrequencyInfo>
       LBFI;
 

llvm/include/llvm/CodeGen/LazyMachineBlockFrequencyInfo.h

@@ -17,11 +17,12 @@
 #define LLVM_CODEGEN_LAZYMACHINEBLOCKFREQUENCYINFO_H
 
 #include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
-#include "llvm/CodeGen/MachineDominators.h"
 #include "llvm/CodeGen/MachineFunctionPass.h"
-#include "llvm/CodeGen/MachineLoopInfo.h"
 
 namespace llvm {
+
+class MachineCycleInfo;
+
 /// This is an alternative analysis pass to MachineBlockFrequencyInfo.
 /// The difference is that with this pass, the block frequencies are not
 /// computed when the analysis pass is executed but rather when the BFI result
@@ -40,10 +41,7 @@ private:
   mutable std::unique_ptr<MachineBlockFrequencyInfo> OwnedMBFI;
 
   /// If generated on the fly this own the instance.
-  mutable std::unique_ptr<MachineLoopInfo> OwnedMLI;
-
-  /// If generated on the fly this own the instance.
-  mutable std::unique_ptr<MachineDominatorTree> OwnedMDT;
+  mutable std::unique_ptr<MachineCycleInfo> OwnedMCI;
 
   /// The function.
   MachineFunction *MF = nullptr;

llvm/include/llvm/CodeGen/MachineBlockFrequencyInfo.h

@@ -27,7 +27,7 @@ template <class BlockT> class BlockFrequencyInfoImpl;
 class MachineBasicBlock;
 class MachineBranchProbabilityInfo;
 class MachineFunction;
-class MachineLoopInfo;
+class MachineCycleInfo;
 class raw_ostream;
 
 /// MachineBlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation
@@ -40,7 +40,7 @@ public:
   LLVM_ABI MachineBlockFrequencyInfo(); // Legacy pass manager only.
   LLVM_ABI explicit MachineBlockFrequencyInfo(
       const MachineFunction &F, const MachineBranchProbabilityInfo &MBPI,
-      const MachineLoopInfo &MLI);
+      const MachineCycleInfo &MCI);
   LLVM_ABI MachineBlockFrequencyInfo(MachineBlockFrequencyInfo &&);
   LLVM_ABI ~MachineBlockFrequencyInfo();
 
@@ -51,7 +51,7 @@ public:
   /// calculate - compute block frequency info for the given function.
   LLVM_ABI void calculate(const MachineFunction &F,
                           const MachineBranchProbabilityInfo &MBPI,
-                          const MachineLoopInfo &MLI);
+                          const MachineCycleInfo &MCI);
 
   LLVM_ABI void print(raw_ostream &OS);
 

llvm/lib/Analysis/BlockFrequencyInfo.cpp

@@ -15,7 +15,7 @@
 #include "llvm/ADT/iterator.h"
 #include "llvm/Analysis/BlockFrequencyInfoImpl.h"
 #include "llvm/Analysis/BranchProbabilityInfo.h"
-#include "llvm/Analysis/LoopInfo.h"
+#include "llvm/Analysis/CycleAnalysis.h"
 #include "llvm/IR/CFG.h"
 #include "llvm/IR/Function.h"
 #include "llvm/IR/PassManager.h"
@@ -153,8 +153,8 @@ BlockFrequencyInfo::BlockFrequencyInfo() = default;
 
 BlockFrequencyInfo::BlockFrequencyInfo(const Function &F,
                                        const BranchProbabilityInfo &BPI,
-                                       const LoopInfo &LI) {
-  calculate(F, BPI, LI);
+                                       const CycleInfo &CI) {
+  calculate(F, BPI, CI);
 }
 
 BlockFrequencyInfo::BlockFrequencyInfo(BlockFrequencyInfo &&Arg)
@@ -183,10 +183,10 @@ bool BlockFrequencyInfo::invalidate(Function &F, const PreservedAnalyses &PA,
 
 void BlockFrequencyInfo::calculate(const Function &F,
                                    const BranchProbabilityInfo &BPI,
-                                   const LoopInfo &LI) {
+                                   const CycleInfo &CI) {
   if (!BFI)
     BFI.reset(new ImplType);
-  BFI->calculate(F, BPI, LI);
+  BFI->calculate(F, BPI, CI);
   if (ViewBlockFreqPropagationDAG != GVDT_None &&
       (ViewBlockFreqFuncName.empty() || F.getName() == ViewBlockFreqFuncName)) {
     view();
@@ -295,7 +295,7 @@ Printable llvm::printBlockFreq(const BlockFrequencyInfo &BFI,
 INITIALIZE_PASS_BEGIN(BlockFrequencyInfoWrapperPass, "block-freq",
                       "Block Frequency Analysis", true, true)
 INITIALIZE_PASS_DEPENDENCY(BranchProbabilityInfoWrapperPass)
-INITIALIZE_PASS_DEPENDENCY(LoopInfoWrapperPass)
+INITIALIZE_PASS_DEPENDENCY(CycleInfoWrapperPass)
 INITIALIZE_PASS_END(BlockFrequencyInfoWrapperPass, "block-freq",
                     "Block Frequency Analysis", true, true)
 
@@ -313,7 +313,7 @@ void BlockFrequencyInfoWrapperPass::print(raw_ostream &OS,
 
 void BlockFrequencyInfoWrapperPass::getAnalysisUsage(AnalysisUsage &AU) const {
   AU.addRequired<BranchProbabilityInfoWrapperPass>();
-  AU.addRequired<LoopInfoWrapperPass>();
+  AU.addRequired<CycleInfoWrapperPass>();
   AU.setPreservesAll();
 }
 
@@ -322,7 +322,7 @@ void BlockFrequencyInfoWrapperPass::releaseMemory() { BFI.releaseMemory(); }
 bool BlockFrequencyInfoWrapperPass::runOnFunction(Function &F) {
   BranchProbabilityInfo &BPI =
       getAnalysis<BranchProbabilityInfoWrapperPass>().getBPI();
-  LoopInfo &LI = getAnalysis<LoopInfoWrapperPass>().getLoopInfo();
+  CycleInfo &LI = getAnalysis<CycleInfoWrapperPass>().getResult();
   BFI.calculate(F, BPI, LI);
   return false;
 }
@@ -331,7 +331,7 @@ AnalysisKey BlockFrequencyAnalysis::Key;
 BlockFrequencyInfo BlockFrequencyAnalysis::run(Function &F,
                                                FunctionAnalysisManager &AM) {
   auto &BP = AM.getResult<BranchProbabilityAnalysis>(F);
-  auto &LI = AM.getResult<LoopAnalysis>(F);
+  auto &LI = AM.getResult<CycleAnalysis>(F);
   BlockFrequencyInfo BFI;
   BFI.calculate(F, BP, LI);
   return BFI;

llvm/lib/Analysis/BlockFrequencyInfoImpl.cpp

@@ -329,6 +329,7 @@ bool BlockFrequencyInfoImplBase::addToDist(Distribution &Dist,
            << " [" << Type << "] weight = " << Weight;
     if (!isLoopHeader(Resolved))
       dbgs() << ", succ = " << getBlockName(Succ);
+    dbgs() << ", pred = " << getBlockName(Pred);
     if (Resolved != Succ)
       dbgs() << ", resolved = " << getBlockName(Resolved);
     dbgs() << "\n";
@@ -350,12 +351,12 @@ bool BlockFrequencyInfoImplBase::addToDist(Distribution &Dist,
 
   if (Resolved < Pred) {
     if (!isLoopHeader(Pred)) {
-      // If OuterLoop is an irreducible loop, we can't actually handle this.
-      assert((!OuterLoop || !OuterLoop->isIrreducible()) &&
-             "unhandled irreducible control flow");
 
       // Irreducible backedge.  Abort.
       LLVM_DEBUG(debugSuccessor("abort!!!"));
+      // If OuterLoop is an irreducible loop, we can't actually handle this.
+      assert((!OuterLoop || !OuterLoop->isIrreducible()) &&
+             "unhandled irreducible control flow");
       return false;
     }
 

llvm/lib/Analysis/LazyBlockFrequencyInfo.cpp

@@ -14,8 +14,8 @@
 //===----------------------------------------------------------------------===//
 
 #include "llvm/Analysis/LazyBlockFrequencyInfo.h"
+#include "llvm/Analysis/CycleAnalysis.h"
 #include "llvm/Analysis/LazyBranchProbabilityInfo.h"
-#include "llvm/Analysis/LoopInfo.h"
 #include "llvm/IR/Dominators.h"
 #include "llvm/InitializePasses.h"
 
@@ -26,7 +26,7 @@ using namespace llvm;
 INITIALIZE_PASS_BEGIN(LazyBlockFrequencyInfoPass, DEBUG_TYPE,
                       "Lazy Block Frequency Analysis", true, true)
 INITIALIZE_PASS_DEPENDENCY(LazyBPIPass)
-INITIALIZE_PASS_DEPENDENCY(LoopInfoWrapperPass)
+INITIALIZE_PASS_DEPENDENCY(CycleInfoWrapperPass)
 INITIALIZE_PASS_END(LazyBlockFrequencyInfoPass, DEBUG_TYPE,
                     "Lazy Block Frequency Analysis", true, true)
 
@@ -44,7 +44,7 @@ void LazyBlockFrequencyInfoPass::getAnalysisUsage(AnalysisUsage &AU) const {
   // asserts that DT is also present so if we don't make sure that we have DT
   // here, that assert will trigger.
   AU.addRequiredTransitive<DominatorTreeWrapperPass>();
-  AU.addRequiredTransitive<LoopInfoWrapperPass>();
+  AU.addRequiredTransitive<CycleInfoWrapperPass>();
   AU.setPreservesAll();
 }
 
@@ -52,7 +52,7 @@ void LazyBlockFrequencyInfoPass::releaseMemory() { LBFI.releaseMemory(); }
 
 bool LazyBlockFrequencyInfoPass::runOnFunction(Function &F) {
   auto &BPIPass = getAnalysis<LazyBranchProbabilityInfoPass>();
-  LoopInfo &LI = getAnalysis<LoopInfoWrapperPass>().getLoopInfo();
+  CycleInfo &LI = getAnalysis<CycleInfoWrapperPass>().getResult();
   LBFI.setAnalysis(&F, &BPIPass, &LI);
   return false;
 }
@@ -60,11 +60,11 @@ bool LazyBlockFrequencyInfoPass::runOnFunction(Function &F) {
 void LazyBlockFrequencyInfoPass::getLazyBFIAnalysisUsage(AnalysisUsage &AU) {
   LazyBranchProbabilityInfoPass::getLazyBPIAnalysisUsage(AU);
   AU.addRequiredTransitive<LazyBlockFrequencyInfoPass>();
-  AU.addRequiredTransitive<LoopInfoWrapperPass>();
+  AU.addRequiredTransitive<CycleInfoWrapperPass>();
 }
 
 void llvm::initializeLazyBFIPassPass(PassRegistry &Registry) {
   initializeLazyBPIPassPass(Registry);
   INITIALIZE_PASS_DEPENDENCY(LazyBlockFrequencyInfoPass);
-  INITIALIZE_PASS_DEPENDENCY(LoopInfoWrapperPass);
+  INITIALIZE_PASS_DEPENDENCY(CycleInfoWrapperPass);
 }

llvm/lib/Analysis/ModuleSummaryAnalysis.cpp

@@ -1084,11 +1084,10 @@ ModuleSummaryIndex llvm::buildModuleSummaryIndex(
     if (GetBFICallback)
       BFI = GetBFICallback(F);
     else if (F.hasProfileData()) {
-      LoopInfo LI{DT};
       CycleInfo CI;
       CI.compute(const_cast<Function &>(F));
       BranchProbabilityInfo BPI{F, CI};
-      BFIPtr = std::make_unique<BlockFrequencyInfo>(F, BPI, LI);
+      BFIPtr = std::make_unique<BlockFrequencyInfo>(F, BPI, CI);
       BFI = BFIPtr.get();
     }
 

llvm/lib/Analysis/OptimizationRemarkEmitter.cpp

@@ -34,17 +34,15 @@ OptimizationRemarkEmitter::OptimizationRemarkEmitter(const Function *F)
   DominatorTree DT;
   DT.recalculate(*const_cast<Function *>(F));
 
-  // Generate LoopInfo from it.
+  // Generate CycleInfo.
   CycleInfo CI;
   CI.compute(*const_cast<Function *>(F));
-  LoopInfo LI;
-  LI.analyze(DT);
 
   // Then compute BranchProbabilityInfo.
   BranchProbabilityInfo BPI(*F, CI, nullptr, &DT, nullptr);
 
   // Finally compute BFI.
-  OwnedBFI = std::make_unique<BlockFrequencyInfo>(*F, BPI, LI);
+  OwnedBFI = std::make_unique<BlockFrequencyInfo>(*F, BPI, CI);
   BFI = OwnedBFI.get();
 }
 

llvm/lib/CodeGen/CodeGenPrepare.cpp

@@ -856,9 +856,8 @@ void CodeGenPrepare::removeAllAssertingVHReferences(Value *V) {
   DominatorTree NewDT(F);
   CycleInfo NewCI;
   NewCI.compute(F);
-  LoopInfo NewLI(NewDT);
   BranchProbabilityInfo NewBPI(F, NewCI, TLInfo);
-  BlockFrequencyInfo NewBFI(F, NewBPI, NewLI);
+  BlockFrequencyInfo NewBFI(F, NewBPI, NewCI);
   NewBFI.verifyMatch(*BFI);
 }
 

llvm/lib/CodeGen/LazyMachineBlockFrequencyInfo.cpp

@@ -15,6 +15,7 @@
 
 #include "llvm/CodeGen/LazyMachineBlockFrequencyInfo.h"
 #include "llvm/CodeGen/MachineBranchProbabilityInfo.h"
+#include "llvm/CodeGen/MachineCycleAnalysis.h"
 #include "llvm/InitializePasses.h"
 
 using namespace llvm;
@@ -24,7 +25,7 @@ using namespace llvm;
 INITIALIZE_PASS_BEGIN(LazyMachineBlockFrequencyInfoPass, DEBUG_TYPE,
                       "Lazy Machine Block Frequency Analysis", true, true)
 INITIALIZE_PASS_DEPENDENCY(MachineBranchProbabilityInfoWrapperPass)
-INITIALIZE_PASS_DEPENDENCY(MachineLoopInfoWrapperPass)
+INITIALIZE_PASS_DEPENDENCY(MachineCycleInfoWrapperPass)
 INITIALIZE_PASS_END(LazyMachineBlockFrequencyInfoPass, DEBUG_TYPE,
                     "Lazy Machine Block Frequency Analysis", true, true)
 
@@ -42,8 +43,7 @@ void LazyMachineBlockFrequencyInfoPass::getAnalysisUsage(
 
 void LazyMachineBlockFrequencyInfoPass::releaseMemory() {
   OwnedMBFI.reset();
-  OwnedMLI.reset();
-  OwnedMDT.reset();
+  OwnedMCI.reset();
 }
 
 MachineBlockFrequencyInfo &
@@ -56,33 +56,20 @@ LazyMachineBlockFrequencyInfoPass::calculateIfNotAvailable() const {
   }
 
   auto &MBPI = getAnalysis<MachineBranchProbabilityInfoWrapperPass>().getMBPI();
-  auto *MLIWrapper = getAnalysisIfAvailable<MachineLoopInfoWrapperPass>();
-  auto *MLI = MLIWrapper ? &MLIWrapper->getLI() : nullptr;
-  auto *MDTWrapper = getAnalysisIfAvailable<MachineDominatorTreeWrapperPass>();
-  auto *MDT = MDTWrapper ? &MDTWrapper->getDomTree() : nullptr;
+  auto *MCIWrapper = getAnalysisIfAvailable<MachineCycleInfoWrapperPass>();
+  auto *MCI = MCIWrapper ? &MCIWrapper->getCycleInfo() : nullptr;
   LLVM_DEBUG(dbgs() << "Building MachineBlockFrequencyInfo on the fly\n");
-  LLVM_DEBUG(if (MLI) dbgs() << "LoopInfo is available\n");
+  LLVM_DEBUG(if (MCI) dbgs() << "CycleInfo is available\n");
 
-  if (!MLI) {
-    LLVM_DEBUG(dbgs() << "Building LoopInfo on the fly\n");
-    LLVM_DEBUG(if (MDT) dbgs() << "DominatorTree is available\n");
-
-    // A dominator tree is needed only for an irreducible CFG.
-    OwnedMLI = std::make_unique<MachineLoopInfo>();
-    OwnedMLI->calculate(*MF, [&]() -> const MachineDominatorTree & {
-      if (!MDT) {
-        LLVM_DEBUG(dbgs() << "Building DominatorTree on the fly\n");
-        OwnedMDT = std::make_unique<MachineDominatorTree>();
-        OwnedMDT->recalculate(*MF);
-        MDT = OwnedMDT.get();
-      }
-      return *MDT;
-    });
-    MLI = OwnedMLI.get();
+  if (!MCI) {
+    LLVM_DEBUG(dbgs() << "Building CycleInfo on the fly\n");
+    OwnedMCI = std::make_unique<MachineCycleInfo>();
+    OwnedMCI->compute(*MF);
+    MCI = OwnedMCI.get();
   }
 
   OwnedMBFI = std::make_unique<MachineBlockFrequencyInfo>();
-  OwnedMBFI->calculate(*MF, MBPI, *MLI);
+  OwnedMBFI->calculate(*MF, MBPI, *MCI);
   return *OwnedMBFI;
 }
 

llvm/lib/CodeGen/MIRSampleProfile.cpp

@@ -18,6 +18,7 @@
 #include "llvm/CodeGen/MIRFSDiscriminatorOptions.h"
 #include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
 #include "llvm/CodeGen/MachineBranchProbabilityInfo.h"
+#include "llvm/CodeGen/MachineCycleAnalysis.h"
 #include "llvm/CodeGen/MachineDominators.h"
 #include "llvm/CodeGen/MachineInstr.h"
 #include "llvm/CodeGen/MachineLoopInfo.h"
@@ -381,9 +382,11 @@ bool MIRProfileLoaderPass::runOnMachineFunction(MachineFunction &MF) {
   }
 
   bool Changed = MIRSampleLoader->runOnFunction(MF);
-  if (Changed)
-    MBFI->calculate(MF, *MBFI->getMBPI(),
-                    *&getAnalysis<MachineLoopInfoWrapperPass>().getLI());
+  if (Changed) {
+    MachineCycleInfo MCI;
+    MCI.compute(MF);
+    MBFI->calculate(MF, *MBFI->getMBPI(), MCI);
+  }
 
   if (ViewBFIAfter && ViewBlockLayoutWithBFI != GVDT_None &&
       (ViewBlockFreqFuncName.empty() ||

llvm/lib/CodeGen/MachineBlockFrequencyInfo.cpp

@@ -16,8 +16,8 @@
 #include "llvm/Analysis/BlockFrequencyInfoImpl.h"
 #include "llvm/CodeGen/MachineBasicBlock.h"
 #include "llvm/CodeGen/MachineBranchProbabilityInfo.h"
+#include "llvm/CodeGen/MachineCycleAnalysis.h"
 #include "llvm/CodeGen/MachineFunction.h"
-#include "llvm/CodeGen/MachineLoopInfo.h"
 #include "llvm/InitializePasses.h"
 #include "llvm/Pass.h"
 #include "llvm/Support/CommandLine.h"
@@ -163,8 +163,8 @@ MachineBlockFrequencyAnalysis::Result
 MachineBlockFrequencyAnalysis::run(MachineFunction &MF,
                                    MachineFunctionAnalysisManager &MFAM) {
   auto &MBPI = MFAM.getResult<MachineBranchProbabilityAnalysis>(MF);
-  auto &MLI = MFAM.getResult<MachineLoopAnalysis>(MF);
-  return Result(MF, MBPI, MLI);
+  auto &MCI = MFAM.getResult<MachineCycleAnalysis>(MF);
+  return Result(MF, MBPI, MCI);
 }
 
 PreservedAnalyses
@@ -180,7 +180,7 @@ MachineBlockFrequencyPrinterPass::run(MachineFunction &MF,
 INITIALIZE_PASS_BEGIN(MachineBlockFrequencyInfoWrapperPass, DEBUG_TYPE,
                       "Machine Block Frequency Analysis", true, true)
 INITIALIZE_PASS_DEPENDENCY(MachineBranchProbabilityInfoWrapperPass)
-INITIALIZE_PASS_DEPENDENCY(MachineLoopInfoWrapperPass)
+INITIALIZE_PASS_DEPENDENCY(MachineCycleInfoWrapperPass)
 INITIALIZE_PASS_END(MachineBlockFrequencyInfoWrapperPass, DEBUG_TYPE,
                     "Machine Block Frequency Analysis", true, true)
 
@@ -196,8 +196,8 @@ MachineBlockFrequencyInfo::MachineBlockFrequencyInfo(
 
 MachineBlockFrequencyInfo::MachineBlockFrequencyInfo(
     const MachineFunction &F, const MachineBranchProbabilityInfo &MBPI,
-    const MachineLoopInfo &MLI) {
-  calculate(F, MBPI, MLI);
+    const MachineCycleInfo &MCI) {
+  calculate(F, MBPI, MCI);
 }
 
 MachineBlockFrequencyInfo::~MachineBlockFrequencyInfo() = default;
@@ -216,17 +216,17 @@ bool MachineBlockFrequencyInfo::invalidate(
 void MachineBlockFrequencyInfoWrapperPass::getAnalysisUsage(
     AnalysisUsage &AU) const {
   AU.addRequired<MachineBranchProbabilityInfoWrapperPass>();
-  AU.addRequired<MachineLoopInfoWrapperPass>();
+  AU.addRequired<MachineCycleInfoWrapperPass>();
   AU.setPreservesAll();
   MachineFunctionPass::getAnalysisUsage(AU);
 }
 
 void MachineBlockFrequencyInfo::calculate(
     const MachineFunction &F, const MachineBranchProbabilityInfo &MBPI,
-    const MachineLoopInfo &MLI) {
+    const MachineCycleInfo &MCI) {
   if (!MBFI)
     MBFI.reset(new ImplType);
-  MBFI->calculate(F, MBPI, MLI);
+  MBFI->calculate(F, MBPI, MCI);
   if (ViewMachineBlockFreqPropagationDAG != GVDT_None &&
       (ViewBlockFreqFuncName.empty() || F.getName() == ViewBlockFreqFuncName)) {
     view("MachineBlockFrequencyDAGS." + F.getName());
@@ -241,8 +241,9 @@ bool MachineBlockFrequencyInfoWrapperPass::runOnMachineFunction(
     MachineFunction &F) {
   MachineBranchProbabilityInfo &MBPI =
       getAnalysis<MachineBranchProbabilityInfoWrapperPass>().getMBPI();
-  MachineLoopInfo &MLI = getAnalysis<MachineLoopInfoWrapperPass>().getLI();
-  MBFI.calculate(F, MBPI, MLI);
+  MachineCycleInfo &MCI =
+      getAnalysis<MachineCycleInfoWrapperPass>().getCycleInfo();
+  MBFI.calculate(F, MBPI, MCI);
   return false;
 }
 

llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp

@@ -35,6 +35,7 @@
 #include "llvm/CodeGen/MachineBasicBlock.h"
 #include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
 #include "llvm/CodeGen/MachineBranchProbabilityInfo.h"
+#include "llvm/CodeGen/MachineCycleAnalysis.h"
 #include "llvm/CodeGen/MachineOperand.h"
 #include "llvm/CodeGen/RegisterClassInfo.h"
 #include "llvm/CodeGen/Rematerializer.h"
@@ -3005,9 +3006,10 @@ bool PreRARematStage::ScoredRemat::maybeBeneficial(
 
 PreRARematStage::ScoredRemat::FreqInfo::FreqInfo(
     MachineFunction &MF, const GCNScheduleDAGMILive &DAG) {
-  assert(DAG.MLI && "MLI not defined in DAG");
   MachineBranchProbabilityInfo MBPI;
-  MachineBlockFrequencyInfo MBFI(MF, MBPI, *DAG.MLI);
+  MachineCycleInfo MCI;
+  MCI.compute(MF);
+  MachineBlockFrequencyInfo MBFI(MF, MBPI, MCI);
 
   const unsigned NumRegions = DAG.Regions.size();
   MinFreq = MBFI.getEntryFreq().getFrequency();

llvm/lib/Transforms/IPO/PartialInlining.cpp

@@ -356,7 +356,7 @@ PartialInlinerImpl::computeOutliningColdRegionsInfo(
   std::unique_ptr<BlockFrequencyInfo> ScopedBFI;
   BlockFrequencyInfo *BFI;
   if (!GetBFI) {
-    ScopedBFI.reset(new BlockFrequencyInfo(F, BPI, LI));
+    ScopedBFI.reset(new BlockFrequencyInfo(F, BPI, CI));
     BFI = ScopedBFI.get();
   } else
     BFI = &(GetBFI(F));
@@ -907,10 +907,8 @@ void PartialInlinerImpl::computeCallsiteToProfCountMap(
       if (!GetBFI) {
         CycleInfo CI;
         CI.compute(*Caller);
-        LoopInfo LI;
-        LI.analyze(Caller);
         BranchProbabilityInfo BPI(*Caller, CI);
-        TempBFI.reset(new BlockFrequencyInfo(*Caller, BPI, LI));
+        TempBFI.reset(new BlockFrequencyInfo(*Caller, BPI, CI));
         CurrentCallerBFI = TempBFI.get();
       } else {
         // New pass manager:
@@ -1095,9 +1093,8 @@ bool PartialInlinerImpl::FunctionCloner::doMultiRegionFunctionOutlining() {
   // Manually calculate a BlockFrequencyInfo and BranchProbabilityInfo.
   CycleInfo CI;
   CI.compute(*ClonedFunc);
-  LoopInfo LI(DT);
   BranchProbabilityInfo BPI(*ClonedFunc, CI);
-  ClonedFuncBFI.reset(new BlockFrequencyInfo(*ClonedFunc, BPI, LI));
+  ClonedFuncBFI.reset(new BlockFrequencyInfo(*ClonedFunc, BPI, CI));
 
   // Cache and recycle the CodeExtractor analysis to avoid O(n^2) compile-time.
   CodeExtractorAnalysisCache CEAC(*ClonedFunc);
@@ -1172,9 +1169,8 @@ PartialInlinerImpl::FunctionCloner::doSingleRegionFunctionOutlining() {
   // Manually calculate a BlockFrequencyInfo and BranchProbabilityInfo.
   CycleInfo CI;
   CI.compute(*ClonedFunc);
-  LoopInfo LI(DT);
   BranchProbabilityInfo BPI(*ClonedFunc, CI);
-  ClonedFuncBFI.reset(new BlockFrequencyInfo(*ClonedFunc, BPI, LI));
+  ClonedFuncBFI.reset(new BlockFrequencyInfo(*ClonedFunc, BPI, CI));
 
   // Gather up the blocks that we're going to extract.
   std::vector<BasicBlock *> ToExtract;

llvm/lib/Transforms/Instrumentation/InstrProfiling.cpp

@@ -982,7 +982,7 @@ void InstrLowerer::promoteCounterLoadStores(Function *F) {
   if (Options.UseBFIInPromotion) {
     std::unique_ptr<BranchProbabilityInfo> BPI;
     BPI.reset(new BranchProbabilityInfo(*F, CI, &GetTLI(*F)));
-    BFI.reset(new BlockFrequencyInfo(*F, *BPI, LI));
+    BFI.reset(new BlockFrequencyInfo(*F, *BPI, CI));
   }
 
   for (const auto &LoadStore : PromotionCandidates) {

llvm/lib/Transforms/Instrumentation/PGOInstrumentation.cpp

@@ -1583,10 +1583,8 @@ void PGOUseFunc::populateCoverage() {
   unsigned NumCorruptCoverage = 0;
   CycleInfo CI;
   CI.compute(F);
-  LoopInfo LI;
-  LI.analyze(&F);
   BranchProbabilityInfo BPI(F, CI);
-  BlockFrequencyInfo BFI(F, BPI, LI);
+  BlockFrequencyInfo BFI(F, BPI, CI);
   auto IsBlockDead = [&](const BasicBlock &BB) -> std::optional<bool> {
     if (auto C = BFI.getBlockProfileCount(&BB))
       return C == 0;
@@ -2085,10 +2083,10 @@ PreservedAnalyses PGOInstrumentationGen::run(Module &M,
 
 // Using the ratio b/w sums of profile count values and BFI count values to
 // adjust the func entry count.
-static void fixFuncEntryCount(PGOUseFunc &Func, LoopInfo &LI,
+static void fixFuncEntryCount(PGOUseFunc &Func, CycleInfo &CI,
                               BranchProbabilityInfo &NBPI) {
   Function &F = Func.getFunc();
-  BlockFrequencyInfo NBFI(F, NBPI, LI);
+  BlockFrequencyInfo NBFI(F, NBPI, CI);
 #ifndef NDEBUG
   auto BFIEntryCount = F.getEntryCount();
   assert(BFIEntryCount && (*BFIEntryCount > 0) && "Invalid BFI Entrycount");
@@ -2131,12 +2129,12 @@ static void fixFuncEntryCount(PGOUseFunc &Func, LoopInfo &LI,
 
 // Compare the profile count values with BFI count values, and print out
 // the non-matching ones.
-static void verifyFuncBFI(PGOUseFunc &Func, LoopInfo &LI,
+static void verifyFuncBFI(PGOUseFunc &Func, CycleInfo &CI,
                           BranchProbabilityInfo &NBPI,
                           uint64_t HotCountThreshold,
                           uint64_t ColdCountThreshold) {
   Function &F = Func.getFunc();
-  BlockFrequencyInfo NBFI(F, NBPI, LI);
+  BlockFrequencyInfo NBFI(F, NBPI, CI);
   //  bool PrintFunc = false;
   bool HotBBOnly = PGOVerifyHotBFI;
   StringRef Msg;
@@ -2341,14 +2339,12 @@ static bool annotateAllFunctions(
     if (PGOViewCounts != PGOVCT_None &&
         (ViewBlockFreqFuncName.empty() ||
          F.getName() == ViewBlockFreqFuncName)) {
-      LoopInfo LI;
-      LI.analyze(&F);
       CycleInfo CI;
       CI.compute(F);
       std::unique_ptr<BranchProbabilityInfo> NewBPI =
           std::make_unique<BranchProbabilityInfo>(F, CI);
       std::unique_ptr<BlockFrequencyInfo> NewBFI =
-          std::make_unique<BlockFrequencyInfo>(F, *NewBPI, LI);
+          std::make_unique<BlockFrequencyInfo>(F, *NewBPI, CI);
       if (PGOViewCounts == PGOVCT_Graph)
         NewBFI->view();
       else if (PGOViewCounts == PGOVCT_Text) {
@@ -2373,13 +2369,11 @@ static bool annotateAllFunctions(
     if (PGOVerifyBFI || PGOVerifyHotBFI || PGOFixEntryCount) {
       CycleInfo CI;
       CI.compute(F);
-      LoopInfo LI;
-      LI.analyze(&F);
       BranchProbabilityInfo NBPI(F, CI);
 
       // Fix func entry count.
       if (PGOFixEntryCount)
-        fixFuncEntryCount(Func, LI, NBPI);
+        fixFuncEntryCount(Func, CI, NBPI);
 
       // Verify BlockFrequency information.
       uint64_t HotCountThreshold = 0, ColdCountThreshold = 0;
@@ -2387,7 +2381,7 @@ static bool annotateAllFunctions(
         HotCountThreshold = PSI->getOrCompHotCountThreshold();
         ColdCountThreshold = PSI->getOrCompColdCountThreshold();
       }
-      verifyFuncBFI(Func, LI, NBPI, HotCountThreshold, ColdCountThreshold);
+      verifyFuncBFI(Func, CI, NBPI, HotCountThreshold, ColdCountThreshold);
     }
   }
 

llvm/lib/Transforms/Scalar/InductiveRangeCheckElimination.cpp

@@ -52,6 +52,7 @@
 #include "llvm/ADT/Twine.h"
 #include "llvm/Analysis/BlockFrequencyInfo.h"
 #include "llvm/Analysis/BranchProbabilityInfo.h"
+#include "llvm/Analysis/CycleAnalysis.h"
 #include "llvm/Analysis/LoopAnalysisManager.h"
 #include "llvm/Analysis/LoopInfo.h"
 #include "llvm/Analysis/ScalarEvolution.h"
@@ -927,6 +928,7 @@ PreservedAnalyses IRCEPass::run(Function &F, FunctionAnalysisManager &AM) {
 
     if (CFGChanged && !SkipProfitabilityChecks) {
       PreservedAnalyses PA = PreservedAnalyses::all();
+      PA.abandon<CycleAnalysis>();
       PA.abandon<BlockFrequencyAnalysis>();
       AM.invalidate(F, PA);
     }
@@ -945,6 +947,7 @@ PreservedAnalyses IRCEPass::run(Function &F, FunctionAnalysisManager &AM) {
       Changed = true;
       if (!SkipProfitabilityChecks) {
         PreservedAnalyses PA = PreservedAnalyses::all();
+        PA.abandon<CycleAnalysis>();
         PA.abandon<BlockFrequencyAnalysis>();
         AM.invalidate(F, PA);
       }

llvm/test/CodeGen/AArch64/GlobalISel/gisel-commandline-option.ll

@@ -73,7 +73,6 @@
 ; VERIFY-NEXT:   Verify generated machine code
 ; ENABLED-NEXT: Analysis for ComputingKnownBits
 ; ENABLED-O1-NEXT: Lazy Branch Probability Analysis
-; ENABLED-O1-NEXT: Natural Loop Information
 ; ENABLED-O1-NEXT: Lazy Block Frequency Analysis
 ; ENABLED-NEXT:  InstructionSelect
 ; ENABLED-O1-NEXT:  AArch64 Post Select Optimizer

llvm/test/CodeGen/AArch64/O3-pipeline.ll

@@ -52,7 +52,6 @@
 ; CHECK-NEXT:       Cycle Info Analysis
 ; CHECK-NEXT:       Post-Dominator Tree Construction
 ; CHECK-NEXT:       Branch Probability Analysis
-; CHECK-NEXT:       Natural Loop Information
 ; CHECK-NEXT:       Block Frequency Analysis
 ; CHECK-NEXT:       Constant Hoisting
 ; CHECK-NEXT:       Replace intrinsics with calls to vector library
@@ -127,7 +126,6 @@
 ; CHECK-NEXT:       RegBankSelect
 ; CHECK-NEXT:       Analysis for ComputingKnownBits
 ; CHECK-NEXT:       Lazy Branch Probability Analysis
-; CHECK-NEXT:       Natural Loop Information
 ; CHECK-NEXT:       Lazy Block Frequency Analysis
 ; CHECK-NEXT:       InstructionSelect
 ; CHECK-NEXT:       ResetMachineFunction
@@ -163,13 +161,14 @@
 ; CHECK-NEXT:       AArch64 Stack Tagging PreRA
 ; CHECK-NEXT:       MachineDominator Tree Construction
 ; CHECK-NEXT:       Machine Natural Loop Construction
+; CHECK-NEXT:       Machine Cycle Info Analysis
 ; CHECK-NEXT:       Machine Block Frequency Analysis
 ; CHECK-NEXT:       Early Machine Loop Invariant Code Motion
 ; CHECK-NEXT:       MachineDominator Tree Construction
+; CHECK-NEXT:       Machine Cycle Info Analysis
 ; CHECK-NEXT:       Machine Block Frequency Analysis
 ; CHECK-NEXT:       Machine Common Subexpression Elimination
 ; CHECK-NEXT:       MachinePostDominator Tree Construction
-; CHECK-NEXT:       Machine Cycle Info Analysis
 ; CHECK-NEXT:       Machine code sinking
 ; CHECK-NEXT:       Peephole Optimizations
 ; CHECK-NEXT:       Remove dead machine instructions
@@ -210,10 +209,11 @@
 ; CHECK-NEXT:       Remove Redundant DEBUG_VALUE analysis
 ; CHECK-NEXT:       Fixup Statepoint Caller Saved
 ; CHECK-NEXT:       PostRA Machine Sink
-; CHECK-NEXT:       MachineDominator Tree Construction
-; CHECK-NEXT:       Machine Natural Loop Construction
+; CHECK-NEXT:       Machine Cycle Info Analysis
 ; CHECK-NEXT:       Machine Block Frequency Analysis
+; CHECK-NEXT:       MachineDominator Tree Construction
 ; CHECK-NEXT:       MachinePostDominator Tree Construction
+; CHECK-NEXT:       Machine Natural Loop Construction
 ; CHECK-NEXT:       Lazy Machine Block Frequency Analysis
 ; CHECK-NEXT:       Machine Optimization Remark Emitter
 ; CHECK-NEXT:       Shrink Wrapping analysis
@@ -233,6 +233,7 @@
 ; CHECK-NEXT:       Falkor HW Prefetch Fix Late Phase
 ; CHECK-NEXT:       PostRA Machine Instruction Scheduler
 ; CHECK-NEXT:       Analyze Machine Code For Garbage Collection
+; CHECK-NEXT:       Machine Cycle Info Analysis
 ; CHECK-NEXT:       Machine Block Frequency Analysis
 ; CHECK-NEXT:       MachinePostDominator Tree Construction
 ; CHECK-NEXT:       Branch Probability Basic Block Placement

llvm/test/CodeGen/AArch64/arm64-opt-remarks-lazy-bfi.ll

@@ -65,7 +65,7 @@
 ; HOTNESS-NEXT: Executing Pass 'Lazy Machine Block Frequency Analysis'
 ; HOTNESS-NEXT: Executing Pass 'Machine Optimization Remark Emitter'
 ; HOTNESS-NEXT: Building MachineBlockFrequencyInfo on the fly
-; HOTNESS-NEXT: Building LoopInfo on the fly
+; HOTNESS-NEXT: Building CycleInfo on the fly
 ; HOTNESS-NOT: Executing Pass
 ; HOTNESS: block-frequency: empty_func
 ; HOTNESS-NOT: Executing Pass

llvm/test/CodeGen/AArch64/late-taildup-computed-goto.ll

@@ -42,21 +42,7 @@ define void @test_interp(ptr %frame, ptr %dst) {
 ; CHECK-NEXT:    add x24, x24, #1
 ; CHECK-NEXT:    br x8
 ; CHECK-NEXT:  Ltmp1: ; Block address taken
-; CHECK-NEXT:  LBB0_2: ; %op1.bb
-; CHECK-NEXT:    str xzr, [x19]
-; CHECK-NEXT:  Ltmp2: ; Block address taken
-; CHECK-NEXT:  LBB0_3: ; %op6.bb
-; CHECK-NEXT:    ; =>This Inner Loop Header: Depth=1
-; CHECK-NEXT:    ldr x0, [x20, #-8]!
-; CHECK-NEXT:    ldr x8, [x0, #8]
-; CHECK-NEXT:    str x22, [x0]
-; CHECK-NEXT:    ldr x8, [x8, #48]
-; CHECK-NEXT:    blr x8
-; CHECK-NEXT:    add x8, x21, x24, lsl #3
-; CHECK-NEXT:    add x24, x24, #1
-; CHECK-NEXT:    br x8
-; CHECK-NEXT:  Ltmp3: ; Block address taken
-; CHECK-NEXT:  LBB0_4: ; %op2.bb
+; CHECK-NEXT:  LBB0_2: ; %op2.bb
 ; CHECK-NEXT:    ; =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    add x8, x21, x24, lsl #3
 ; CHECK-NEXT:    mov x20, xzr
@@ -64,10 +50,10 @@ define void @test_interp(ptr %frame, ptr %dst) {
 ; CHECK-NEXT:    mov x23, xzr
 ; CHECK-NEXT:    add x24, x24, #1
 ; CHECK-NEXT:    br x8
-; CHECK-NEXT:  Ltmp4: ; Block address taken
-; CHECK-NEXT:  LBB0_5: ; %op4.bb
-; CHECK-NEXT:  Ltmp5: ; Block address taken
-; CHECK-NEXT:  LBB0_6: ; %op5.bb
+; CHECK-NEXT:  Ltmp2: ; Block address taken
+; CHECK-NEXT:  LBB0_3: ; %op4.bb
+; CHECK-NEXT:  Ltmp3: ; Block address taken
+; CHECK-NEXT:  LBB0_4: ; %op5.bb
 ; CHECK-NEXT:    ; =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    str x23, [x19]
 ; CHECK-NEXT:    ldur x8, [x23, #12]
@@ -78,6 +64,20 @@ define void @test_interp(ptr %frame, ptr %dst) {
 ; CHECK-NEXT:    add x20, x20, #8
 ; CHECK-NEXT:    add x24, x24, #1
 ; CHECK-NEXT:    br x8
+; CHECK-NEXT:  Ltmp4: ; Block address taken
+; CHECK-NEXT:  LBB0_5: ; %op1.bb
+; CHECK-NEXT:    str xzr, [x19]
+; CHECK-NEXT:  Ltmp5: ; Block address taken
+; CHECK-NEXT:  LBB0_6: ; %op6.bb
+; CHECK-NEXT:    ; =>This Inner Loop Header: Depth=1
+; CHECK-NEXT:    ldr x0, [x20, #-8]!
+; CHECK-NEXT:    ldr x8, [x0, #8]
+; CHECK-NEXT:    str x22, [x0]
+; CHECK-NEXT:    ldr x8, [x8, #48]
+; CHECK-NEXT:    blr x8
+; CHECK-NEXT:    add x8, x21, x24, lsl #3
+; CHECK-NEXT:    add x24, x24, #1
+; CHECK-NEXT:    br x8
 ; CHECK-NEXT:    .loh AdrpAdd Lloh0, Lloh1
 entry:
   br label %loop.header

llvm/test/CodeGen/AMDGPU/llc-pipeline.ll

@@ -235,7 +235,6 @@
 ; GCN-O1-NEXT:      Cycle Info Analysis
 ; GCN-O1-NEXT:      Post-Dominator Tree Construction
 ; GCN-O1-NEXT:      Branch Probability Analysis
-; GCN-O1-NEXT:      Natural Loop Information
 ; GCN-O1-NEXT:      Block Frequency Analysis
 ; GCN-O1-NEXT:      Constant Hoisting
 ; GCN-O1-NEXT:      Replace intrinsics with calls to vector library
@@ -321,7 +320,6 @@
 ; GCN-O1-NEXT:        Branch Probability Analysis
 ; GCN-O1-NEXT:        Assignment Tracking Analysis
 ; GCN-O1-NEXT:        Lazy Branch Probability Analysis
-; GCN-O1-NEXT:        Natural Loop Information
 ; GCN-O1-NEXT:        Lazy Block Frequency Analysis
 ; GCN-O1-NEXT:        AMDGPU DAG->DAG Pattern Instruction Selection
 ; GCN-O1-NEXT:        MachineDominator Tree Construction
@@ -338,13 +336,14 @@
 ; GCN-O1-NEXT:        Remove dead machine instructions
 ; GCN-O1-NEXT:        MachineDominator Tree Construction
 ; GCN-O1-NEXT:        Machine Natural Loop Construction
+; GCN-O1-NEXT:        Machine Cycle Info Analysis
 ; GCN-O1-NEXT:        Machine Block Frequency Analysis
 ; GCN-O1-NEXT:        Early Machine Loop Invariant Code Motion
 ; GCN-O1-NEXT:        MachineDominator Tree Construction
+; GCN-O1-NEXT:        Machine Cycle Info Analysis
 ; GCN-O1-NEXT:        Machine Block Frequency Analysis
 ; GCN-O1-NEXT:        Machine Common Subexpression Elimination
 ; GCN-O1-NEXT:        MachinePostDominator Tree Construction
-; GCN-O1-NEXT:        Machine Cycle Info Analysis
 ; GCN-O1-NEXT:        Machine Register Class Info Analysis
 ; GCN-O1-NEXT:        Machine code sinking
 ; GCN-O1-NEXT:        Peephole Optimizations
@@ -377,10 +376,11 @@
 ; GCN-O1-NEXT:        SI Whole Quad Mode
 ; GCN-O1-NEXT:        SI optimize exec mask operations pre-RA
 ; GCN-O1-NEXT:        AMDGPU Pre-RA Long Branch Reg
-; GCN-O1-NEXT:        Machine Natural Loop Construction
+; GCN-O1-NEXT:        Machine Cycle Info Analysis
 ; GCN-O1-NEXT:        Machine Block Frequency Analysis
 ; GCN-O1-NEXT:        Debug Variable Analysis
 ; GCN-O1-NEXT:        Live Stack Slot Analysis
+; GCN-O1-NEXT:        Machine Natural Loop Construction
 ; GCN-O1-NEXT:        Virtual Register Map
 ; GCN-O1-NEXT:        Live Register Matrix
 ; GCN-O1-NEXT:        Bundle Machine CFG Edges
@@ -390,7 +390,6 @@
 ; GCN-O1-NEXT:        Greedy Register Allocator
 ; GCN-O1-NEXT:        Virtual Register Rewriter
 ; GCN-O1-NEXT:        Stack Slot Coloring
-; GCN-O1-NEXT:        Machine Cycle Info Analysis
 ; GCN-O1-NEXT:        SI lower SGPR spill instructions
 ; GCN-O1-NEXT:        Virtual Register Map
 ; GCN-O1-NEXT:        Live Register Matrix
@@ -416,6 +415,7 @@
 ; GCN-O1-NEXT:        Remove Redundant DEBUG_VALUE analysis
 ; GCN-O1-NEXT:        Fixup Statepoint Caller Saved
 ; GCN-O1-NEXT:        PostRA Machine Sink
+; GCN-O1-NEXT:        Machine Cycle Info Analysis
 ; GCN-O1-NEXT:        Machine Block Frequency Analysis
 ; GCN-O1-NEXT:        MachineDominator Tree Construction
 ; GCN-O1-NEXT:        MachinePostDominator Tree Construction
@@ -434,6 +434,7 @@
 ; GCN-O1-NEXT:        MachineDominator Tree Construction
 ; GCN-O1-NEXT:        Machine Natural Loop Construction
 ; GCN-O1-NEXT:        PostRA Machine Instruction Scheduler
+; GCN-O1-NEXT:        Machine Cycle Info Analysis
 ; GCN-O1-NEXT:        Machine Block Frequency Analysis
 ; GCN-O1-NEXT:        MachinePostDominator Tree Construction
 ; GCN-O1-NEXT:        Branch Probability Basic Block Placement
@@ -548,7 +549,6 @@
 ; GCN-O1-OPTS-NEXT:      Cycle Info Analysis
 ; GCN-O1-OPTS-NEXT:      Post-Dominator Tree Construction
 ; GCN-O1-OPTS-NEXT:      Branch Probability Analysis
-; GCN-O1-OPTS-NEXT:      Natural Loop Information
 ; GCN-O1-OPTS-NEXT:      Block Frequency Analysis
 ; GCN-O1-OPTS-NEXT:      Constant Hoisting
 ; GCN-O1-OPTS-NEXT:      Replace intrinsics with calls to vector library
@@ -641,7 +641,6 @@
 ; GCN-O1-OPTS-NEXT:        Branch Probability Analysis
 ; GCN-O1-OPTS-NEXT:        Assignment Tracking Analysis
 ; GCN-O1-OPTS-NEXT:        Lazy Branch Probability Analysis
-; GCN-O1-OPTS-NEXT:        Natural Loop Information
 ; GCN-O1-OPTS-NEXT:        Lazy Block Frequency Analysis
 ; GCN-O1-OPTS-NEXT:        AMDGPU DAG->DAG Pattern Instruction Selection
 ; GCN-O1-OPTS-NEXT:        MachineDominator Tree Construction
@@ -658,13 +657,14 @@
 ; GCN-O1-OPTS-NEXT:        Remove dead machine instructions
 ; GCN-O1-OPTS-NEXT:        MachineDominator Tree Construction
 ; GCN-O1-OPTS-NEXT:        Machine Natural Loop Construction
+; GCN-O1-OPTS-NEXT:        Machine Cycle Info Analysis
 ; GCN-O1-OPTS-NEXT:        Machine Block Frequency Analysis
 ; GCN-O1-OPTS-NEXT:        Early Machine Loop Invariant Code Motion
 ; GCN-O1-OPTS-NEXT:        MachineDominator Tree Construction
+; GCN-O1-OPTS-NEXT:        Machine Cycle Info Analysis
 ; GCN-O1-OPTS-NEXT:        Machine Block Frequency Analysis
 ; GCN-O1-OPTS-NEXT:        Machine Common Subexpression Elimination
 ; GCN-O1-OPTS-NEXT:        MachinePostDominator Tree Construction
-; GCN-O1-OPTS-NEXT:        Machine Cycle Info Analysis
 ; GCN-O1-OPTS-NEXT:        Machine Register Class Info Analysis
 ; GCN-O1-OPTS-NEXT:        Machine code sinking
 ; GCN-O1-OPTS-NEXT:        Peephole Optimizations
@@ -676,6 +676,7 @@
 ; GCN-O1-OPTS-NEXT:        MachineDominator Tree Construction
 ; GCN-O1-OPTS-NEXT:        Early Machine Loop Invariant Code Motion
 ; GCN-O1-OPTS-NEXT:        MachineDominator Tree Construction
+; GCN-O1-OPTS-NEXT:        Machine Cycle Info Analysis
 ; GCN-O1-OPTS-NEXT:        Machine Block Frequency Analysis
 ; GCN-O1-OPTS-NEXT:        Machine Common Subexpression Elimination
 ; GCN-O1-OPTS-NEXT:        SI Fold Operands
@@ -704,10 +705,11 @@
 ; GCN-O1-OPTS-NEXT:        SI Whole Quad Mode
 ; GCN-O1-OPTS-NEXT:        SI optimize exec mask operations pre-RA
 ; GCN-O1-OPTS-NEXT:        AMDGPU Pre-RA Long Branch Reg
-; GCN-O1-OPTS-NEXT:        Machine Natural Loop Construction
+; GCN-O1-OPTS-NEXT:        Machine Cycle Info Analysis
 ; GCN-O1-OPTS-NEXT:        Machine Block Frequency Analysis
 ; GCN-O1-OPTS-NEXT:        Debug Variable Analysis
 ; GCN-O1-OPTS-NEXT:        Live Stack Slot Analysis
+; GCN-O1-OPTS-NEXT:        Machine Natural Loop Construction
 ; GCN-O1-OPTS-NEXT:        Virtual Register Map
 ; GCN-O1-OPTS-NEXT:        Live Register Matrix
 ; GCN-O1-OPTS-NEXT:        Bundle Machine CFG Edges
@@ -717,7 +719,6 @@
 ; GCN-O1-OPTS-NEXT:        Greedy Register Allocator
 ; GCN-O1-OPTS-NEXT:        Virtual Register Rewriter
 ; GCN-O1-OPTS-NEXT:        Stack Slot Coloring
-; GCN-O1-OPTS-NEXT:        Machine Cycle Info Analysis
 ; GCN-O1-OPTS-NEXT:        SI lower SGPR spill instructions
 ; GCN-O1-OPTS-NEXT:        Virtual Register Map
 ; GCN-O1-OPTS-NEXT:        Live Register Matrix
@@ -743,6 +744,7 @@
 ; GCN-O1-OPTS-NEXT:        Remove Redundant DEBUG_VALUE analysis
 ; GCN-O1-OPTS-NEXT:        Fixup Statepoint Caller Saved
 ; GCN-O1-OPTS-NEXT:        PostRA Machine Sink
+; GCN-O1-OPTS-NEXT:        Machine Cycle Info Analysis
 ; GCN-O1-OPTS-NEXT:        Machine Block Frequency Analysis
 ; GCN-O1-OPTS-NEXT:        MachineDominator Tree Construction
 ; GCN-O1-OPTS-NEXT:        MachinePostDominator Tree Construction
@@ -761,6 +763,7 @@
 ; GCN-O1-OPTS-NEXT:        MachineDominator Tree Construction
 ; GCN-O1-OPTS-NEXT:        Machine Natural Loop Construction
 ; GCN-O1-OPTS-NEXT:        PostRA Machine Instruction Scheduler
+; GCN-O1-OPTS-NEXT:        Machine Cycle Info Analysis
 ; GCN-O1-OPTS-NEXT:        Machine Block Frequency Analysis
 ; GCN-O1-OPTS-NEXT:        MachinePostDominator Tree Construction
 ; GCN-O1-OPTS-NEXT:        Branch Probability Basic Block Placement
@@ -878,7 +881,6 @@
 ; GCN-O2-NEXT:      Cycle Info Analysis
 ; GCN-O2-NEXT:      Post-Dominator Tree Construction
 ; GCN-O2-NEXT:      Branch Probability Analysis
-; GCN-O2-NEXT:      Natural Loop Information
 ; GCN-O2-NEXT:      Block Frequency Analysis
 ; GCN-O2-NEXT:      Constant Hoisting
 ; GCN-O2-NEXT:      Replace intrinsics with calls to vector library
@@ -972,7 +974,6 @@
 ; GCN-O2-NEXT:        Branch Probability Analysis
 ; GCN-O2-NEXT:        Assignment Tracking Analysis
 ; GCN-O2-NEXT:        Lazy Branch Probability Analysis
-; GCN-O2-NEXT:        Natural Loop Information
 ; GCN-O2-NEXT:        Lazy Block Frequency Analysis
 ; GCN-O2-NEXT:        AMDGPU DAG->DAG Pattern Instruction Selection
 ; GCN-O2-NEXT:        MachineDominator Tree Construction
@@ -989,13 +990,14 @@
 ; GCN-O2-NEXT:        Remove dead machine instructions
 ; GCN-O2-NEXT:        MachineDominator Tree Construction
 ; GCN-O2-NEXT:        Machine Natural Loop Construction
+; GCN-O2-NEXT:        Machine Cycle Info Analysis
 ; GCN-O2-NEXT:        Machine Block Frequency Analysis
 ; GCN-O2-NEXT:        Early Machine Loop Invariant Code Motion
 ; GCN-O2-NEXT:        MachineDominator Tree Construction
+; GCN-O2-NEXT:        Machine Cycle Info Analysis
 ; GCN-O2-NEXT:        Machine Block Frequency Analysis
 ; GCN-O2-NEXT:        Machine Common Subexpression Elimination
 ; GCN-O2-NEXT:        MachinePostDominator Tree Construction
-; GCN-O2-NEXT:        Machine Cycle Info Analysis
 ; GCN-O2-NEXT:        Machine Register Class Info Analysis
 ; GCN-O2-NEXT:        Machine code sinking
 ; GCN-O2-NEXT:        Peephole Optimizations
@@ -1007,6 +1009,7 @@
 ; GCN-O2-NEXT:        MachineDominator Tree Construction
 ; GCN-O2-NEXT:        Early Machine Loop Invariant Code Motion
 ; GCN-O2-NEXT:        MachineDominator Tree Construction
+; GCN-O2-NEXT:        Machine Cycle Info Analysis
 ; GCN-O2-NEXT:        Machine Block Frequency Analysis
 ; GCN-O2-NEXT:        Machine Common Subexpression Elimination
 ; GCN-O2-NEXT:        SI Fold Operands
@@ -1036,10 +1039,11 @@
 ; GCN-O2-NEXT:        SI optimize exec mask operations pre-RA
 ; GCN-O2-NEXT:        SI Form memory clauses
 ; GCN-O2-NEXT:        AMDGPU Pre-RA Long Branch Reg
-; GCN-O2-NEXT:        Machine Natural Loop Construction
+; GCN-O2-NEXT:        Machine Cycle Info Analysis
 ; GCN-O2-NEXT:        Machine Block Frequency Analysis
 ; GCN-O2-NEXT:        Debug Variable Analysis
 ; GCN-O2-NEXT:        Live Stack Slot Analysis
+; GCN-O2-NEXT:        Machine Natural Loop Construction
 ; GCN-O2-NEXT:        Virtual Register Map
 ; GCN-O2-NEXT:        Live Register Matrix
 ; GCN-O2-NEXT:        Bundle Machine CFG Edges
@@ -1049,7 +1053,6 @@
 ; GCN-O2-NEXT:        Greedy Register Allocator
 ; GCN-O2-NEXT:        Virtual Register Rewriter
 ; GCN-O2-NEXT:        Stack Slot Coloring
-; GCN-O2-NEXT:        Machine Cycle Info Analysis
 ; GCN-O2-NEXT:        SI lower SGPR spill instructions
 ; GCN-O2-NEXT:        Virtual Register Map
 ; GCN-O2-NEXT:        Live Register Matrix
@@ -1075,6 +1078,7 @@
 ; GCN-O2-NEXT:        Remove Redundant DEBUG_VALUE analysis
 ; GCN-O2-NEXT:        Fixup Statepoint Caller Saved
 ; GCN-O2-NEXT:        PostRA Machine Sink
+; GCN-O2-NEXT:        Machine Cycle Info Analysis
 ; GCN-O2-NEXT:        Machine Block Frequency Analysis
 ; GCN-O2-NEXT:        MachineDominator Tree Construction
 ; GCN-O2-NEXT:        MachinePostDominator Tree Construction
@@ -1093,6 +1097,7 @@
 ; GCN-O2-NEXT:        MachineDominator Tree Construction
 ; GCN-O2-NEXT:        Machine Natural Loop Construction
 ; GCN-O2-NEXT:        PostRA Machine Instruction Scheduler
+; GCN-O2-NEXT:        Machine Cycle Info Analysis
 ; GCN-O2-NEXT:        Machine Block Frequency Analysis
 ; GCN-O2-NEXT:        MachinePostDominator Tree Construction
 ; GCN-O2-NEXT:        Branch Probability Basic Block Placement
@@ -1217,7 +1222,6 @@
 ; GCN-O3-NEXT:      Cycle Info Analysis
 ; GCN-O3-NEXT:      Post-Dominator Tree Construction
 ; GCN-O3-NEXT:      Branch Probability Analysis
-; GCN-O3-NEXT:      Natural Loop Information
 ; GCN-O3-NEXT:      Block Frequency Analysis
 ; GCN-O3-NEXT:      Constant Hoisting
 ; GCN-O3-NEXT:      Replace intrinsics with calls to vector library
@@ -1319,7 +1323,6 @@
 ; GCN-O3-NEXT:        Branch Probability Analysis
 ; GCN-O3-NEXT:        Assignment Tracking Analysis
 ; GCN-O3-NEXT:        Lazy Branch Probability Analysis
-; GCN-O3-NEXT:        Natural Loop Information
 ; GCN-O3-NEXT:        Lazy Block Frequency Analysis
 ; GCN-O3-NEXT:        AMDGPU DAG->DAG Pattern Instruction Selection
 ; GCN-O3-NEXT:        MachineDominator Tree Construction
@@ -1336,13 +1339,14 @@
 ; GCN-O3-NEXT:        Remove dead machine instructions
 ; GCN-O3-NEXT:        MachineDominator Tree Construction
 ; GCN-O3-NEXT:        Machine Natural Loop Construction
+; GCN-O3-NEXT:        Machine Cycle Info Analysis
 ; GCN-O3-NEXT:        Machine Block Frequency Analysis
 ; GCN-O3-NEXT:        Early Machine Loop Invariant Code Motion
 ; GCN-O3-NEXT:        MachineDominator Tree Construction
+; GCN-O3-NEXT:        Machine Cycle Info Analysis
 ; GCN-O3-NEXT:        Machine Block Frequency Analysis
 ; GCN-O3-NEXT:        Machine Common Subexpression Elimination
 ; GCN-O3-NEXT:        MachinePostDominator Tree Construction
-; GCN-O3-NEXT:        Machine Cycle Info Analysis
 ; GCN-O3-NEXT:        Machine Register Class Info Analysis
 ; GCN-O3-NEXT:        Machine code sinking
 ; GCN-O3-NEXT:        Peephole Optimizations
@@ -1354,6 +1358,7 @@
 ; GCN-O3-NEXT:        MachineDominator Tree Construction
 ; GCN-O3-NEXT:        Early Machine Loop Invariant Code Motion
 ; GCN-O3-NEXT:        MachineDominator Tree Construction
+; GCN-O3-NEXT:        Machine Cycle Info Analysis
 ; GCN-O3-NEXT:        Machine Block Frequency Analysis
 ; GCN-O3-NEXT:        Machine Common Subexpression Elimination
 ; GCN-O3-NEXT:        SI Fold Operands
@@ -1383,10 +1388,11 @@
 ; GCN-O3-NEXT:        SI optimize exec mask operations pre-RA
 ; GCN-O3-NEXT:        SI Form memory clauses
 ; GCN-O3-NEXT:        AMDGPU Pre-RA Long Branch Reg
-; GCN-O3-NEXT:        Machine Natural Loop Construction
+; GCN-O3-NEXT:        Machine Cycle Info Analysis
 ; GCN-O3-NEXT:        Machine Block Frequency Analysis
 ; GCN-O3-NEXT:        Debug Variable Analysis
 ; GCN-O3-NEXT:        Live Stack Slot Analysis
+; GCN-O3-NEXT:        Machine Natural Loop Construction
 ; GCN-O3-NEXT:        Virtual Register Map
 ; GCN-O3-NEXT:        Live Register Matrix
 ; GCN-O3-NEXT:        Bundle Machine CFG Edges
@@ -1396,7 +1402,6 @@
 ; GCN-O3-NEXT:        Greedy Register Allocator
 ; GCN-O3-NEXT:        Virtual Register Rewriter
 ; GCN-O3-NEXT:        Stack Slot Coloring
-; GCN-O3-NEXT:        Machine Cycle Info Analysis
 ; GCN-O3-NEXT:        SI lower SGPR spill instructions
 ; GCN-O3-NEXT:        Virtual Register Map
 ; GCN-O3-NEXT:        Live Register Matrix
@@ -1422,6 +1427,7 @@
 ; GCN-O3-NEXT:        Remove Redundant DEBUG_VALUE analysis
 ; GCN-O3-NEXT:        Fixup Statepoint Caller Saved
 ; GCN-O3-NEXT:        PostRA Machine Sink
+; GCN-O3-NEXT:        Machine Cycle Info Analysis
 ; GCN-O3-NEXT:        Machine Block Frequency Analysis
 ; GCN-O3-NEXT:        MachineDominator Tree Construction
 ; GCN-O3-NEXT:        MachinePostDominator Tree Construction
@@ -1440,6 +1446,7 @@
 ; GCN-O3-NEXT:        MachineDominator Tree Construction
 ; GCN-O3-NEXT:        Machine Natural Loop Construction
 ; GCN-O3-NEXT:        PostRA Machine Instruction Scheduler
+; GCN-O3-NEXT:        Machine Cycle Info Analysis
 ; GCN-O3-NEXT:        Machine Block Frequency Analysis
 ; GCN-O3-NEXT:        MachinePostDominator Tree Construction
 ; GCN-O3-NEXT:        Branch Probability Basic Block Placement

llvm/test/CodeGen/AMDGPU/sgpr-regalloc-flags.ll

@@ -18,7 +18,6 @@
 ; DEFAULT: Greedy Register Allocator
 ; DEFAULT-NEXT: Virtual Register Rewriter
 ; DEFAULT-NEXT: Stack Slot Coloring
-; DEFAULT-NEXT: Machine Cycle Info Analysis
 ; DEFAULT-NEXT: SI lower SGPR spill instructions
 ; DEFAULT-NEXT: Virtual Register Map
 ; DEFAULT-NEXT: Live Register Matrix
@@ -58,14 +57,14 @@
 
 ; BASIC-DEFAULT: Debug Variable Analysis
 ; BASIC-DEFAULT-NEXT: Live Stack Slot Analysis
-; BASIC-DEFAULT-NEXT: Machine Natural Loop Construction
+; BASIC-DEFAULT-NEXT: Machine Cycle Info Analysis
 ; BASIC-DEFAULT-NEXT: Machine Block Frequency Analysis
+; BASIC-DEFAULT-NEXT: Machine Natural Loop Construction
 ; BASIC-DEFAULT-NEXT: Virtual Register Map
 ; BASIC-DEFAULT-NEXT: Live Register Matrix
 ; BASIC-DEFAULT-NEXT: Basic Register Allocator
 ; BASIC-DEFAULT-NEXT: Virtual Register Rewriter
 ; BASIC-DEFAULT-NEXT: Stack Slot Coloring
-; BASIC-DEFAULT-NEXT: Machine Cycle Info Analysis
 ; BASIC-DEFAULT-NEXT: SI lower SGPR spill instructions
 ; BASIC-DEFAULT-NEXT: Virtual Register Map
 ; BASIC-DEFAULT-NEXT: Live Register Matrix
@@ -94,7 +93,6 @@
 ; DEFAULT-BASIC: Greedy Register Allocator
 ; DEFAULT-BASIC-NEXT: Virtual Register Rewriter
 ; DEFAULT-BASIC-NEXT: Stack Slot Coloring
-; DEFAULT-BASIC-NEXT: Machine Cycle Info Analysis
 ; DEFAULT-BASIC-NEXT: SI lower SGPR spill instructions
 ; DEFAULT-BASIC-NEXT: Virtual Register Map
 ; DEFAULT-BASIC-NEXT: Live Register Matrix
@@ -118,14 +116,14 @@
 
 ; BASIC-BASIC: Debug Variable Analysis
 ; BASIC-BASIC-NEXT: Live Stack Slot Analysis
-; BASIC-BASIC-NEXT: Machine Natural Loop Construction
+; BASIC-BASIC-NEXT: Machine Cycle Info Analysis
 ; BASIC-BASIC-NEXT: Machine Block Frequency Analysis
+; BASIC-BASIC-NEXT: Machine Natural Loop Construction
 ; BASIC-BASIC-NEXT: Virtual Register Map
 ; BASIC-BASIC-NEXT: Live Register Matrix
 ; BASIC-BASIC-NEXT: Basic Register Allocator
 ; BASIC-BASIC-NEXT: Virtual Register Rewriter
 ; BASIC-BASIC-NEXT: Stack Slot Coloring
-; BASIC-BASIC-NEXT: Machine Cycle Info Analysis
 ; BASIC-BASIC-NEXT: SI lower SGPR spill instructions
 ; BASIC-BASIC-NEXT: Virtual Register Map
 ; BASIC-BASIC-NEXT: Live Register Matrix

llvm/test/CodeGen/ARM/O3-pipeline.ll

@@ -31,7 +31,6 @@
 ; CHECK-NEXT:      Cycle Info Analysis
 ; CHECK-NEXT:      Post-Dominator Tree Construction
 ; CHECK-NEXT:      Branch Probability Analysis
-; CHECK-NEXT:      Natural Loop Information
 ; CHECK-NEXT:      Block Frequency Analysis
 ; CHECK-NEXT:      Constant Hoisting
 ; CHECK-NEXT:      Replace intrinsics with calls to vector library
@@ -81,7 +80,6 @@
 ; CHECK-NEXT:      Branch Probability Analysis
 ; CHECK-NEXT:      Assignment Tracking Analysis
 ; CHECK-NEXT:      Lazy Branch Probability Analysis
-; CHECK-NEXT:      Natural Loop Information
 ; CHECK-NEXT:      Lazy Block Frequency Analysis
 ; CHECK-NEXT:      ARM Instruction Selection
 ; CHECK-NEXT:      Finalize ISel and expand pseudo-instructions
@@ -94,13 +92,14 @@
 ; CHECK-NEXT:      Remove dead machine instructions
 ; CHECK-NEXT:      MachineDominator Tree Construction
 ; CHECK-NEXT:      Machine Natural Loop Construction
+; CHECK-NEXT:      Machine Cycle Info Analysis
 ; CHECK-NEXT:      Machine Block Frequency Analysis
 ; CHECK-NEXT:      Early Machine Loop Invariant Code Motion
 ; CHECK-NEXT:      MachineDominator Tree Construction
+; CHECK-NEXT:      Machine Cycle Info Analysis
 ; CHECK-NEXT:      Machine Block Frequency Analysis
 ; CHECK-NEXT:      Machine Common Subexpression Elimination
 ; CHECK-NEXT:      MachinePostDominator Tree Construction
-; CHECK-NEXT:      Machine Cycle Info Analysis
 ; CHECK-NEXT:      Machine Register Class Info Analysis
 ; CHECK-NEXT:      Machine code sinking
 ; CHECK-NEXT:      Peephole Optimizations
@@ -131,6 +130,7 @@
 ; CHECK-NEXT:      Live Interval Analysis
 ; CHECK-NEXT:      Register Coalescer
 ; CHECK-NEXT:      Rename Disconnected Subregister Components
+; CHECK-NEXT:      Machine Cycle Info Analysis
 ; CHECK-NEXT:      Machine Block Frequency Analysis
 ; CHECK-NEXT:      Machine Instruction Scheduler
 ; CHECK-NEXT:      Debug Variable Analysis
@@ -150,6 +150,7 @@
 ; CHECK-NEXT:      Remove Redundant DEBUG_VALUE analysis
 ; CHECK-NEXT:      Fixup Statepoint Caller Saved
 ; CHECK-NEXT:      PostRA Machine Sink
+; CHECK-NEXT:      Machine Cycle Info Analysis
 ; CHECK-NEXT:      Machine Block Frequency Analysis
 ; CHECK-NEXT:      MachineDominator Tree Construction
 ; CHECK-NEXT:      MachinePostDominator Tree Construction
@@ -170,8 +171,7 @@
 ; CHECK-NEXT:      ARM pseudo instruction expansion pass
 ; CHECK-NEXT:      Insert KCFI indirect call checks
 ; CHECK-NEXT:      Thumb2 instruction size reduce pass
-; CHECK-NEXT:      MachineDominator Tree Construction
-; CHECK-NEXT:      Machine Natural Loop Construction
+; CHECK-NEXT:      Machine Cycle Info Analysis
 ; CHECK-NEXT:      Machine Block Frequency Analysis
 ; CHECK-NEXT:      If Converter
 ; CHECK-NEXT:      Thumb IT blocks insertion pass
@@ -183,10 +183,11 @@
 ; CHECK-NEXT:      ARM Indirect Thunks
 ; CHECK-NEXT:      ARM sls hardening pass
 ; CHECK-NEXT:      Analyze Machine Code For Garbage Collection
-; CHECK-NEXT:      MachineDominator Tree Construction
-; CHECK-NEXT:      Machine Natural Loop Construction
+; CHECK-NEXT:      Machine Cycle Info Analysis
 ; CHECK-NEXT:      Machine Block Frequency Analysis
 ; CHECK-NEXT:      MachinePostDominator Tree Construction
+; CHECK-NEXT:      MachineDominator Tree Construction
+; CHECK-NEXT:      Machine Natural Loop Construction
 ; CHECK-NEXT:      Branch Probability Basic Block Placement
 ; CHECK-NEXT:      Insert fentry calls
 ; CHECK-NEXT:      Insert XRay ops

llvm/test/CodeGen/LoongArch/opt-pipeline.ll

@@ -56,7 +56,6 @@
 ; LAXX-NEXT:       Cycle Info Analysis
 ; LAXX-NEXT:       Post-Dominator Tree Construction
 ; LAXX-NEXT:       Branch Probability Analysis
-; LAXX-NEXT:       Natural Loop Information
 ; LAXX-NEXT:       Block Frequency Analysis
 ; LAXX-NEXT:       Constant Hoisting
 ; LAXX-NEXT:       Replace intrinsics with calls to vector library
@@ -87,7 +86,6 @@
 ; LAXX-NEXT:       Branch Probability Analysis
 ; LAXX-NEXT:       Assignment Tracking Analysis
 ; LAXX-NEXT:       Lazy Branch Probability Analysis
-; LAXX-NEXT:       Natural Loop Information
 ; LAXX-NEXT:       Lazy Block Frequency Analysis
 ; LAXX-NEXT:       LoongArch DAG->DAG Pattern Instruction Selection
 ; LAXX-NEXT:       Finalize ISel and expand pseudo-instructions
@@ -100,13 +98,14 @@
 ; LAXX-NEXT:       Remove dead machine instructions
 ; LAXX-NEXT:       MachineDominator Tree Construction
 ; LAXX-NEXT:       Machine Natural Loop Construction
+; LAXX-NEXT:       Machine Cycle Info Analysis
 ; LAXX-NEXT:       Machine Block Frequency Analysis
 ; LAXX-NEXT:       Early Machine Loop Invariant Code Motion
 ; LAXX-NEXT:       MachineDominator Tree Construction
+; LAXX-NEXT:       Machine Cycle Info Analysis
 ; LAXX-NEXT:       Machine Block Frequency Analysis
 ; LAXX-NEXT:       Machine Common Subexpression Elimination
 ; LAXX-NEXT:       MachinePostDominator Tree Construction
-; LAXX-NEXT:       Machine Cycle Info Analysis
 ; LAXX-NEXT:       Machine Register Class Info Analysis
 ; LAXX-NEXT:       Machine code sinking
 ; LAXX-NEXT:       Peephole Optimizations
@@ -145,6 +144,7 @@
 ; LAXX-NEXT:       Remove Redundant DEBUG_VALUE analysis
 ; LAXX-NEXT:       Fixup Statepoint Caller Saved
 ; LAXX-NEXT:       PostRA Machine Sink
+; LAXX-NEXT:       Machine Cycle Info Analysis
 ; LAXX-NEXT:       Machine Block Frequency Analysis
 ; LAXX-NEXT:       MachineDominator Tree Construction
 ; LAXX-NEXT:       MachinePostDominator Tree Construction
@@ -162,6 +162,7 @@
 ; LAXX-NEXT:       Machine Natural Loop Construction
 ; LAXX-NEXT:       Post RA top-down list latency scheduler
 ; LAXX-NEXT:       Analyze Machine Code For Garbage Collection
+; LAXX-NEXT:       Machine Cycle Info Analysis
 ; LAXX-NEXT:       Machine Block Frequency Analysis
 ; LAXX-NEXT:       MachinePostDominator Tree Construction
 ; LAXX-NEXT:       Branch Probability Basic Block Placement

llvm/test/CodeGen/M68k/pipeline.ll

@@ -25,7 +25,6 @@
 ; CHECK-NEXT:      Cycle Info Analysis
 ; CHECK-NEXT:      Post-Dominator Tree Construction
 ; CHECK-NEXT:      Branch Probability Analysis
-; CHECK-NEXT:      Natural Loop Information
 ; CHECK-NEXT:      Block Frequency Analysis
 ; CHECK-NEXT:      Constant Hoisting
 ; CHECK-NEXT:      Replace intrinsics with calls to vector library
@@ -55,7 +54,6 @@
 ; CHECK-NEXT:      Branch Probability Analysis
 ; CHECK-NEXT:      Assignment Tracking Analysis
 ; CHECK-NEXT:      Lazy Branch Probability Analysis
-; CHECK-NEXT:      Natural Loop Information
 ; CHECK-NEXT:      Lazy Block Frequency Analysis
 ; CHECK-NEXT:      M68k DAG->DAG Pattern Instruction Selection
 ; CHECK-NEXT:      M68k PIC Global Base Reg Initialization
@@ -69,13 +67,14 @@
 ; CHECK-NEXT:      Remove dead machine instructions
 ; CHECK-NEXT:      MachineDominator Tree Construction
 ; CHECK-NEXT:      Machine Natural Loop Construction
+; CHECK-NEXT:      Machine Cycle Info Analysis
 ; CHECK-NEXT:      Machine Block Frequency Analysis
 ; CHECK-NEXT:      Early Machine Loop Invariant Code Motion
 ; CHECK-NEXT:      MachineDominator Tree Construction
+; CHECK-NEXT:      Machine Cycle Info Analysis
 ; CHECK-NEXT:      Machine Block Frequency Analysis
 ; CHECK-NEXT:      Machine Common Subexpression Elimination
 ; CHECK-NEXT:      MachinePostDominator Tree Construction
-; CHECK-NEXT:      Machine Cycle Info Analysis
 ; CHECK-NEXT:      Machine Register Class Info Analysis
 ; CHECK-NEXT:      Machine code sinking
 ; CHECK-NEXT:      Peephole Optimizations
@@ -110,6 +109,7 @@
 ; CHECK-NEXT:      Remove Redundant DEBUG_VALUE analysis
 ; CHECK-NEXT:      Fixup Statepoint Caller Saved
 ; CHECK-NEXT:      PostRA Machine Sink
+; CHECK-NEXT:      Machine Cycle Info Analysis
 ; CHECK-NEXT:      Machine Block Frequency Analysis
 ; CHECK-NEXT:      MachineDominator Tree Construction
 ; CHECK-NEXT:      MachinePostDominator Tree Construction
@@ -128,6 +128,7 @@
 ; CHECK-NEXT:      Machine Natural Loop Construction
 ; CHECK-NEXT:      Post RA top-down list latency scheduler
 ; CHECK-NEXT:      Analyze Machine Code For Garbage Collection
+; CHECK-NEXT:      Machine Cycle Info Analysis
 ; CHECK-NEXT:      Machine Block Frequency Analysis
 ; CHECK-NEXT:      MachinePostDominator Tree Construction
 ; CHECK-NEXT:      Branch Probability Basic Block Placement

llvm/test/CodeGen/PowerPC/O3-pipeline.ll

@@ -58,7 +58,6 @@
 ; CHECK-NEXT:       Cycle Info Analysis
 ; CHECK-NEXT:       Post-Dominator Tree Construction
 ; CHECK-NEXT:       Branch Probability Analysis
-; CHECK-NEXT:       Natural Loop Information
 ; CHECK-NEXT:       Block Frequency Analysis
 ; CHECK-NEXT:       Constant Hoisting
 ; CHECK-NEXT:       Replace intrinsics with calls to vector library
@@ -98,7 +97,6 @@
 ; CHECK-NEXT:       Branch Probability Analysis
 ; CHECK-NEXT:       Assignment Tracking Analysis
 ; CHECK-NEXT:       Lazy Branch Probability Analysis
-; CHECK-NEXT:       Natural Loop Information
 ; CHECK-NEXT:       Lazy Block Frequency Analysis
 ; CHECK-NEXT:       PowerPC DAG->DAG Pattern Instruction Selection
 ; CHECK-NEXT:       MachineDominator Tree Construction
@@ -122,13 +120,14 @@
 ; CHECK-NEXT:       Machine Register Class Info Analysis
 ; CHECK-NEXT:       Lazy Machine Block Frequency Analysis
 ; CHECK-NEXT:       Machine InstCombiner
+; CHECK-NEXT:       Machine Cycle Info Analysis
 ; CHECK-NEXT:       Machine Block Frequency Analysis
 ; CHECK-NEXT:       Early Machine Loop Invariant Code Motion
 ; CHECK-NEXT:       MachineDominator Tree Construction
+; CHECK-NEXT:       Machine Cycle Info Analysis
 ; CHECK-NEXT:       Machine Block Frequency Analysis
 ; CHECK-NEXT:       Machine Common Subexpression Elimination
 ; CHECK-NEXT:       MachinePostDominator Tree Construction
-; CHECK-NEXT:       Machine Cycle Info Analysis
 ; CHECK-NEXT:       Machine code sinking
 ; CHECK-NEXT:       Peephole Optimizations
 ; CHECK-NEXT:       Remove dead machine instructions
@@ -137,7 +136,7 @@
 ; CHECK-NEXT:       Live Variable Analysis
 ; CHECK-NEXT:       MachineDominator Tree Construction
 ; CHECK-NEXT:       MachinePostDominator Tree Construction
-; CHECK-NEXT:       Machine Natural Loop Construction
+; CHECK-NEXT:       Machine Cycle Info Analysis
 ; CHECK-NEXT:       Machine Block Frequency Analysis
 ; CHECK-NEXT:       PowerPC MI Peephole Optimization
 ; CHECK-NEXT:       Remove dead machine instructions
@@ -167,6 +166,7 @@
 ; CHECK-NEXT:       Live Interval Analysis
 ; CHECK-NEXT:       Register Coalescer
 ; CHECK-NEXT:       Rename Disconnected Subregister Components
+; CHECK-NEXT:       Machine Cycle Info Analysis
 ; CHECK-NEXT:       Machine Block Frequency Analysis
 ; CHECK-NEXT:       Machine Instruction Scheduler
 ; CHECK-NEXT:       PowerPC VSX FMA Mutation
@@ -188,6 +188,7 @@
 ; CHECK-NEXT:       Remove Redundant DEBUG_VALUE analysis
 ; CHECK-NEXT:       Fixup Statepoint Caller Saved
 ; CHECK-NEXT:       PostRA Machine Sink
+; CHECK-NEXT:       Machine Cycle Info Analysis
 ; CHECK-NEXT:       Machine Block Frequency Analysis
 ; CHECK-NEXT:       MachineDominator Tree Construction
 ; CHECK-NEXT:       MachinePostDominator Tree Construction
@@ -201,14 +202,14 @@
 ; CHECK-NEXT:       Tail Duplication
 ; CHECK-NEXT:       Machine Copy Propagation Pass
 ; CHECK-NEXT:       Post-RA pseudo instruction expansion pass
-; CHECK-NEXT:       MachineDominator Tree Construction
-; CHECK-NEXT:       Machine Natural Loop Construction
+; CHECK-NEXT:       Machine Cycle Info Analysis
 ; CHECK-NEXT:       Machine Block Frequency Analysis
 ; CHECK-NEXT:       If Converter
 ; CHECK-NEXT:       MachineDominator Tree Construction
 ; CHECK-NEXT:       Machine Natural Loop Construction
 ; CHECK-NEXT:       PostRA Machine Instruction Scheduler
 ; CHECK-NEXT:       Analyze Machine Code For Garbage Collection
+; CHECK-NEXT:       Machine Cycle Info Analysis
 ; CHECK-NEXT:       Machine Block Frequency Analysis
 ; CHECK-NEXT:       MachinePostDominator Tree Construction
 ; CHECK-NEXT:       Branch Probability Basic Block Placement

llvm/test/CodeGen/RISCV/GlobalISel/gisel-commandline-option.ll

@@ -26,7 +26,6 @@
 ; ENABLED-NEXT:  RegBankSelect
 ; ENABLED-NEXT:  Analysis for ComputingKnownBits
 ; ENABLED-O1-NEXT:  Lazy Branch Probability Analysis
-; ENABLED-O1-NEXT:  Natural Loop Information
 ; ENABLED-O1-NEXT:  Lazy Block Frequency Analysis
 ; ENABLED-NEXT:  InstructionSelect
 ; ENABLED-NEXT:  ResetMachineFunction

llvm/test/CodeGen/RISCV/O3-pipeline.ll

@@ -60,7 +60,6 @@
 ; CHECK-NEXT:       Cycle Info Analysis
 ; CHECK-NEXT:       Post-Dominator Tree Construction
 ; CHECK-NEXT:       Branch Probability Analysis
-; CHECK-NEXT:       Natural Loop Information
 ; CHECK-NEXT:       Block Frequency Analysis
 ; CHECK-NEXT:       Constant Hoisting
 ; CHECK-NEXT:       Replace intrinsics with calls to vector library
@@ -106,12 +105,12 @@
 ; CHECK-NEXT:       Branch Probability Analysis
 ; CHECK-NEXT:       Assignment Tracking Analysis
 ; CHECK-NEXT:       Lazy Branch Probability Analysis
-; CHECK-NEXT:       Natural Loop Information
 ; CHECK-NEXT:       Lazy Block Frequency Analysis
 ; CHECK-NEXT:       RISC-V DAG->DAG Pattern Instruction Selection
 ; CHECK-NEXT:       Finalize ISel and expand pseudo-instructions
 ; CHECK-NEXT:       MachineDominator Tree Construction
-; CHECK-NEXT:	    Machine Natural Loop Construction
+; CHECK-NEXT:       Machine Natural Loop Construction
+; CHECK-NEXT:       Machine Cycle Info Analysis
 ; CHECK-NEXT:       Machine Block Frequency Analysis
 ; CHECK-NEXT:       Early Machine Loop Invariant Code Motion
 ; CHECK-NEXT:       MachineDominator Tree Construction
@@ -131,13 +130,14 @@
 ; CHECK-NEXT:       Machine Trace Metrics
 ; CHECK-NEXT:       Lazy Machine Block Frequency Analysis
 ; CHECK-NEXT:       Machine InstCombiner
+; CHECK-NEXT:       Machine Cycle Info Analysis
 ; CHECK-NEXT:       Machine Block Frequency Analysis
 ; CHECK-NEXT:       Early Machine Loop Invariant Code Motion
 ; CHECK-NEXT:       MachineDominator Tree Construction
+; CHECK-NEXT:       Machine Cycle Info Analysis
 ; CHECK-NEXT:       Machine Block Frequency Analysis
 ; CHECK-NEXT:       Machine Common Subexpression Elimination
 ; CHECK-NEXT:       MachinePostDominator Tree Construction
-; CHECK-NEXT:       Machine Cycle Info Analysis
 ; CHECK-NEXT:       Machine code sinking
 ; CHECK-NEXT:       Peephole Optimizations
 ; CHECK-NEXT:       Remove dead machine instructions
@@ -186,10 +186,11 @@
 ; CHECK-NEXT:       Remove Redundant DEBUG_VALUE analysis
 ; CHECK-NEXT:       Fixup Statepoint Caller Saved
 ; CHECK-NEXT:       PostRA Machine Sink
-; CHECK-NEXT:       MachineDominator Tree Construction
-; CHECK-NEXT:       Machine Natural Loop Construction
+; CHECK-NEXT:       Machine Cycle Info Analysis
 ; CHECK-NEXT:       Machine Block Frequency Analysis
+; CHECK-NEXT:       MachineDominator Tree Construction
 ; CHECK-NEXT:       MachinePostDominator Tree Construction
+; CHECK-NEXT:       Machine Natural Loop Construction
 ; CHECK-NEXT:       Lazy Machine Block Frequency Analysis
 ; CHECK-NEXT:       Machine Optimization Remark Emitter
 ; CHECK-NEXT:       Shrink Wrapping analysis
@@ -207,6 +208,7 @@
 ; CHECK-NEXT:       Machine Natural Loop Construction
 ; CHECK-NEXT:       PostRA Machine Instruction Scheduler
 ; CHECK-NEXT:       Analyze Machine Code For Garbage Collection
+; CHECK-NEXT:       Machine Cycle Info Analysis
 ; CHECK-NEXT:       Machine Block Frequency Analysis
 ; CHECK-NEXT:       MachinePostDominator Tree Construction
 ; CHECK-NEXT:       Branch Probability Basic Block Placement

llvm/test/CodeGen/SPIRV/llc-pipeline.ll

@@ -66,7 +66,6 @@
 ; SPIRV-O0-NEXT:      Dominator Tree Construction
 ; SPIRV-O0-NEXT:      Cycle Info Analysis
 ; SPIRV-O0-NEXT:      Lazy Branch Probability Analysis
-; SPIRV-O0-NEXT:      Natural Loop Information
 ; SPIRV-O0-NEXT:      Lazy Block Frequency Analysis
 ; SPIRV-O0-NEXT:      InstructionSelect
 ; SPIRV-O0-NEXT:      ResetMachineFunction
@@ -129,7 +128,6 @@
 ; SPIRV-Opt-NEXT:      Cycle Info Analysis
 ; SPIRV-Opt-NEXT:      Post-Dominator Tree Construction
 ; SPIRV-Opt-NEXT:      Branch Probability Analysis
-; SPIRV-Opt-NEXT:      Natural Loop Information
 ; SPIRV-Opt-NEXT:      Block Frequency Analysis
 ; SPIRV-Opt-NEXT:      Constant Hoisting
 ; SPIRV-Opt-NEXT:      Replace intrinsics with calls to vector library
@@ -187,7 +185,6 @@
 ; SPIRV-Opt-NEXT:      SPIRV post legalizer
 ; SPIRV-Opt-NEXT:      Analysis for ComputingKnownBits
 ; SPIRV-Opt-NEXT:      Lazy Branch Probability Analysis
-; SPIRV-Opt-NEXT:      Natural Loop Information
 ; SPIRV-Opt-NEXT:      Lazy Block Frequency Analysis
 ; SPIRV-Opt-NEXT:      InstructionSelect
 ; SPIRV-Opt-NEXT:      ResetMachineFunction
@@ -201,13 +198,14 @@
 ; SPIRV-Opt-NEXT:      Remove dead machine instructions
 ; SPIRV-Opt-NEXT:      MachineDominator Tree Construction
 ; SPIRV-Opt-NEXT:      Machine Natural Loop Construction
+; SPIRV-Opt-NEXT:      Machine Cycle Info Analysis
 ; SPIRV-Opt-NEXT:      Machine Block Frequency Analysis
 ; SPIRV-Opt-NEXT:      Early Machine Loop Invariant Code Motion
 ; SPIRV-Opt-NEXT:      MachineDominator Tree Construction
+; SPIRV-Opt-NEXT:      Machine Cycle Info Analysis
 ; SPIRV-Opt-NEXT:      Machine Block Frequency Analysis
 ; SPIRV-Opt-NEXT:      Machine Common Subexpression Elimination
 ; SPIRV-Opt-NEXT:      MachinePostDominator Tree Construction
-; SPIRV-Opt-NEXT:      Machine Cycle Info Analysis
 ; SPIRV-Opt-NEXT:      Machine Register Class Info Analysis
 ; SPIRV-Opt-NEXT:      Machine code sinking
 ; SPIRV-Opt-NEXT:      Peephole Optimizations

llvm/test/CodeGen/WebAssembly/GlobalISel/gisel-commandline-option.ll

@@ -28,7 +28,6 @@
 ; ENABLED-O1-NEXT:  Dominator Tree Construction
 ; ENABLED-O1-NEXT:  Cycle Info Analysis
 ; ENABLED-O1-NEXT:  Lazy Branch Probability Analysis
-; ENABLED-O1-NEXT:  Natural Loop Information
 ; ENABLED-O1-NEXT:  Lazy Block Frequency Analysis
 ; ENABLED-NEXT:  InstructionSelect
 ; NOFALLBACK-NEXT:  WebAssembly Argument Move

llvm/test/CodeGen/X86/opt-pipeline.ll

@@ -54,7 +54,6 @@
 ; CHECK-NEXT:       Cycle Info Analysis
 ; CHECK-NEXT:       Post-Dominator Tree Construction
 ; CHECK-NEXT:       Branch Probability Analysis
-; CHECK-NEXT:       Natural Loop Information
 ; CHECK-NEXT:       Block Frequency Analysis
 ; CHECK-NEXT:       Constant Hoisting
 ; CHECK-NEXT:       Replace intrinsics with calls to vector library
@@ -87,7 +86,6 @@
 ; CHECK-NEXT:       Branch Probability Analysis
 ; CHECK-NEXT:       Assignment Tracking Analysis
 ; CHECK-NEXT:       Lazy Branch Probability Analysis
-; CHECK-NEXT:       Natural Loop Information
 ; CHECK-NEXT:       Lazy Block Frequency Analysis
 ; CHECK-NEXT:       X86 DAG->DAG Instruction Selection
 ; CHECK-NEXT:       MachineDominator Tree Construction
@@ -113,13 +111,14 @@
 ; CHECK-NEXT:       X86 cmov Conversion
 ; CHECK-NEXT:       MachineDominator Tree Construction
 ; CHECK-NEXT:       Machine Natural Loop Construction
+; CHECK-NEXT:       Machine Cycle Info Analysis
 ; CHECK-NEXT:       Machine Block Frequency Analysis
 ; CHECK-NEXT:       Early Machine Loop Invariant Code Motion
 ; CHECK-NEXT:       MachineDominator Tree Construction
+; CHECK-NEXT:       Machine Cycle Info Analysis
 ; CHECK-NEXT:       Machine Block Frequency Analysis
 ; CHECK-NEXT:       Machine Common Subexpression Elimination
 ; CHECK-NEXT:       MachinePostDominator Tree Construction
-; CHECK-NEXT:       Machine Cycle Info Analysis
 ; CHECK-NEXT:       Machine code sinking
 ; CHECK-NEXT:       Peephole Optimizations
 ; CHECK-NEXT:       Remove dead machine instructions
@@ -147,6 +146,7 @@
 ; CHECK-NEXT:       Live Interval Analysis
 ; CHECK-NEXT:       Register Coalescer
 ; CHECK-NEXT:       Rename Disconnected Subregister Components
+; CHECK-NEXT:       Machine Cycle Info Analysis
 ; CHECK-NEXT:       Machine Block Frequency Analysis
 ; CHECK-NEXT:       Machine Instruction Scheduler
 ; CHECK-NEXT:       Debug Variable Analysis
@@ -174,6 +174,7 @@
 ; CHECK-NEXT:       Remove Redundant DEBUG_VALUE analysis
 ; CHECK-NEXT:       Fixup Statepoint Caller Saved
 ; CHECK-NEXT:       PostRA Machine Sink
+; CHECK-NEXT:       Machine Cycle Info Analysis
 ; CHECK-NEXT:       Machine Block Frequency Analysis
 ; CHECK-NEXT:       MachinePostDominator Tree Construction
 ; CHECK-NEXT:       Lazy Machine Block Frequency Analysis
@@ -192,6 +193,7 @@
 ; CHECK-NEXT:       Machine Natural Loop Construction
 ; CHECK-NEXT:       Post RA top-down list latency scheduler
 ; CHECK-NEXT:       Analyze Machine Code For Garbage Collection
+; CHECK-NEXT:       Machine Cycle Info Analysis
 ; CHECK-NEXT:       Machine Block Frequency Analysis
 ; CHECK-NEXT:       MachinePostDominator Tree Construction
 ; CHECK-NEXT:       Branch Probability Basic Block Placement

llvm/test/Other/new-pm-thinlto-postlink-pgo-defaults.ll

@@ -44,7 +44,6 @@
 ; CHECK-O-NEXT: Running analysis: BranchProbabilityAnalysis on foo
 ; CHECK-O-NEXT: Running analysis: CycleAnalysis on foo
 ; CHECK-O-NEXT: Running analysis: PostDominatorTreeAnalysis on foo
-; CHECK-O-NEXT: Running analysis: LoopAnalysis on foo
 ; CHECK-O-NEXT: Running pass: SimplifyCFGPass
 ; CHECK-O-NEXT: Running pass: AlwaysInlinerPass
 ; CHECK-O-NEXT: Running pass: ModuleInlinerWrapperPass
@@ -84,8 +83,10 @@
 ; CHECK-O-NEXT: Running pass: ReassociatePass
 ; CHECK-O-NEXT: Running analysis: UniformityInfoAnalysis
 ; CHECK-O23-NEXT: Running pass: ConstraintEliminationPass
+; CHECK-O23-NEXT: Running analysis: LoopAnalysis on foo
 ; CHECK-O23-NEXT: Running analysis: ScalarEvolutionAnalysis
 ; CHECK-O-NEXT: Running pass: LoopSimplifyPass
+; CHECK-O1-NEXT: Running analysis: LoopAnalysis on foo
 ; CHECK-O-NEXT: Running pass: LCSSAPass
 ; CHECK-O1-NEXT: Running analysis: ScalarEvolutionAnalysis
 ; CHECK-O-NEXT: Running analysis: InnerAnalysisManagerProxy

llvm/test/Other/new-pm-thinlto-postlink-samplepgo-defaults.ll

@@ -50,7 +50,6 @@
 ; CHECK-O-NEXT: Running analysis: BranchProbabilityAnalysis on foo
 ; CHECK-O-NEXT: Running analysis: CycleAnalysis on foo
 ; CHECK-O-NEXT: Running analysis: PostDominatorTreeAnalysis on foo
-; CHECK-O-NEXT: Running analysis: LoopAnalysis on foo
 ; CHECK-O-NEXT: Running pass: SimplifyCFGPass on foo
 
 ; CHECK-O-NEXT: Running pass: PGOForceFunctionAttrsPass
@@ -91,8 +90,10 @@
 ; CHECK-O-NEXT: Running pass: ReassociatePass
 ; CHECK-O-NEXT: Running analysis: UniformityInfoAnalysis
 ; CHECK-O23-NEXT: Running pass: ConstraintEliminationPass
+; CHECK-O23-NEXT: Running analysis: LoopAnalysis on foo
 ; CHECK-O23-NEXT: Running analysis: ScalarEvolutionAnalysis
 ; CHECK-O-NEXT: Running pass: LoopSimplifyPass
+; CHECK-O1-NEXT: Running analysis: LoopAnalysis on foo
 ; CHECK-O-NEXT: Running pass: LCSSAPass
 ; CHECK-O1-NEXT: Running analysis: ScalarEvolutionAnalysis
 ; CHECK-O-NEXT: Running analysis: InnerAnalysisManagerProxy

llvm/test/Other/new-pm-thinlto-prelink-pgo-defaults.ll

@@ -122,7 +122,6 @@
 ; CHECK-O-NEXT: Running analysis: BranchProbabilityAnalysis on foo
 ; CHECK-O-NEXT: Running analysis: CycleAnalysis on foo
 ; CHECK-O-NEXT: Running analysis: PostDominatorTreeAnalysis on foo
-; CHECK-O-NEXT: Running analysis: LoopAnalysis on foo
 ; CHECK-O23-NEXT: Running pass: AggressiveInstCombinePass
 ; CHECK-O-NEXT: Running pass: LibCallsShrinkWrapPass
 ; CHECK-O23-NEXT: Running pass: PGOMemOPSizeOpt
@@ -131,8 +130,10 @@
 ; CHECK-O-NEXT: Running pass: ReassociatePass
 ; CHECK-O-NEXT: Running analysis: UniformityInfoAnalysis
 ; CHECK-O23-NEXT: Running pass: ConstraintEliminationPass
+; CHECK-O23-NEXT: Running analysis: LoopAnalysis on foo
 ; CHECK-O23-NEXT: Running analysis: ScalarEvolutionAnalysis
 ; CHECK-O-NEXT: Running pass: LoopSimplifyPass
+; CHECK-O1-NEXT: Running analysis: LoopAnalysis on foo
 ; CHECK-O-NEXT: Running pass: LCSSAPass
 ; CHECK-O1-NEXT: Running analysis: ScalarEvolutionAnalysis
 ; CHECK-O-NEXT: Running analysis: InnerAnalysisManagerProxy

llvm/test/Other/new-pm-thinlto-prelink-samplepgo-defaults.ll

@@ -56,7 +56,6 @@
 ; CHECK-O-NEXT: Running analysis: BranchProbabilityAnalysis on foo
 ; CHECK-O-NEXT: Running analysis: CycleAnalysis on foo
 ; CHECK-O-NEXT: Running analysis: PostDominatorTreeAnalysis on foo
-; CHECK-O-NEXT: Running analysis: LoopAnalysis on foo
 ; CHECK-O-NEXT: Running pass: SimplifyCFGPass on foo
 ; CHECK-O-NEXT: Running pass: PGOForceFunctionAttrsPass
 ; CHECK-O-NEXT: Running pass: AlwaysInlinerPass
@@ -96,8 +95,10 @@
 ; CHECK-O-NEXT: Running pass: ReassociatePass
 ; CHECK-O-NEXT: Running analysis: UniformityInfoAnalysis
 ; CHECK-O23-NEXT: Running pass: ConstraintEliminationPass
+; CHECK-O23-NEXT: Running analysis: LoopAnalysis on foo
 ; CHECK-O23-NEXT: Running analysis: ScalarEvolutionAnalysis
 ; CHECK-O-NEXT: Running pass: LoopSimplifyPass
+; CHECK-O1-NEXT: Running analysis: LoopAnalysis on foo
 ; CHECK-O-NEXT: Running pass: LCSSAPass
 ; CHECK-O1-NEXT: Running analysis: ScalarEvolutionAnalysis
 ; CHECK-O-NEXT: Running analysis: InnerAnalysisManagerProxy

llvm/test/Transforms/GlobalOpt/dbg-intrinsic-loopanalysis.ll

@@ -2,7 +2,7 @@
 ; RUN: opt -strip-debug -S < %s | opt -passes="globalopt" -o /dev/null -debug-pass-manager 2>&1 | FileCheck %s
 
 ; Make sure that the call to dbg.declare does not prevent running BlockFrequency
-; and (especially) Loop Analysis.
+; and (especially) CycleAnalysis.
 ; Later passes (e.g. instcombine) may behave in different ways depending on if
 ; LoopInfo is available or not. Therefore, letting GlobalOpt run or not run
 ; LoopAnalysis depending on the presence of a dbg.declare may make the compiler
@@ -10,7 +10,7 @@
 
 ; CHECK: Running pass: GlobalOptPass on [module]
 ; CHECK: Running analysis: BlockFrequencyAnalysis on h
-; CHECK: Running analysis: LoopAnalysis on h
+; CHECK: Running analysis: CycleAnalysis on h
 
 define i16 @h(ptr %k) {
 entry:

llvm/test/Transforms/Inline/cgscc-incremental-invalidate.ll

@@ -11,20 +11,17 @@
 ; CHECK: Invalidating analysis: CycleAnalysis on test1_f
 ; CHECK: Invalidating analysis: DominatorTreeAnalysis on test1_f
 ; CHECK: Invalidating analysis: BranchProbabilityAnalysis on test1_f
-; CHECK: Invalidating analysis: LoopAnalysis on test1_f
 ; CHECK: Invalidating analysis: BlockFrequencyAnalysis on test1_f
 ; CHECK: Invalidating analysis: EphemeralValuesAnalysis on test1_f
 ; CHECK: Running analysis: DominatorTreeAnalysis on test1_g
 ; CHECK: Invalidating analysis: CycleAnalysis on test1_g
 ; CHECK: Invalidating analysis: DominatorTreeAnalysis on test1_g
 ; CHECK: Invalidating analysis: BranchProbabilityAnalysis on test1_g
-; CHECK: Invalidating analysis: LoopAnalysis on test1_g
 ; CHECK: Invalidating analysis: BlockFrequencyAnalysis on test1_g
 ; CHECK: Invalidating analysis: EphemeralValuesAnalysis on test1_g
 ; CHECK: Invalidating analysis: CycleAnalysis on test1_h
 ; CHECK: Invalidating analysis: DominatorTreeAnalysis on test1_h
 ; CHECK: Invalidating analysis: BranchProbabilityAnalysis on test1_h
-; CHECK: Invalidating analysis: LoopAnalysis on test1_h
 ; CHECK: Invalidating analysis: BlockFrequencyAnalysis on test1_h
 ; CHECK: Invalidating analysis: EphemeralValuesAnalysis on test1_h
 ; CHECK-NOT: Invalidating analysis:

llvm/unittests/Analysis/BlockFrequencyInfoTest.cpp

@@ -28,18 +28,14 @@ namespace {
 class BlockFrequencyInfoTest : public testing::Test {
 protected:
   std::unique_ptr<BranchProbabilityInfo> BPI;
-  std::unique_ptr<DominatorTree> DT;
   std::unique_ptr<CycleInfo> CI;
-  std::unique_ptr<LoopInfo> LI;
   LLVMContext C;
 
   BlockFrequencyInfo buildBFI(Function &F) {
-    DT.reset(new DominatorTree(F));
-    LI.reset(new LoopInfo(*DT));
     CI.reset(new CycleInfo());
     CI->compute(F);
     BPI.reset(new BranchProbabilityInfo(F, *CI));
-    return BlockFrequencyInfo(F, *BPI, *LI);
+    return BlockFrequencyInfo(F, *BPI, *CI);
   }
   std::unique_ptr<Module> makeLLVMModule() {
     const char *ModuleStrig = "define i32 @f(i32 %x) {\n"

llvm/unittests/Analysis/ProfileSummaryInfoTest.cpp

@@ -37,7 +37,6 @@ protected:
   LLVMContext C;
   std::unique_ptr<BranchProbabilityInfo> BPI;
   std::unique_ptr<DominatorTree> DT;
-  std::unique_ptr<LoopInfo> LI;
   std::unique_ptr<CycleInfo> CI;
 
   ProfileSummaryInfo buildPSI(Module *M) {
@@ -45,11 +44,10 @@ protected:
   }
   BlockFrequencyInfo buildBFI(Function &F) {
     DT.reset(new DominatorTree(F));
-    LI.reset(new LoopInfo(*DT));
     CI.reset(new CycleInfo());
     CI->compute(F);
     BPI.reset(new BranchProbabilityInfo(F, *CI));
-    return BlockFrequencyInfo(F, *BPI, *LI);
+    return BlockFrequencyInfo(F, *BPI, *CI);
   }
   std::unique_ptr<Module> makeLLVMModule(const char *ProfKind = nullptr,
                                          uint64_t NumCounts = 3,

llvm/unittests/Target/X86/MachineSizeOptsTest.cpp

@@ -14,8 +14,8 @@
 #include "llvm/CodeGen/MIRParser/MIRParser.h"
 #include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
 #include "llvm/CodeGen/MachineBranchProbabilityInfo.h"
+#include "llvm/CodeGen/MachineCycleAnalysis.h"
 #include "llvm/CodeGen/MachineDominators.h"
-#include "llvm/CodeGen/MachineLoopInfo.h"
 #include "llvm/CodeGen/MachineModuleInfo.h"
 #include "llvm/IR/Module.h"
 #include "llvm/MC/TargetRegistry.h"
@@ -47,14 +47,15 @@ class MachineSizeOptsTest : public testing::Test {
   std::unique_ptr<Module> M;
   struct BFIData {
     std::unique_ptr<MachineDominatorTree> MDT;
-    std::unique_ptr<MachineLoopInfo> MLI;
+    std::unique_ptr<MachineCycleInfo> MCI;
     std::unique_ptr<MachineBranchProbabilityInfo> MBPI;
     std::unique_ptr<MachineBlockFrequencyInfo> MBFI;
     BFIData(MachineFunction &MF) {
       MDT.reset(new MachineDominatorTree(MF));
-      MLI.reset(new MachineLoopInfo(*MDT));
+      MCI.reset(new MachineCycleInfo());
+      MCI->compute(MF);
       MBPI.reset(new MachineBranchProbabilityInfo());
-      MBFI.reset(new MachineBlockFrequencyInfo(MF, *MBPI, *MLI));
+      MBFI.reset(new MachineBlockFrequencyInfo(MF, *MBPI, *MCI));
     }
     MachineBlockFrequencyInfo *get() { return MBFI.get(); }
   };

llvm/unittests/Transforms/Utils/BasicBlockUtilsTest.cpp

@@ -651,11 +651,10 @@ bb4:
 )IR");
   Function *F = M->getFunction("crit_edge");
   DominatorTree DT(*F);
-  LoopInfo LI(DT);
   CycleInfo CI;
   CI.compute(*F);
   BranchProbabilityInfo BPI(*F, CI);
-  BlockFrequencyInfo BFI(*F, BPI, LI);
+  BlockFrequencyInfo BFI(*F, BPI, CI);
 
   ASSERT_TRUE(SplitIndirectBrCriticalEdges(*F, /*IgnoreBlocksWithoutPHI=*/true,
                                            &BPI, &BFI));
@@ -695,11 +694,10 @@ bb4:
 )IR");
   Function *F = M->getFunction("crit_edge");
   DominatorTree DT(*F);
-  LoopInfo LI(DT);
   CycleInfo CI;
   CI.compute(*F);
   BranchProbabilityInfo BPI(*F, CI);
-  BlockFrequencyInfo BFI(*F, BPI, LI);
+  BlockFrequencyInfo BFI(*F, BPI, CI);
 
   ASSERT_TRUE(SplitIndirectBrCriticalEdges(*F, /*IgnoreBlocksWithoutPHI=*/false,
                                            &BPI, &BFI));

llvm/unittests/Transforms/Utils/SizeOptsTest.cpp

@@ -33,17 +33,15 @@ protected:
   std::unique_ptr<Module> M;
   struct BFIData {
     std::unique_ptr<DominatorTree> DT;
-    std::unique_ptr<LoopInfo> LI;
     std::unique_ptr<CycleInfo> CI;
     std::unique_ptr<BranchProbabilityInfo> BPI;
     std::unique_ptr<BlockFrequencyInfo> BFI;
     BFIData(Function &F) {
       DT.reset(new DominatorTree(F));
-      LI.reset(new LoopInfo(*DT));
       CI.reset(new CycleInfo());
       CI->compute(F);
       BPI.reset(new BranchProbabilityInfo(F, *CI));
-      BFI.reset(new BlockFrequencyInfo(F, *BPI, *LI));
+      BFI.reset(new BlockFrequencyInfo(F, *BPI, *CI));
     }
     BlockFrequencyInfo *get() { return BFI.get(); }
   };