XCheriot was not considered in this function, so RV32E+XCheriot
defaulted
to ilp32e instead of cheriot when no -target-abi was given.
Since this function does not have unit test coverage, this adds new
tests
for the ABI inference functions: RISCVISAInfo::computeDefaultABI() and
RISCVABI::computeTargetABI.
This change was created with the help of AI tools
RVY is a new base ISA, so the syntax to enable it is rv32y/rv64y.
Since the compressed instructions reuse the space for Zcf (RV32) and
Zcd (RV64), those are marked as incompatible and the logic for C/Zce
is updated as part of this PR.
RVY can also extend RVE instead of RVY (as is done for CHERIoT), but the
official arch string syntax for that has not been finalized yet.
Related discussion on that includes the "long base name" proposal:
https://lists.riscv.org/g/tech-unprivileged/message/1134
Reviewers: topperc, lenary, jrtc27
Pull Request: https://github.com/llvm/llvm-project/pull/201931
Xqccmt is Qualcomm's vendor extension providing compressed (16-bit) jump
table instructions, equivalent to (and mutually exclusive with) the
standard Zcmt extension.
Two instructions are added:
- qc.cm.jt (index 0-31): jump via table, no link register written
- qc.cm.jalt (index 32-255): jump via table with link; bit 0 of the jump
table entry selects the link register at runtime: 0 = ra (x1), 1 = t0
(x5)
The encoding is identical to cm.jt/cm.jalt from Zcmt. Xqccmt and Zcmt
are mutually exclusive and cannot be combined. Xqccmt is also
incompatible with Zcd (overlapping encoding space).
Spec: https://github.com/riscv/riscv-unified-db/pull/1788
This pushes some of our simplifications to extension dependencies into
other parts of RISCVISAInfo and into the tablegen predicates.
The key affected pieces are:
- Error messages around Zcd incompatibilities now reference only `zcd`.
- We now have a big list of extensions that are rv32-only.
There are no instructions in the Xqci extension itself, it is just an
alias of a group. If we have all the items in the group, then we should
add `xqci` to the list of extensions we have.
This helps with multilib matching.
This change implements the conditional "Zca implies C" rule to match
GCC's behavior (PR119122) and the RISC-V specification for MISA.C.
The rule is:
- For RV32:
- No F and no D: Zca alone implies C
- F but no D: Zca + Zcf implies C
- F and D: Zca + Zcf + Zcd implies C
- For RV64:
- No D: Zca alone implies C
- D: Zca + Zcd implies C
This fixes multilib matching issues where LLVM-generated march strings
didn't include the C extension when GCC's multilib configurations
expected it.
Reference:
- GCC PR119122: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119122
- RISC-V Zc spec:
https://github.com/riscv/riscv-isa-manual/blob/main/src/zc.adoc
Signed-off-by: Jerry Zhang Jian <jerry.zhangjian@sifive.com>
XSfvfbfexp16e, XSfvfexp16e, and XSfvfexp32e are SiFive's vector
exponential instruction extensions of BFloat16, F16, and F32,
respectively. Spec:
https://www.sifive.com/document-file/exponential-function-instruction-xsfvfexp32e-xsfvf
XSfvfexpa and XSfvfexpa64e are SiFive's vector exponential approximation
instruction extensions where the former supports F16 and F32 and the
latter covers F64. These instructions approximate 2 raised to a
fractional power. Spec:
https://www.sifive.com/document-file/exponential-approximation-instruction-xsfvfexpa-ex
This patch adds their corresponding features and MC supports.
---------
Co-authored-by: Jesse Huang <jesse.huang@sifive.com>
Co-authored-by: Craig Topper <craig.topper@sifive.com>
This is needed to handle the scenario of an extension that implies
FeatureStdExtE, as is the case for the
downstream FeatureVendorXCheriot used for Cheriot support.
This extension adds two external input output instructions for
non-memory-mapped device.
The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.7.0
This patch adds assembler only support.
Co-authored-by: Sudharsan Veeravalli <quic_svs@quicinc.com>
Like cryptography extensions like `Zk`, `B` (a combination of `Zba`,
`Zbb` and `Zbs` extensions) can be useful if we handle this extension as
a combination.
If all `Zba`, `Zbb` and `Zbs` extensions are enabled, it also enables
the `B` extension.
With a minor fix for the build failures.
Original message:
This extension adds nine instructions, eight for non-memory-mapped devices synchronization and delay instruction.
The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.7.0
This patch adds assembler only support.
Co-authored-by: Sudharsan Veeravalli quic_svs@quicinc.com
This extension adds nine instructions, eight for non-memory-mapped
devices synchronization and delay instruction.
The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.7.0
This patch adds assembler only support.
Co-authored-by: Sudharsan Veeravalli <quic_svs@quicinc.com>
This extension adds 10 instructions that provide hints to the interface
simulation environment.
The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/
This patch adds assembler only support.
This extension adds twelve conditional branch instructions that use an
immediate operand for the source.
The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.7.0
This patch adds assembler only support.
Co-authored-by: Sudharsan Veeravalli <quic_svs@quicinc.com>
The Xqcili extension includes a two instructions that load large
immediates than is available with the base RISC-V ISA.
The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.7.0
This patch adds assembler only support.
I was reviewing encodings to put the disassembling of vendor
instructions after after standard instructions and found that these
overlap with c.fldsp and c.fsdsp.
This extension adds thirty eight bit manipulation instructions.
The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.6
This patch adds assembler only support.
Co-authored-by: Sudharsan Veeravalli <quic_svs@quicinc.com>
Xqccmp is a new spec by Qualcomm that makes a vendor-specific effort to
solve the push/pop + frame pointers issue. Broadly, it takes the Zcmp
instructions and reverse the order they push/pop registers in, which
ends up matching the frame pointer convention.
This extension adds a new instruction not present in Zcmp,
`qc.cm.pushfp`, which will set `fp` to the incoming `sp` value after it
has pushed the registers.
This change duplicates the Zcmp implementation, with minor changes to
mnemonics (for the `qc.` prefix), predicates, and the addition of
`qc.cm.pushfp`. There is also new logic to prevent combining Xqccmp and
Zcmp. Xqccmp is kept separate to Xqci for decoding/encoding etc, as the
specs are separate today.
Specification:
https://github.com/quic/riscv-unified-db/releases/tag/Xqccmp_extension-0.1.0
This extension adds eight 48 bit load store instructions.
The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/latest
This patch adds assembler only support.
---------
Co-authored-by: Harsh Chandel <hchandel@qti.qualcomm.com>
This extension adds eleven instructions to accelerate interrupt
servicing.
The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/latest
This patch adds assembler only support.
---------
Co-authored-by: Harsh Chandel <hchandel@qti.qualcomm.com>
The Qualcomm uC Xqcicm extension adds 13 conditional move instructions.
The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/latest
This patch adds assembler only support.
---------
Co-authored-by: Harsh Chandel <hchandel@qti.qualcomm.com>
This extension adds 3 instructions that perform load-store address
calculation.
The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/latest
This patch adds assembler only support.
---------
Co-authored-by: Harsh Chandel <hchandel@qti.qualcomm.com>
Co-authored-by: Sudharsan Veeravalli <quic_svs@quicinc.com>
The Qualcomm uC Xqcics extension adds 8 conditional select instructions.
The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/latest
This patch adds assembler only support.
---------
Co-authored-by: Harsh Chandel <hchandel@qti.qualcomm.com>
