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Fold constant 0 at instcombine.

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This commit is contained in:
Aaditya 2026-08-01 15:31:43 +05:30
parent 58c12ff41b
commit fc4b0be2b5
2 changed files with 10 additions and 25 deletions
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10
llvm/lib/Analysis/ConstantFolding.cpp
View file

@ -1816,6 +1816,9 @@ bool llvm::canConstantFoldCallTo(const CallBase *Call, const Function *F) {
case Intrinsic::amdgcn_wave_reduce_min:
case Intrinsic::amdgcn_wave_reduce_and:
case Intrinsic::amdgcn_wave_reduce_or:
case Intrinsic::amdgcn_wave_reduce_xor:
case Intrinsic::amdgcn_wave_reduce_add:
case Intrinsic::amdgcn_wave_reduce_sub:
case Intrinsic::amdgcn_s_wqm:
case Intrinsic::amdgcn_s_quadmask:
case Intrinsic::amdgcn_s_bitreplicate:
@ -3910,6 +3913,13 @@ static Constant *ConstantFoldIntrinsicCall2(Intrinsic::ID IntrinsicID, Type *Ty,
if (!C0 || !C1)
return Constant::getNullValue(Ty);
return ConstantInt::get(Ty, APIntOps::pext(*C0, *C1));
case Intrinsic::amdgcn_wave_reduce_add:
case Intrinsic::amdgcn_wave_reduce_sub:
case Intrinsic::amdgcn_wave_reduce_xor: {
if (C0 && C0->isZero())
return Constant::getNullValue(Ty);
return nullptr;
}
case Intrinsic::amdgcn_wave_reduce_umin:
case Intrinsic::amdgcn_wave_reduce_umax:
case Intrinsic::amdgcn_wave_reduce_max:

25
llvm/lib/Target/AMDGPU/SIISelLowering.cpp
View file

@ -5982,13 +5982,6 @@ static MachineBasicBlock *lowerWaveReduce(MachineInstr &MI,
MachineInstr *SrcDef = MRI.getVRegDef(SrcReg);
if (SrcDef && SrcDef->isMoveImmediate()) {
int64_t Imm = SrcDef->getOperand(1).getImm();
unsigned XorMovOp = Opc == AMDGPU::S_XOR_B32
? AMDGPU::S_MOV_B32
: AMDGPU::S_MOV_B64_IMM_PSEUDO;
if (Imm == 0) { // 0 * parity(exec) = 0
BuildMI(BB, MI, DL, TII->get(XorMovOp), DstReg).addImm(0);
break;
}
if (Imm == 1) { // 1 * parity(exec) = parity(exec)
if (Opc == AMDGPU::S_XOR_B32) {
BuildMI(BB, MI, DL, TII->get(AMDGPU::S_MOV_B32), DstReg)
@ -6025,15 +6018,6 @@ static MachineBasicBlock *lowerWaveReduce(MachineInstr &MI,
}
case AMDGPU::S_SUB_I32: {
Register NegatedVal = MRI.createVirtualRegister(DstRegClass);
// Check if Src is a known identity constant.
MachineInstr *SrcDef = MRI.getVRegDef(SrcReg);
if (SrcDef && SrcDef->isMoveImmediate()) {
int64_t Imm = SrcDef->getOperand(1).getImm();
if (Imm == 0) { // 0 * bitcount(exec) = 0
BuildMI(BB, MI, DL, TII->get(AMDGPU::S_MOV_B32), DstReg).addImm(0);
break;
}
}
// Take the negation of the source operand.
BuildMI(BB, MI, DL, TII->get(AMDGPU::S_SUB_I32), NegatedVal)
.addImm(0)
@ -6048,10 +6032,6 @@ static MachineBasicBlock *lowerWaveReduce(MachineInstr &MI,
MachineInstr *SrcDef = MRI.getVRegDef(SrcReg);
if (SrcDef && SrcDef->isMoveImmediate()) {
int64_t Imm = SrcDef->getOperand(1).getImm();
if (Imm == 0) { // 0 * bitcount(exec) = 0
BuildMI(BB, MI, DL, TII->get(AMDGPU::S_MOV_B32), DstReg).addImm(0);
break;
}
if (Imm == 1) { // 1 * bitcount(exec) = bitcount(exec)
BuildMI(BB, MI, DL, TII->get(AMDGPU::COPY), DstReg)
.addReg(NewAccumulator->getOperand(0).getReg());
@ -6084,11 +6064,6 @@ static MachineBasicBlock *lowerWaveReduce(MachineInstr &MI,
MachineInstr *SrcDef = MRI.getVRegDef(SrcReg);
if (SrcDef && SrcDef->isMoveImmediate()) {
int64_t Imm = SrcDef->getOperand(1).getImm();
if (Imm == 0) { // 0 * bitcount(exec) = 0
BuildMI(BB, MI, DL, TII->get(AMDGPU::S_MOV_B64_IMM_PSEUDO), DstReg)
.addImm(0);
break;
}
if (Imm == 1 && Opc == AMDGPU::S_ADD_U64_PSEUDO) {
// 1 * bitcount(exec) = bitcount(exec)
Register DstHi =