[LLVM][SelectionDAG] Reduce chances of a split VSETCC being rewidened. (#191438)

This is a reimplementation of
https://github.com/llvm/llvm-project/pull/139295 but without introducing
a potential infinite type legalisation loop whereby splitting a SETCC
requires the result to be rewidened.

Fixes https://github.com/llvm/llvm-project/issues/190773

llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp

@@ -4797,8 +4797,7 @@ SDValue DAGTypeLegalizer::SplitVecOp_VSETCC(SDNode *N) {
   GetSplitVector(N->getOperand(isStrict ? 2 : 1), Lo1, Hi1);
 
   EVT VT = N->getValueType(0);
-  EVT PartResVT = Lo0.getValueType().changeElementType(*DAG.getContext(),
-                                                       VT.getScalarType());
+  EVT PartResVT = getSetCCResultType(Lo0.getValueType());
 
   if (Opc == ISD::SETCC) {
     LoRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Lo0, Lo1, N->getOperand(2));
@@ -4823,7 +4822,15 @@ SDValue DAGTypeLegalizer::SplitVecOp_VSETCC(SDNode *N) {
                         N->getOperand(2), MaskHi, EVLHi);
   }
 
-  return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoRes, HiRes);
+  EVT ConcatVT = PartResVT.getDoubleNumVectorElementsVT(*DAG.getContext());
+  SDValue Con = DAG.getNode(ISD::CONCAT_VECTORS, DL, ConcatVT, LoRes, HiRes);
+  if (VT == ConcatVT)
+    return Con;
+
+  EVT OpVT = N->getOperand(0).getValueType();
+  ISD::NodeType ExtendCode =
+      TargetLowering::getExtendForContent(TLI.getBooleanContents(OpVT));
+  return DAG.getExtOrTrunc(Con, DL, VT, ExtendCode);
 }
 
 

llvm/lib/Target/ARM/ARMISelLowering.cpp

@@ -1502,18 +1502,16 @@ ARMTargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,
   return std::make_pair(RRC, Cost);
 }
 
-EVT ARMTargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &,
+EVT ARMTargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &C,
                                           EVT VT) const {
   if (!VT.isVector())
     return getPointerTy(DL);
 
   // MVE has a predicate register.
-  if ((Subtarget->hasMVEIntegerOps() &&
-       (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
-        VT == MVT::v16i8)) ||
-      (Subtarget->hasMVEFloatOps() &&
-       (VT == MVT::v2f64 || VT == MVT::v4f32 || VT == MVT::v8f16)))
-    return MVT::getVectorVT(MVT::i1, VT.getVectorElementCount());
+  if ((Subtarget->hasMVEIntegerOps() && VT.isInteger()) ||
+      (Subtarget->hasMVEFloatOps() && VT.isFloatingPoint()))
+    return VT.changeElementType(C, MVT::i1);
+
   return VT.changeVectorElementTypeToInteger();
 }
 

llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp

@@ -1072,8 +1072,12 @@ bool WebAssemblyTargetLowering::isOffsetFoldingLegal(
 EVT WebAssemblyTargetLowering::getSetCCResultType(const DataLayout &DL,
                                                   LLVMContext &C,
                                                   EVT VT) const {
-  if (VT.isVector())
+  if (VT.isVector()) {
+    if (VT.getVectorElementType() == MVT::f16 && !Subtarget->hasFP16())
+      return VT.changeElementType(C, MVT::i1);
+
     return VT.changeVectorElementTypeToInteger();
+  }
 
   // So far, all branch instructions in Wasm take an I32 condition.
   // The default TargetLowering::getSetCCResultType returns the pointer size,

llvm/test/CodeGen/WebAssembly/simd-pr190773.ll

@@ -0,0 +1,47 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc < %s -mtriple=wasm32 -mattr=+simd128 | FileCheck %s
+
+define <4 x i1>  @f(ptr %out, <4 x half> %v) {
+; CHECK-LABEL: f:
+; CHECK:         .functype f (i32, i32, i32, i32, i32) -> (v128)
+; CHECK-NEXT:    .local f32, f32, f32
+; CHECK-NEXT:  # %bb.0:
+; CHECK-NEXT:    local.get 4
+; CHECK-NEXT:    call __extendhfsf2
+; CHECK-NEXT:    local.set 5
+; CHECK-NEXT:    local.get 3
+; CHECK-NEXT:    call __extendhfsf2
+; CHECK-NEXT:    local.set 6
+; CHECK-NEXT:    local.get 2
+; CHECK-NEXT:    call __extendhfsf2
+; CHECK-NEXT:    local.set 7
+; CHECK-NEXT:    local.get 1
+; CHECK-NEXT:    call __extendhfsf2
+; CHECK-NEXT:    f32.const 0x0p0
+; CHECK-NEXT:    f32.ne
+; CHECK-NEXT:    i32x4.splat
+; CHECK-NEXT:    local.get 7
+; CHECK-NEXT:    f32.const 0x0p0
+; CHECK-NEXT:    f32.ne
+; CHECK-NEXT:    i32x4.replace_lane 2
+; CHECK-NEXT:    i32.const 63
+; CHECK-NEXT:    i64x2.shl
+; CHECK-NEXT:    i32.const 63
+; CHECK-NEXT:    i64x2.shr_s
+; CHECK-NEXT:    local.get 6
+; CHECK-NEXT:    f32.const 0x0p0
+; CHECK-NEXT:    f32.ne
+; CHECK-NEXT:    i32x4.splat
+; CHECK-NEXT:    local.get 5
+; CHECK-NEXT:    f32.const 0x0p0
+; CHECK-NEXT:    f32.ne
+; CHECK-NEXT:    i32x4.replace_lane 2
+; CHECK-NEXT:    i32.const 63
+; CHECK-NEXT:    i64x2.shl
+; CHECK-NEXT:    i32.const 63
+; CHECK-NEXT:    i64x2.shr_s
+; CHECK-NEXT:    i8x16.shuffle 0, 1, 2, 3, 8, 9, 10, 11, 16, 17, 18, 19, 24, 25, 26, 27
+; CHECK-NEXT:    # fallthrough-return
+  %cmp = fcmp une <4 x half> %v, zeroinitializer
+  ret <4 x i1> %cmp
+}