[VPlan] Simplify reverse(reverse(x)) -> x (#199057)
This is a version of #196900 that performs the simplification as a separate transform. We need to add an additional `vp.splice.right(vp.splice.left(poison, x, evl), poison, evl) -> x` simplification to avoid left over splices whenever reverses are removed in an EVL tail folded loop. Co-authored-by: Madhur Amilkanthwar <madhura@nvidia.com>
This commit is contained in:
Luke Lau
GitHub
parent
0a04c148c1
commit
ccef34d45a
6 changed files with 96 additions and 23 deletions
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@ -1853,6 +1853,15 @@ void VPlanTransforms::simplifyRecipes(VPlan &Plan) {
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}
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}
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void VPlanTransforms::simplifyReverses(VPlan &Plan) {
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VPValue *X;
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for (VPBasicBlock *VPBB : VPBlockUtils::blocksOnly<VPBasicBlock>(
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vp_depth_first_deep(Plan.getEntry())))
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for (VPRecipeBase &R : make_early_inc_range(*VPBB))
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if (match(&R, m_Reverse(m_Reverse(m_VPValue(X)))))
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R.getVPSingleValue()->replaceAllUsesWith(X);
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}
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/// Reassociate (headermask && x) && y -> headermask && (x && y) to allow the
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/// header mask to be simplified further when tail folding, e.g. in
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/// optimizeEVLMasks.
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@ -2822,6 +2831,7 @@ void VPlanTransforms::optimize(VPlan &Plan) {
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RUN_VPLAN_PASS(reassociateHeaderMask, Plan);
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RUN_VPLAN_PASS(simplifyRecipes, Plan);
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RUN_VPLAN_PASS(removeBranchOnConst, Plan, /*OnlyLatches=*/false);
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RUN_VPLAN_PASS(simplifyReverses, Plan);
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RUN_VPLAN_PASS(removeDeadRecipes, Plan);
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RUN_VPLAN_PASS(createAndOptimizeReplicateRegions, Plan);
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@ -3155,11 +3165,22 @@ void VPlanTransforms::optimizeEVLMasks(VPlan &Plan) {
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}
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}
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// Fold the following splice patterns into vp.reverse for reverse accesses:
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// Fold the following splice patterns:
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// splice.right(splice.left(poison, x, evl), poison, evl) -> x
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// vector.reverse(splice.left(poison, x, evl)) -> vp.reverse(x, true, evl)
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// splice.right(vector.reverse(x), poison, evl) -> vp.reverse(x, true, evl)
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for (VPUser *U : collectUsersRecursively(EVL)) {
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auto *R = cast<VPRecipeBase>(U);
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VPValue *X;
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if (match(U, m_Intrinsic<Intrinsic::vector_splice_right>(
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m_Intrinsic<Intrinsic::vector_splice_left>(
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m_Poison(), m_VPValue(X), m_Specific(EVL)),
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m_Poison(), m_Specific(EVL)))) {
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R->getVPSingleValue()->replaceAllUsesWith(X);
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OldRecipes.push_back(R);
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continue;
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}
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if (!match(U,
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m_CombineOr(
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m_Reverse(m_Intrinsic<Intrinsic::vector_splice_left>(
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@ -3168,13 +3189,12 @@ void VPlanTransforms::optimizeEVLMasks(VPlan &Plan) {
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m_Reverse(m_VPValue(X)), m_Poison(), m_Specific(EVL)))))
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continue;
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auto *Def = cast<VPSingleDefRecipe>(U);
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auto *VPReverse = new VPWidenIntrinsicRecipe(
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Intrinsic::experimental_vp_reverse, {X, Plan.getTrue(), EVL},
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X->getScalarType(), {}, {}, Def->getDebugLoc());
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VPReverse->insertBefore(Def);
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Def->replaceAllUsesWith(VPReverse);
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OldRecipes.push_back(Def);
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X->getScalarType(), {}, {}, R->getDebugLoc());
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VPReverse->insertBefore(R);
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R->getVPSingleValue()->replaceAllUsesWith(VPReverse);
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OldRecipes.push_back(R);
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}
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for (VPRecipeBase *R : reverse(OldRecipes)) {
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@ -388,6 +388,9 @@ struct VPlanTransforms {
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/// Perform instcombine-like simplifications on recipes in \p Plan.
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static void simplifyRecipes(VPlan &Plan);
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/// Cancel out redundant reverses in \p Plan, e.g. reverse(reverse(x)) -> x.
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static void simplifyReverses(VPlan &Plan);
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/// Remove BranchOnCond recipes with true or false conditions together with
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/// removing dead edges to their successors. If \p OnlyLatches is true, only
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/// process loop latches. Returns true if incoming values from any phi-like
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@ -25,11 +25,9 @@ define void @reverse_load_store(i64 %startval, ptr noalias %ptr, ptr noalias %pt
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; IF-EVL-NEXT: [[TMP6:%.*]] = sub i64 0, [[TMP4]]
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; IF-EVL-NEXT: [[TMP12:%.*]] = getelementptr i32, ptr [[TMP8]], i64 [[TMP6]]
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; IF-EVL-NEXT: [[VP_OP_LOAD:%.*]] = call <vscale x 4 x i32> @llvm.vp.load.nxv4i32.p0(ptr align 4 [[TMP12]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP5]])
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; IF-EVL-NEXT: [[VP_REVERSE:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vp.reverse.nxv4i32(<vscale x 4 x i32> [[VP_OP_LOAD]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP5]])
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; IF-EVL-NEXT: [[TMP13:%.*]] = getelementptr inbounds i32, ptr [[PTR2:%.*]], i64 [[TMP7]]
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; IF-EVL-NEXT: [[TMP17:%.*]] = getelementptr i32, ptr [[TMP13]], i64 [[TMP6]]
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; IF-EVL-NEXT: [[VP_REVERSE3:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vp.reverse.nxv4i32(<vscale x 4 x i32> [[VP_REVERSE]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP5]])
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; IF-EVL-NEXT: call void @llvm.vp.store.nxv4i32.p0(<vscale x 4 x i32> [[VP_REVERSE3]], ptr align 4 [[TMP17]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP5]])
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; IF-EVL-NEXT: call void @llvm.vp.store.nxv4i32.p0(<vscale x 4 x i32> [[VP_OP_LOAD]], ptr align 4 [[TMP17]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP5]])
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; IF-EVL-NEXT: [[INDEX_EVL_NEXT]] = add nuw i64 [[TMP20]], [[EVL_BASED_IV]]
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; IF-EVL-NEXT: [[AVL_NEXT]] = sub nuw i64 [[AVL]], [[TMP20]]
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; IF-EVL-NEXT: [[TMP24:%.*]] = icmp eq i64 [[AVL_NEXT]], 0
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@ -63,11 +61,9 @@ define void @reverse_load_store(i64 %startval, ptr noalias %ptr, ptr noalias %pt
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; NO-VP-NEXT: [[TMP12:%.*]] = sub i64 0, [[TMP9]]
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; NO-VP-NEXT: [[TMP14:%.*]] = getelementptr inbounds i32, ptr [[TMP13]], i64 [[TMP12]]
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; NO-VP-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 4 x i32>, ptr [[TMP14]], align 4
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; NO-VP-NEXT: [[REVERSE:%.*]] = call <vscale x 4 x i32> @llvm.vector.reverse.nxv4i32(<vscale x 4 x i32> [[WIDE_LOAD]])
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; NO-VP-NEXT: [[TMP15:%.*]] = getelementptr inbounds i32, ptr [[PTR2:%.*]], i64 [[TMP8]]
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; NO-VP-NEXT: [[TMP20:%.*]] = getelementptr inbounds i32, ptr [[TMP15]], i64 [[TMP12]]
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; NO-VP-NEXT: [[REVERSE1:%.*]] = call <vscale x 4 x i32> @llvm.vector.reverse.nxv4i32(<vscale x 4 x i32> [[REVERSE]])
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; NO-VP-NEXT: store <vscale x 4 x i32> [[REVERSE1]], ptr [[TMP20]], align 4
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; NO-VP-NEXT: store <vscale x 4 x i32> [[WIDE_LOAD]], ptr [[TMP20]], align 4
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; NO-VP-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP3]]
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; NO-VP-NEXT: [[TMP21:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
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; NO-VP-NEXT: br i1 [[TMP21]], label [[MIDDLE_BLOCK:%.*]], label [[FOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
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@ -134,11 +130,9 @@ define void @reverse_load_store_masked(i64 %startval, ptr noalias %ptr, ptr noal
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; IF-EVL-NEXT: [[TMP7:%.*]] = sub i64 0, [[TMP15]]
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; IF-EVL-NEXT: [[TMP20:%.*]] = getelementptr i32, ptr [[TMP16]], i64 [[TMP7]]
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; IF-EVL-NEXT: [[VP_OP_LOAD4:%.*]] = call <vscale x 4 x i32> @llvm.vp.load.nxv4i32.p0(ptr align 4 [[TMP20]], <vscale x 4 x i1> [[VP_REVERSE_MASK]], i32 [[TMP5]])
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; IF-EVL-NEXT: [[VP_REVERSE:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vp.reverse.nxv4i32(<vscale x 4 x i32> [[VP_OP_LOAD4]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP5]])
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; IF-EVL-NEXT: [[TMP21:%.*]] = getelementptr i32, ptr [[PTR2:%.*]], i64 [[TMP11]]
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; IF-EVL-NEXT: [[TMP25:%.*]] = getelementptr i32, ptr [[TMP21]], i64 [[TMP7]]
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; IF-EVL-NEXT: [[TMP13:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vp.reverse.nxv4i32(<vscale x 4 x i32> [[VP_REVERSE]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP5]])
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; IF-EVL-NEXT: call void @llvm.vp.store.nxv4i32.p0(<vscale x 4 x i32> [[TMP13]], ptr align 4 [[TMP25]], <vscale x 4 x i1> [[VP_REVERSE_MASK]], i32 [[TMP5]])
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; IF-EVL-NEXT: call void @llvm.vp.store.nxv4i32.p0(<vscale x 4 x i32> [[VP_OP_LOAD4]], ptr align 4 [[TMP25]], <vscale x 4 x i1> [[VP_REVERSE_MASK]], i32 [[TMP5]])
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; IF-EVL-NEXT: [[INDEX_EVL_NEXT]] = add nuw i64 [[TMP26]], [[EVL_BASED_IV]]
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; IF-EVL-NEXT: [[AVL_NEXT]] = sub nuw i64 [[AVL]], [[TMP26]]
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; IF-EVL-NEXT: [[TMP29:%.*]] = icmp eq i64 [[AVL_NEXT]], 0
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@ -177,11 +171,9 @@ define void @reverse_load_store_masked(i64 %startval, ptr noalias %ptr, ptr noal
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; NO-VP-NEXT: [[TMP16:%.*]] = getelementptr i32, ptr [[TMP15]], i64 [[TMP14]]
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; NO-VP-NEXT: [[REVERSE:%.*]] = call <vscale x 4 x i1> @llvm.vector.reverse.nxv4i1(<vscale x 4 x i1> [[TMP10]])
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; NO-VP-NEXT: [[WIDE_MASKED_LOAD:%.*]] = call <vscale x 4 x i32> @llvm.masked.load.nxv4i32.p0(ptr align 4 [[TMP16]], <vscale x 4 x i1> [[REVERSE]], <vscale x 4 x i32> poison)
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; NO-VP-NEXT: [[REVERSE2:%.*]] = call <vscale x 4 x i32> @llvm.vector.reverse.nxv4i32(<vscale x 4 x i32> [[WIDE_MASKED_LOAD]])
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; NO-VP-NEXT: [[TMP17:%.*]] = getelementptr i32, ptr [[PTR2:%.*]], i64 [[TMP8]]
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; NO-VP-NEXT: [[TMP22:%.*]] = getelementptr i32, ptr [[TMP17]], i64 [[TMP14]]
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; NO-VP-NEXT: [[REVERSE4:%.*]] = call <vscale x 4 x i32> @llvm.vector.reverse.nxv4i32(<vscale x 4 x i32> [[REVERSE2]])
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; NO-VP-NEXT: call void @llvm.masked.store.nxv4i32.p0(<vscale x 4 x i32> [[REVERSE4]], ptr align 4 [[TMP22]], <vscale x 4 x i1> [[REVERSE]])
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; NO-VP-NEXT: call void @llvm.masked.store.nxv4i32.p0(<vscale x 4 x i32> [[WIDE_MASKED_LOAD]], ptr align 4 [[TMP22]], <vscale x 4 x i1> [[REVERSE]])
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; NO-VP-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP3]]
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; NO-VP-NEXT: [[TMP23:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
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; NO-VP-NEXT: br i1 [[TMP23]], label [[MIDDLE_BLOCK:%.*]], label [[FOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
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@ -0,0 +1,59 @@
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; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py UTC_ARGS: --filter-out-after "middle.block:" --version 6
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; RUN: opt -p loop-vectorize -force-vector-width=4 -disable-output -vplan-print-after=simplifyReverses %s 2>&1 | FileCheck %s
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define void @reverse_copy(ptr noalias %src, ptr noalias %dst, i32 %n) {
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; CHECK-LABEL: VPlan for loop in 'reverse_copy'
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; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' {
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; CHECK-NEXT: Live-in vp<[[VP0:%[0-9]+]]> = VF
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; CHECK-NEXT: Live-in vp<[[VP1:%[0-9]+]]> = VF * UF
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; CHECK-NEXT: Live-in vp<[[VP2:%[0-9]+]]> = vector-trip-count
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; CHECK-NEXT: vp<[[VP3:%[0-9]+]]> = original trip-count
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; CHECK-EMPTY:
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; CHECK-NEXT: ir-bb<entry>:
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; CHECK-NEXT: EMIT vp<[[VP3]]> = EXPAND SCEV ((-1 * (0 smin (-1 + %n)<nsw>)) + %n)
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; CHECK-NEXT: Successor(s): scalar.ph, vector.ph
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; CHECK-EMPTY:
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; CHECK-NEXT: vector.ph:
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; CHECK-NEXT: vp<[[VP4:%[0-9]+]]> = DERIVED-IV ir<%n> + vp<[[VP2]]> * ir<-1>
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; CHECK-NEXT: Successor(s): vector loop
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; CHECK-EMPTY:
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; CHECK-NEXT: <x1> vector loop: {
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; CHECK-NEXT: vp<[[VP5:%[0-9]+]]> = CANONICAL-IV
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; CHECK-EMPTY:
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; CHECK-NEXT: vector.body:
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; CHECK-NEXT: ir<%iv> = WIDEN-INDUCTION nsw ir<%n>, ir<-1>, vp<[[VP0]]>
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; CHECK-NEXT: vp<[[VP6:%[0-9]+]]> = DERIVED-IV ir<%n> + vp<[[VP5]]> * ir<-1>
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; CHECK-NEXT: vp<[[VP7:%[0-9]+]]> = SCALAR-STEPS vp<[[VP6]]>, ir<-1>, vp<[[VP0]]>
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; CHECK-NEXT: CLONE ir<%iv.next> = add nsw vp<[[VP7]]>, ir<-1>
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; CHECK-NEXT: CLONE ir<%gep.src> = getelementptr ir<%src>, ir<%iv.next>
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; CHECK-NEXT: vp<[[VP8:%[0-9]+]]> = vector-end-pointer ir<%gep.src>, vp<[[VP0]]>
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; CHECK-NEXT: WIDEN ir<%x> = load vp<[[VP8]]>
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; CHECK-NEXT: EMIT vp<[[VP9:%[0-9]+]]> = reverse ir<%x>
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; CHECK-NEXT: CLONE ir<%gep.dst> = getelementptr ir<%dst>, ir<%iv.next>
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; CHECK-NEXT: vp<[[VP10:%[0-9]+]]> = vector-end-pointer ir<%gep.dst>, vp<[[VP0]]>
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; CHECK-NEXT: EMIT vp<[[VP11:%[0-9]+]]> = reverse vp<[[VP9]]>
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; CHECK-NEXT: WIDEN store vp<[[VP10]]>, ir<%x>
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; CHECK-NEXT: EMIT vp<%index.next> = add nuw vp<[[VP5]]>, vp<[[VP1]]>
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; CHECK-NEXT: EMIT branch-on-count vp<%index.next>, vp<[[VP2]]>
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; CHECK-NEXT: No successors
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; CHECK-NEXT: }
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; CHECK-NEXT: Successor(s): middle.block
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; CHECK-EMPTY:
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; CHECK-NEXT: middle.block:
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;
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entry:
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br label %loop
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loop:
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%iv = phi i32 [%n, %entry], [%iv.next, %loop]
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%iv.next = add nsw i32 %iv, -1
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%gep.src = getelementptr i32, ptr %src, i32 %iv.next
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%x = load i32, ptr %gep.src
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%gep.dst = getelementptr i32, ptr %dst, i32 %iv.next
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store i32 %x, ptr %gep.dst
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%ec = icmp sgt i32 %iv.next, 0
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br i1 %ec, label %loop, label %exit
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exit:
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ret void
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}
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@ -45,6 +45,7 @@
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; CHECK: VPlan for loop in 'foo' after reassociateHeaderMask
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; CHECK: VPlan for loop in 'foo' after simplifyRecipes
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; CHECK: VPlan for loop in 'foo' after removeBranchOnConst
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; CHECK: VPlan for loop in 'foo' after simplifyReverses
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; CHECK: VPlan for loop in 'foo' after removeDeadRecipes
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; CHECK: VPlan for loop in 'foo' after createAndOptimizeReplicateRegions
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; CHECK: VPlan for loop in 'foo' after mergeBlocksIntoPredecessors
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@ -39,10 +39,8 @@ define void @test_runtime_check_known_false_after_construction(ptr %start.1, ptr
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; CHECK-NEXT: [[NEXT_GEP3:%.*]] = getelementptr i8, ptr [[START_2_DIFF]], i64 [[OFFSET_IDX]]
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; CHECK-NEXT: [[TMP14:%.*]] = getelementptr i64, ptr [[NEXT_GEP3]], i64 -3
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; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i64>, ptr [[TMP14]], align 8
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; CHECK-NEXT: [[REVERSE:%.*]] = shufflevector <4 x i64> [[WIDE_LOAD]], <4 x i64> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
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; CHECK-NEXT: [[TMP16:%.*]] = getelementptr i64, ptr [[NEXT_GEP]], i64 -3
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; CHECK-NEXT: [[REVERSE4:%.*]] = shufflevector <4 x i64> [[REVERSE]], <4 x i64> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
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; CHECK-NEXT: store <4 x i64> [[REVERSE4]], ptr [[TMP16]], align 8
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; CHECK-NEXT: store <4 x i64> [[WIDE_LOAD]], ptr [[TMP16]], align 8
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; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
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; CHECK-NEXT: [[TMP17:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
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; CHECK-NEXT: br i1 [[TMP17]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
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@ -51,11 +49,11 @@ define void @test_runtime_check_known_false_after_construction(ptr %start.1, ptr
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; CHECK-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]
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; CHECK: [[SCALAR_PH]]:
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; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi ptr [ [[TMP10]], %[[MIDDLE_BLOCK]] ], [ [[START_1]], %[[ENTRY]] ], [ [[START_1]], %[[VECTOR_SCEVCHECK]] ]
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; CHECK-NEXT: [[BC_RESUME_VAL4:%.*]] = phi ptr [ [[TMP11]], %[[MIDDLE_BLOCK]] ], [ [[START_2_DIFF]], %[[ENTRY]] ], [ [[START_2_DIFF]], %[[VECTOR_SCEVCHECK]] ]
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; CHECK-NEXT: [[BC_RESUME_VAL3:%.*]] = phi ptr [ [[TMP11]], %[[MIDDLE_BLOCK]] ], [ [[START_2_DIFF]], %[[ENTRY]] ], [ [[START_2_DIFF]], %[[VECTOR_SCEVCHECK]] ]
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; CHECK-NEXT: br label %[[LOOP:.*]]
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; CHECK: [[LOOP]]:
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; CHECK-NEXT: [[PTR_IV_1:%.*]] = phi ptr [ [[PTR_IV_1_NEXT:%.*]], %[[LOOP]] ], [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ]
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; CHECK-NEXT: [[PTR_IV_2:%.*]] = phi ptr [ [[PTR_IV_2_NEXT:%.*]], %[[LOOP]] ], [ [[BC_RESUME_VAL4]], %[[SCALAR_PH]] ]
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; CHECK-NEXT: [[PTR_IV_2:%.*]] = phi ptr [ [[PTR_IV_2_NEXT:%.*]], %[[LOOP]] ], [ [[BC_RESUME_VAL3]], %[[SCALAR_PH]] ]
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; CHECK-NEXT: [[PTR_IV_2_NEXT]] = getelementptr i8, ptr [[PTR_IV_2]], i64 -8
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; CHECK-NEXT: [[PTR_IV_1_NEXT]] = getelementptr i8, ptr [[PTR_IV_1]], i64 -8
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; CHECK-NEXT: [[L:%.*]] = load i64, ptr [[PTR_IV_2]], align 8
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