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Revert "[NFC][LiveStacks] Use vectors instead of map and unordred_map" (#180421)

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Reverts llvm/llvm-project#165477

Break https://lab.llvm.org/buildbot/#/builders/52/builds/14874
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Qinkun Bao 2026-02-08 11:54:51 -05:00 committed by GitHub
parent 3c5b05427d
commit 1b0f139f8e
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GPG key ID: B5690EEEBB952194
5 changed files with 64 additions and 52 deletions
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44
llvm/include/llvm/CodeGen/LiveStacks.h
View file

@ -40,43 +40,49 @@ class LiveStacks {
///
VNInfo::Allocator VNInfoAllocator;
int StartIdx = -1;
SmallVector<LiveInterval *> S2LI;
SmallVector<const TargetRegisterClass *> S2RC;
/// S2IMap - Stack slot indices to live interval mapping.
using SS2IntervalMap = std::unordered_map<int, LiveInterval>;
SS2IntervalMap S2IMap;
/// S2RCMap - Stack slot indices to register class mapping.
std::map<int, const TargetRegisterClass *> S2RCMap;
public:
using iterator = SmallVector<LiveInterval *>::iterator;
using const_iterator = SmallVector<LiveInterval *>::const_iterator;
using iterator = SS2IntervalMap::iterator;
using const_iterator = SS2IntervalMap::const_iterator;
const_iterator begin() const { return S2LI.begin(); }
const_iterator end() const { return S2LI.end(); }
iterator begin() { return S2LI.begin(); }
iterator end() { return S2LI.end(); }
const_iterator begin() const { return S2IMap.begin(); }
const_iterator end() const { return S2IMap.end(); }
iterator begin() { return S2IMap.begin(); }
iterator end() { return S2IMap.end(); }
unsigned getStartIdx() const { return StartIdx; }
unsigned getNumIntervals() const { return (unsigned)S2LI.size(); }
unsigned getNumIntervals() const { return (unsigned)S2IMap.size(); }
LiveInterval &getOrCreateInterval(int Slot, const TargetRegisterClass *RC);
LiveInterval &getInterval(int Slot) {
assert(Slot >= 0 && "Spill slot indice must be >= 0");
return *S2LI[Slot - StartIdx];
SS2IntervalMap::iterator I = S2IMap.find(Slot);
assert(I != S2IMap.end() && "Interval does not exist for stack slot");
return I->second;
}
const LiveInterval &getInterval(int Slot) const {
assert(Slot >= 0 && "Spill slot indice must be >= 0");
return *S2LI[Slot - StartIdx];
SS2IntervalMap::const_iterator I = S2IMap.find(Slot);
assert(I != S2IMap.end() && "Interval does not exist for stack slot");
return I->second;
}
bool hasInterval(int Slot) const {
if (Slot < StartIdx || StartIdx == -1)
return false;
return !getInterval(Slot).empty();
}
bool hasInterval(int Slot) const { return S2IMap.count(Slot); }
const TargetRegisterClass *getIntervalRegClass(int Slot) const {
assert(Slot >= 0 && "Spill slot indice must be >= 0");
return S2RC[Slot - StartIdx];
std::map<int, const TargetRegisterClass *>::const_iterator I =
S2RCMap.find(Slot);
assert(I != S2RCMap.end() &&
"Register class info does not exist for stack slot");
return I->second;
}
VNInfo::Allocator &getVNInfoAllocator() { return VNInfoAllocator; }

41
llvm/lib/CodeGen/LiveStacks.cpp
View file

@ -37,12 +37,10 @@ void LiveStacksWrapperLegacy::getAnalysisUsage(AnalysisUsage &AU) const {
}
void LiveStacks::releaseMemory() {
for (int Idx = 0; Idx < (int)S2LI.size(); ++Idx)
S2LI[Idx]->~LiveInterval();
// Release VNInfo memory regions, VNInfo objects don't need to be dtor'd.
VNInfoAllocator.Reset();
S2LI.clear();
S2RC.clear();
S2IMap.clear();
S2RCMap.clear();
}
void LiveStacks::init(MachineFunction &MF) {
@ -54,22 +52,20 @@ void LiveStacks::init(MachineFunction &MF) {
LiveInterval &
LiveStacks::getOrCreateInterval(int Slot, const TargetRegisterClass *RC) {
assert(Slot >= 0 && "Spill slot indice must be >= 0");
if (StartIdx == -1)
StartIdx = Slot;
int Idx = Slot - StartIdx;
assert(Idx >= 0 && "Slot not in order ?");
if (Idx < (int)S2LI.size()) {
S2RC[Idx] = TRI->getCommonSubClass(S2RC[Idx], RC);
SS2IntervalMap::iterator I = S2IMap.find(Slot);
if (I == S2IMap.end()) {
I = S2IMap
.emplace(
std::piecewise_construct, std::forward_as_tuple(Slot),
std::forward_as_tuple(Register::index2StackSlot(Slot), 0.0F))
.first;
S2RCMap.insert(std::make_pair(Slot, RC));
} else {
S2RC.resize(Idx + 1);
S2LI.resize(Idx + 1);
S2LI[Idx] = this->VNInfoAllocator.Allocate<LiveInterval>();
new (S2LI[Idx]) LiveInterval(Register::index2StackSlot(Slot), 0.0F);
S2RC[Idx] = RC;
// Use the largest common subclass register class.
const TargetRegisterClass *&OldRC = S2RCMap[Slot];
OldRC = TRI->getCommonSubClass(OldRC, RC);
}
assert(S2RC.size() == S2LI.size());
return *S2LI[Idx];
return I->second;
}
AnalysisKey LiveStacksAnalysis::Key;
@ -100,12 +96,13 @@ void LiveStacksWrapperLegacy::print(raw_ostream &OS, const Module *) const {
}
/// print - Implement the dump method.
void LiveStacks::print(raw_ostream &OS, const Module *) const {
void LiveStacks::print(raw_ostream &OS, const Module*) const {
OS << "********** INTERVALS **********\n";
for (int Idx = 0; Idx < (int)S2LI.size(); ++Idx) {
S2LI[Idx]->print(OS);
const TargetRegisterClass *RC = S2RC[Idx];
for (const_iterator I = begin(), E = end(); I != E; ++I) {
I->second.print(OS);
int Slot = I->first;
const TargetRegisterClass *RC = getIntervalRegClass(Slot);
if (RC)
OS << " [" << TRI->getRegClassName(RC) << "]\n";
else

20
llvm/lib/CodeGen/StackSlotColoring.cpp
View file

@ -260,14 +260,24 @@ void StackSlotColoring::InitializeSlots() {
UsedColors[0].resize(LastFI);
Assignments.resize(LastFI);
using Pair = std::iterator_traits<LiveStacks::iterator>::value_type;
SmallVector<Pair *, 16> Intervals;
Intervals.reserve(LS->getNumIntervals());
for (auto &I : *LS)
Intervals.push_back(&I);
llvm::sort(Intervals,
[](Pair *LHS, Pair *RHS) { return LHS->first < RHS->first; });
// Gather all spill slots into a list.
LLVM_DEBUG(dbgs() << "Spill slot intervals:\n");
for (auto [Idx, I] : llvm::enumerate(*LS)) {
int FI = Idx + LS->getStartIdx();
if (!I || MFI->isDeadObjectIndex(FI))
continue;
LiveInterval &li = *I;
for (auto *I : Intervals) {
LiveInterval &li = I->second;
LLVM_DEBUG(li.dump());
int FI = li.reg().stackSlotIndex();
if (MFI->isDeadObjectIndex(FI))
continue;
SSIntervals.push_back(&li);
OrigAlignments[FI] = MFI->getObjectAlign(FI);

6
llvm/lib/Target/AMDGPU/AMDGPUMarkLastScratchLoad.cpp
View file

@ -102,15 +102,15 @@ bool AMDGPUMarkLastScratchLoad::run(MachineFunction &MF) {
bool Changed = false;
for (auto *LI : *LS) {
for (const LiveRange::Segment &Segment : LI->segments) {
for (auto &[SS, LI] : *LS) {
for (const LiveRange::Segment &Segment : LI.segments) {
// Ignore segments that run to the end of basic block because in this case
// slot is still live at the end of it.
if (Segment.end.isBlock())
continue;
const int FrameIndex = LI->reg().stackSlotIndex();
const int FrameIndex = LI.reg().stackSlotIndex();
MachineInstr *LastLoad = nullptr;
MachineInstr *MISegmentEnd = SI->getInstructionFromIndex(Segment.end);

5
llvm/lib/Target/AMDGPU/AMDGPURewriteAGPRCopyMFMA.cpp
View file

@ -480,14 +480,13 @@ void AMDGPURewriteAGPRCopyMFMAImpl::eliminateSpillsOfReassignedVGPRs() const {
SmallVector<LiveInterval *, 32> StackIntervals;
StackIntervals.reserve(NumSlots);
for (auto [Idx, LI] : llvm::enumerate(LSS)) {
int Slot = Idx + LSS.getStartIdx();
for (auto &[Slot, LI] : LSS) {
if (!MFI.isSpillSlotObjectIndex(Slot) || MFI.isDeadObjectIndex(Slot))
continue;
const TargetRegisterClass *RC = LSS.getIntervalRegClass(Slot);
if (TRI.hasVGPRs(RC))
StackIntervals.push_back(LI);
StackIntervals.push_back(&LI);
}
sort(StackIntervals, [](const LiveInterval *A, const LiveInterval *B) {