[NFC][Driver][HIP] Fix mixing amdgcnspirv and gfxXXX via --offload-arch (#133024)
Due to `amdgcnspirv` piggybacking on the HIPAMDToolchain, it loses its immediately apparent SPIR-Vness, which makes the Driver want to go all the way to Assembly emmission. This was problematic as we were trying to `llvm-link` SPIR-V, before trying to translate it. This patch ensures that we do the right thing and stop at bitcode emission if we are mixing `amdgcnspirv` and concrete targets.
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2 changed files with 7 additions and 4 deletions
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@ -3750,9 +3750,12 @@ class OffloadingActionBuilder final {
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// compiler phases, including backend and assemble phases.
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ActionList AL;
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Action *BackendAction = nullptr;
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if (ToolChains.front()->getTriple().isSPIRV()) {
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if (ToolChains.front()->getTriple().isSPIRV() ||
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(ToolChains.front()->getTriple().isAMDGCN() &&
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GpuArchList[I] == StringRef("amdgcnspirv"))) {
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// Emit LLVM bitcode for SPIR-V targets. SPIR-V device tool chain
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// (HIPSPVToolChain) runs post-link LLVM IR passes.
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// (HIPSPVToolChain or HIPAMDToolChain) runs post-link LLVM IR
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// passes.
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types::ID Output = Args.hasArg(options::OPT_S)
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? types::TY_LLVM_IR
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: types::TY_LLVM_BC;
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@ -187,8 +187,8 @@
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// Check mixed AMDGCNSPIRV and concrete GPU arch.
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//
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// AMDGCNSPIRV: "-cc1" "-triple" "spirv64-amd-amdhsa" {{.*}}"-emit-obj" {{.*}} "-o" "[[AMDGCNSPV_OBJ:.*o]]"
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// AMDGCNSPIRV: {{".*llvm-link.*"}} "-o" "[[AMDGCNSPV_TMP:.*out]]" "[[AMDGCNSPV_OBJ]]"
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// AMDGCNSPIRV: "-cc1" "-triple" "spirv64-amd-amdhsa" {{.*}}"-emit-llvm-bc" {{.*}} "-o" "[[AMDGCNSPV_BC:.*bc]]"
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// AMDGCNSPIRV: {{".*llvm-link.*"}} "-o" "[[AMDGCNSPV_TMP:.*out]]" "[[AMDGCNSPV_BC]]"
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// AMDGCNSPIRV: {{".*llvm-spirv.*"}} "--spirv-max-version=1.6" "--spirv-ext=+all" {{.*}} "[[AMDGCNSPV_TMP]]" {{.*}}"-o" "[[AMDGCNSPV_CO:.*out]]"
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// AMDGCNSPIRV: "-cc1" "-triple" "amdgcn-amd-amdhsa" {{.*}}"-emit-obj" {{.*}}"-target-cpu" "gfx900"{{.*}} "-o" "[[GFX900_OBJ:.*o]]"
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// AMDGCNSPIRV: {{".*lld.*"}} {{.*}}"-plugin-opt=mcpu=gfx900" {{.*}} "-o" "[[GFX900_CO:.*out]]" {{.*}}"[[GFX900_OBJ]]"
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