[WebAssembly] Support acquire-release atomics in CodeGen (#184900)
Set the correct memory ordering for relaxed atomics after ISel. This allows SelectionDAG to keep the simple generic selection for target-independent AtomicLoad nodes, but keeps the ordering immediate correct in the MIR. Notably, the MachineMemOperand still has the original memory ordering and MIR passes would use that rather than the ordering immedate to make their code motion decisions (if we had any for Wasm, which we don't).
This commit is contained in:
Derek Schuff
GitHub
parent
6b1ad6bbfd
commit
18d85a33cc
5 changed files with 1133 additions and 139 deletions
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@ -16,6 +16,7 @@
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#include "WebAssemblyISelLowering.h"
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#include "WebAssemblyTargetMachine.h"
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#include "WebAssemblyUtilities.h"
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#include "llvm/BinaryFormat/Wasm.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/SelectionDAGISel.h"
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#include "llvm/CodeGen/WasmEHFuncInfo.h"
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@ -69,6 +70,12 @@ public:
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bool SelectAddrOperands32(SDValue Op, SDValue &Offset, SDValue &Addr);
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bool SelectAddrOperands64(SDValue Op, SDValue &Offset, SDValue &Addr);
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bool SelectAtomicAddrOperands(SDNode *Op, SDValue N, SDValue &Offset,
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SDValue &Addr, SDValue &Order, bool Is64);
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bool SelectAtomicAddrOperands32(SDNode *Op, SDValue N, SDValue &Offset,
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SDValue &Addr, SDValue &Order);
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bool SelectAtomicAddrOperands64(SDNode *Op, SDValue N, SDValue &Offset,
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SDValue &Addr, SDValue &Order);
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// Include the pieces autogenerated from the target description.
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#include "WebAssemblyGenDAGISel.inc"
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@ -174,6 +181,25 @@ static APInt encodeFunctionSignature(SelectionDAG *DAG, SDLoc &DL,
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return Sig;
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}
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static unsigned getWebAssemblyMemoryOrder(AtomicOrdering Ordering) {
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unsigned OrderVal = wasm::WASM_MEM_ORDER_SEQ_CST;
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switch (Ordering) {
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case AtomicOrdering::Unordered:
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case AtomicOrdering::Monotonic:
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case AtomicOrdering::Acquire:
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case AtomicOrdering::Release:
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case AtomicOrdering::AcquireRelease:
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OrderVal = wasm::WASM_MEM_ORDER_ACQ_REL;
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break;
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case AtomicOrdering::SequentiallyConsistent:
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OrderVal = wasm::WASM_MEM_ORDER_SEQ_CST;
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break;
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default:
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llvm_unreachable("Invalid atomic ordering");
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}
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return OrderVal;
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}
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void WebAssemblyDAGToDAGISel::Select(SDNode *Node) {
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// If we have a custom node, we already have selected!
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if (Node->isMachineOpcode()) {
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@ -186,7 +212,6 @@ void WebAssemblyDAGToDAGISel::Select(SDNode *Node) {
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auto GlobalGetIns = PtrVT == MVT::i64 ? WebAssembly::GLOBAL_GET_I64
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: WebAssembly::GLOBAL_GET_I32;
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// Few custom selection stuff.
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SDLoc DL(Node);
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MachineFunction &MF = CurDAG->getMachineFunction();
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switch (Node->getOpcode()) {
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@ -207,17 +232,22 @@ void WebAssemblyDAGToDAGISel::Select(SDNode *Node) {
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Node->getOperand(0) // inchain
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);
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break;
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case SyncScope::System:
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// Currently wasm only supports sequentially consistent atomics, so we
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// always set the order to 0 (sequentially consistent).
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case SyncScope::System: {
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unsigned Order = wasm::WASM_MEM_ORDER_SEQ_CST;
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if (MF.getSubtarget<WebAssemblySubtarget>().hasRelaxedAtomics()) {
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auto Ordering =
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static_cast<AtomicOrdering>(Node->getConstantOperandVal(1));
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Order = getWebAssemblyMemoryOrder(Ordering);
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}
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Fence = CurDAG->getMachineNode(
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WebAssembly::ATOMIC_FENCE,
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DL, // debug loc
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MVT::Other, // outchain type
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CurDAG->getTargetConstant(0, DL, MVT::i32), // order
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Node->getOperand(0) // inchain
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DL, // debug loc
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MVT::Other, // outchain type
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CurDAG->getTargetConstant(Order, DL, MVT::i32), // order
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Node->getOperand(0) // inchain
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);
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break;
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}
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default:
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llvm_unreachable("Unknown scope!");
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}
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@ -548,6 +578,65 @@ bool WebAssemblyDAGToDAGISel::SelectAddrOperands64(SDValue Op, SDValue &Offset,
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return SelectAddrOperands(MVT::i64, WebAssembly::CONST_I64, Op, Offset, Addr);
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}
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static MemSDNode *findMemSDNode(SDNode *N) {
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while (N) {
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if (auto *MemNode = dyn_cast<MemSDNode>(N))
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return MemNode;
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switch (N->getOpcode()) {
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case ISD::ZERO_EXTEND:
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case ISD::SIGN_EXTEND:
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case ISD::ANY_EXTEND:
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case ISD::SIGN_EXTEND_INREG:
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case ISD::AssertZext:
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case ISD::AssertSext:
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case ISD::TRUNCATE:
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case ISD::BITCAST:
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case ISD::AND:
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N = N->getOperand(0).getNode();
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break;
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default:
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return nullptr;
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}
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}
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return nullptr;
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}
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bool WebAssemblyDAGToDAGISel::SelectAtomicAddrOperands(SDNode *Op, SDValue N,
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SDValue &Offset,
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SDValue &Addr,
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SDValue &Order,
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bool Is64) {
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auto *MemNode = findMemSDNode(Op);
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if (!MemNode)
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return false;
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bool Match = Is64 ? SelectAddrOperands64(N, Offset, Addr)
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: SelectAddrOperands32(N, Offset, Addr);
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if (!Match)
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return false;
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auto Ordering = MemNode->getMergedOrdering();
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unsigned OrderVal = wasm::WASM_MEM_ORDER_SEQ_CST;
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if (Subtarget->hasRelaxedAtomics())
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OrderVal = getWebAssemblyMemoryOrder(Ordering);
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Order = CurDAG->getTargetConstant(OrderVal, SDLoc(Op), MVT::i32);
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return true;
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}
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bool WebAssemblyDAGToDAGISel::SelectAtomicAddrOperands32(SDNode *Op, SDValue N,
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SDValue &Offset,
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SDValue &Addr,
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SDValue &Order) {
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return SelectAtomicAddrOperands(Op, N, Offset, Addr, Order, /*Is64=*/false);
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}
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bool WebAssemblyDAGToDAGISel::SelectAtomicAddrOperands64(SDNode *Op, SDValue N,
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SDValue &Offset,
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SDValue &Addr,
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SDValue &Order) {
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return SelectAtomicAddrOperands(Op, N, Offset, Addr, Order, /*Is64=*/true);
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}
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/// This pass converts a legalized DAG into a WebAssembly-specific DAG, ready
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/// for instruction scheduling.
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FunctionPass *llvm::createWebAssemblyISelDag(WebAssemblyTargetMachine &TM,
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@ -11,6 +11,13 @@
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///
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//===----------------------------------------------------------------------===//
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def AtomicAddrOps32 : ComplexPattern<i32, 3, "SelectAtomicAddrOperands32"> {
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let WantsRoot = 1;
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}
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def AtomicAddrOps64 : ComplexPattern<i64, 3, "SelectAtomicAddrOperands64"> {
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let WantsRoot = 1;
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}
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let UseNamedOperandTable = 1 in
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multiclass ATOMIC_I<dag oops_r, dag iops_r, dag oops_s, dag iops_s,
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list<dag> pattern_r, string asmstr_r,
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@ -150,11 +157,11 @@ multiclass AtomicLoad<WebAssemblyRegClass rc, string name, int atomic_op> {
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}
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multiclass AtomicLoadPat<ValueType ty, SDPatternOperator kind, string Name> {
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def : Pat<(ty (kind (AddrOps32 offset32_op:$offset, I32:$addr))),
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(!cast<NI>(Name # "_A32") 0, 0, offset32_op:$offset, I32:$addr)>,
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def : Pat<(ty (kind (AtomicAddrOps32 offset32_op:$offset, I32:$addr, i32imm:$order))),
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(!cast<NI>(Name # "_A32") $order, 0, offset32_op:$offset, I32:$addr)>,
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Requires<[HasAddr32, HasAtomics]>;
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def : Pat<(ty (kind (AddrOps64 offset64_op:$offset, I64:$addr))),
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(!cast<NI>(Name # "_A64") 0, 0, offset64_op:$offset, I64:$addr)>,
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def : Pat<(ty (kind (AtomicAddrOps64 offset64_op:$offset, I64:$addr, i32imm:$order))),
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(!cast<NI>(Name # "_A64") $order, 0, offset64_op:$offset, I64:$addr)>,
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Requires<[HasAddr64, HasAtomics]>;
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}
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@ -245,18 +252,12 @@ multiclass AtomicStore<WebAssemblyRegClass rc, string name, int atomic_op> {
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defm ATOMIC_STORE_I32 : AtomicStore<I32, "i32.atomic.store", 0x17>;
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defm ATOMIC_STORE_I64 : AtomicStore<I64, "i64.atomic.store", 0x18>;
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// We used to need an 'atomic' version of store patterns because store and atomic_store
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// nodes have different operand orders.
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//
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// TODO: This is no longer true and atomic_store and store patterns
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// can be unified.
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multiclass AStorePat<ValueType ty, PatFrag kind, string inst> {
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def : Pat<(kind ty:$val, (AddrOps32 offset32_op:$offset, I32:$addr)),
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(!cast<NI>(inst#_A32) 0, 0, $offset, $addr, $val)>,
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def : Pat<(kind ty:$val, (AtomicAddrOps32 offset32_op:$offset, I32:$addr, i32imm:$order)),
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(!cast<NI>(inst#_A32) $order, 0, $offset, $addr, $val)>,
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Requires<[HasAddr32, HasAtomics]>;
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def : Pat<(kind ty:$val, (AddrOps64 offset64_op:$offset, I64:$addr)),
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(!cast<NI>(inst#_A64) 0, 0, $offset, $addr, $val)>,
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def : Pat<(kind ty:$val, (AtomicAddrOps64 offset64_op:$offset, I64:$addr, i32imm:$order)),
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(!cast<NI>(inst#_A64) $order, 0, $offset, $addr, $val)>,
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Requires<[HasAddr64, HasAtomics]>;
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}
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defm : AStorePat<i32, atomic_store_32, "ATOMIC_STORE_I32">;
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@ -393,11 +394,13 @@ defm ATOMIC_RMW32_U_XCHG_I64 :
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WebAssemblyBinRMW<I64, "i64.atomic.rmw32.xchg_u", 0x47>;
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multiclass BinRMWPat<ValueType ty, PatFrag kind, string inst> {
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def : Pat<(ty (kind (AddrOps32 offset32_op:$offset, I32:$addr), ty:$val)),
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(!cast<NI>(inst#_A32) 0, 0, $offset, $addr, $val)>,
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def : Pat<(ty (kind (AtomicAddrOps32 offset32_op:$offset, I32:$addr,
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i32imm:$order), ty:$val)),
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(!cast<NI>(inst#_A32) $order, 0, $offset, $addr, $val)>,
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Requires<[HasAddr32, HasAtomics]>;
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def : Pat<(ty (kind (AddrOps64 offset64_op:$offset, I64:$addr), ty:$val)),
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(!cast<NI>(inst#_A64) 0, 0, $offset, $addr, $val)>,
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def : Pat<(ty (kind (AtomicAddrOps64 offset64_op:$offset, I64:$addr,
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i32imm:$order), ty:$val)),
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(!cast<NI>(inst#_A64) $order, 0, $offset, $addr, $val)>,
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Requires<[HasAddr64, HasAtomics]>;
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}
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@ -536,11 +539,11 @@ defm ATOMIC_RMW32_U_CMPXCHG_I64 :
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WebAssemblyTerRMW<I64, "i64.atomic.rmw32.cmpxchg_u", 0x4e>;
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multiclass TerRMWPat<ValueType ty, PatFrag kind, string inst> {
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def : Pat<(ty (kind (AddrOps32 offset32_op:$offset, I32:$addr), ty:$exp, ty:$new)),
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(!cast<NI>(inst#_A32) 0, 0, $offset, $addr, $exp, $new)>,
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def : Pat<(ty (kind (AtomicAddrOps32 offset32_op:$offset, I32:$addr, i32imm:$order), ty:$exp, ty:$new)),
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(!cast<NI>(inst#_A32) $order, 0, $offset, $addr, $exp, $new)>,
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Requires<[HasAddr32, HasAtomics]>;
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def : Pat<(ty (kind (AddrOps64 offset64_op:$offset, I64:$addr), ty:$exp, ty:$new)),
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(!cast<NI>(inst#_A64) 0, 0, $offset, $addr, $exp, $new)>,
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def : Pat<(ty (kind (AtomicAddrOps64 offset64_op:$offset, I64:$addr, i32imm:$order), ty:$exp, ty:$new)),
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(!cast<NI>(inst#_A64) $order, 0, $offset, $addr, $exp, $new)>,
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Requires<[HasAddr64, HasAtomics]>;
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}
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@ -1,36 +1,140 @@
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; RUN: llc < %s | FileCheck %s --check-prefix NOATOMIC
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; RUN: llc < %s -asm-verbose=false -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+atomics | FileCheck %s
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target triple = "wasm32-unknown-unknown"
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
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; RUN: llc < %s --mtriple=wasm32 | FileCheck %s --check-prefixes=NO-ATOMICS
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; RUN: llc < %s --mtriple=wasm32 -mattr=+atomics | FileCheck %s --check-prefixes=ATOMICS
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; RUN: llc < %s --mtriple=wasm32 -mattr=+atomics,+relaxed-atomics | FileCheck %s --check-prefixes=RELAXED32
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; RUN: llc < %s --mtriple=wasm64 -mattr=+atomics,+relaxed-atomics | FileCheck %s --check-prefixes=RELAXED64
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; A multithread fence is lowered to an atomic.fence instruction.
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; CHECK-LABEL: multithread_fence:
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; CHECK: atomic.fence
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; NOATOMIC-NOT: i32.atomic.rmw.or
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define void @multithread_fence() {
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fence seq_cst
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define void @fence_acquire() {
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; NO-ATOMICS-LABEL: fence_acquire:
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; NO-ATOMICS: .functype fence_acquire () -> ()
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; NO-ATOMICS-NEXT: # %bb.0:
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; NO-ATOMICS-NEXT: # fallthrough-return
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;
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; ATOMICS-LABEL: fence_acquire:
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; ATOMICS: .functype fence_acquire () -> ()
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; ATOMICS-NEXT: # %bb.0:
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; ATOMICS-NEXT: atomic.fence
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; ATOMICS-NEXT: # fallthrough-return
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;
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; RELAXED32-LABEL: fence_acquire:
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; RELAXED32: .functype fence_acquire () -> ()
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; RELAXED32-NEXT: # %bb.0:
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; RELAXED32-NEXT: atomic.fence acqrel
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; RELAXED32-NEXT: # fallthrough-return
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;
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; RELAXED64-LABEL: fence_acquire:
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; RELAXED64: .functype fence_acquire () -> ()
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; RELAXED64-NEXT: # %bb.0:
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; RELAXED64-NEXT: atomic.fence acqrel
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; RELAXED64-NEXT: # fallthrough-return
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fence acquire
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ret void
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}
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; Fences with weaker memory orderings than seq_cst should be treated the same
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; because atomic memory access in wasm are sequentially consistent.
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; CHECK-LABEL: multithread_weak_fence:
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; CHECK: atomic.fence
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; CHECK-NEXT: atomic.fence
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; CHECK-NEXT: atomic.fence
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define void @multithread_weak_fence() {
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fence acquire
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define void @fence_release() {
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; NO-ATOMICS-LABEL: fence_release:
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; NO-ATOMICS: .functype fence_release () -> ()
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; NO-ATOMICS-NEXT: # %bb.0:
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; NO-ATOMICS-NEXT: # fallthrough-return
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;
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; ATOMICS-LABEL: fence_release:
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; ATOMICS: .functype fence_release () -> ()
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; ATOMICS-NEXT: # %bb.0:
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; ATOMICS-NEXT: atomic.fence
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; ATOMICS-NEXT: # fallthrough-return
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;
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; RELAXED32-LABEL: fence_release:
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; RELAXED32: .functype fence_release () -> ()
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; RELAXED32-NEXT: # %bb.0:
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; RELAXED32-NEXT: atomic.fence acqrel
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; RELAXED32-NEXT: # fallthrough-return
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;
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; RELAXED64-LABEL: fence_release:
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; RELAXED64: .functype fence_release () -> ()
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; RELAXED64-NEXT: # %bb.0:
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; RELAXED64-NEXT: atomic.fence acqrel
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; RELAXED64-NEXT: # fallthrough-return
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fence release
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ret void
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}
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define void @fence_acq_rel() {
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; NO-ATOMICS-LABEL: fence_acq_rel:
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; NO-ATOMICS: .functype fence_acq_rel () -> ()
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; NO-ATOMICS-NEXT: # %bb.0:
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; NO-ATOMICS-NEXT: # fallthrough-return
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;
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; ATOMICS-LABEL: fence_acq_rel:
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; ATOMICS: .functype fence_acq_rel () -> ()
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; ATOMICS-NEXT: # %bb.0:
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; ATOMICS-NEXT: atomic.fence
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; ATOMICS-NEXT: # fallthrough-return
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;
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; RELAXED32-LABEL: fence_acq_rel:
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; RELAXED32: .functype fence_acq_rel () -> ()
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; RELAXED32-NEXT: # %bb.0:
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; RELAXED32-NEXT: atomic.fence acqrel
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; RELAXED32-NEXT: # fallthrough-return
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;
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; RELAXED64-LABEL: fence_acq_rel:
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; RELAXED64: .functype fence_acq_rel () -> ()
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; RELAXED64-NEXT: # %bb.0:
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; RELAXED64-NEXT: atomic.fence acqrel
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; RELAXED64-NEXT: # fallthrough-return
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fence acq_rel
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ret void
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}
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define void @fence_seq_cst() {
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; NO-ATOMICS-LABEL: fence_seq_cst:
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; NO-ATOMICS: .functype fence_seq_cst () -> ()
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; NO-ATOMICS-NEXT: # %bb.0:
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; NO-ATOMICS-NEXT: # fallthrough-return
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;
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; ATOMICS-LABEL: fence_seq_cst:
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; ATOMICS: .functype fence_seq_cst () -> ()
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; ATOMICS-NEXT: # %bb.0:
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; ATOMICS-NEXT: atomic.fence
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; ATOMICS-NEXT: # fallthrough-return
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;
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; RELAXED32-LABEL: fence_seq_cst:
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; RELAXED32: .functype fence_seq_cst () -> ()
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; RELAXED32-NEXT: # %bb.0:
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; RELAXED32-NEXT: atomic.fence seqcst
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; RELAXED32-NEXT: # fallthrough-return
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;
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; RELAXED64-LABEL: fence_seq_cst:
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; RELAXED64: .functype fence_seq_cst () -> ()
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; RELAXED64-NEXT: # %bb.0:
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; RELAXED64-NEXT: atomic.fence seqcst
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||||
; RELAXED64-NEXT: # fallthrough-return
|
||||
fence seq_cst
|
||||
ret void
|
||||
}
|
||||
|
||||
; A singlethread fence becomes compiler_fence instruction, a pseudo instruction
|
||||
; that acts as a compiler barrier. The barrier should not be emitted to .s file.
|
||||
; CHECK-LABEL: singlethread_fence:
|
||||
; CHECK-NOT: compiler_fence
|
||||
; CHECK-NOT: atomic_fence
|
||||
define void @singlethread_fence() {
|
||||
; NO-ATOMICS-LABEL: singlethread_fence:
|
||||
; NO-ATOMICS: .functype singlethread_fence () -> ()
|
||||
; NO-ATOMICS-NEXT: # %bb.0:
|
||||
; NO-ATOMICS-NEXT: # fallthrough-return
|
||||
;
|
||||
; ATOMICS-LABEL: singlethread_fence:
|
||||
; ATOMICS: .functype singlethread_fence () -> ()
|
||||
; ATOMICS-NEXT: # %bb.0:
|
||||
; ATOMICS-NEXT: # fallthrough-return
|
||||
;
|
||||
; RELAXED32-LABEL: singlethread_fence:
|
||||
; RELAXED32: .functype singlethread_fence () -> ()
|
||||
; RELAXED32-NEXT: # %bb.0:
|
||||
; RELAXED32-NEXT: # fallthrough-return
|
||||
;
|
||||
; RELAXED64-LABEL: singlethread_fence:
|
||||
; RELAXED64: .functype singlethread_fence () -> ()
|
||||
; RELAXED64-NEXT: # %bb.0:
|
||||
; RELAXED64-NEXT: # fallthrough-return
|
||||
fence syncscope("singlethread") seq_cst
|
||||
fence syncscope("singlethread") acquire
|
||||
fence syncscope("singlethread") release
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -41,6 +41,26 @@ define i32 @load_i32_with_folded_gep_offset(ptr %p) {
|
|||
ret i32 %t
|
||||
}
|
||||
|
||||
; Same for nusw.
|
||||
|
||||
; CHECK-LABEL: load_i32_with_folded_gep_offset_nusw:
|
||||
; CHECK: i32.atomic.load $push0=, 24($0){{$}}
|
||||
define i32 @load_i32_with_folded_gep_offset_nusw(ptr %p) {
|
||||
%s = getelementptr nusw i32, ptr %p, i32 6
|
||||
%t = load atomic i32, ptr %s seq_cst, align 4
|
||||
ret i32 %t
|
||||
}
|
||||
|
||||
; For nuw we don't need the offset to be positive.
|
||||
|
||||
; CHECK-LABEL: load_i32_with_folded_gep_offset_nuw:
|
||||
; CHECK: i32.atomic.load $push0=, -24($0){{$}}
|
||||
define i32 @load_i32_with_folded_gep_offset_nuw(ptr %p) {
|
||||
%s = getelementptr nuw i32, ptr %p, i32 -6
|
||||
%t = load atomic i32, ptr %s seq_cst, align 4
|
||||
ret i32 %t
|
||||
}
|
||||
|
||||
; We can't fold a negative offset though, even with an inbounds gep.
|
||||
|
||||
; CHECK-LABEL: load_i32_with_unfolded_gep_negative_offset:
|
||||
|
|
@ -99,8 +119,19 @@ define i32 @load_i32_from_global_address() {
|
|||
ret i32 %t
|
||||
}
|
||||
|
||||
define i32 @load_i32_global_with_folded_gep_offset_nonconst_nuw(i32 %idx) {
|
||||
; CHECK-LABEL: load_i32_global_with_folded_gep_offset_nonconst_nuw:
|
||||
; CHECK: i32.const $push0=, 2
|
||||
; CHECK: i32.shl $push1=, $0, $pop0
|
||||
; CHECK: i32.atomic.load $push2=, gv($pop1)
|
||||
%s = getelementptr nuw i32, ptr @gv, i32 %idx
|
||||
%t = load atomic i32, ptr %s seq_cst, align 4
|
||||
ret i32 %t
|
||||
}
|
||||
|
||||
;===----------------------------------------------------------------------------
|
||||
; Atomic loads: 64-bit
|
||||
|
||||
;===----------------------------------------------------------------------------
|
||||
|
||||
; Basic load.
|
||||
|
|
|
|||
Loading…
Reference in a new issue