[Hexagon] Fix truncation to boolean vector that need widening (#182528)
When truncating a sub-HVX-width vector to a boolean vector (e.g., v64i8 -> v64i1 in 128-byte HVX mode), the operation would crash with "Unhandled HVX operation" UNREACHABLE. This happened because the condition in LowerHvxOperationWrapper/ReplaceHvxNodeResults did not handle the case where the input vector needs widening and the result is a boolean vector. The fix adds WidenHvxTruncateToBool which widens the input to HVX register width (e.g., v64i8 -> v128i8), performs the truncate to widened bool type (v128i8 -> v128i1), extracts the result subvector (v128i1 -> v64i1). This allows the widened truncate to match the existing V6_vandvrt pattern in HexagonPatternsHVX.td.
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Brian Cain
GitHub
parent
8d625621eb
commit
0c53a89b22
4 changed files with 205 additions and 15 deletions
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@ -501,6 +501,7 @@ private:
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SDValue CreateTLWrapper(SDValue Op, SelectionDAG &DAG) const;
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SDValue RemoveTLWrapper(SDValue Op, SelectionDAG &DAG) const;
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SDValue WidenHvxTruncateToBool(SDValue Op, SelectionDAG &DAG) const;
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std::pair<const TargetRegisterClass*, uint8_t>
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findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT)
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@ -3616,6 +3616,43 @@ HexagonTargetLowering::WidenHvxSetCC(SDValue Op, SelectionDAG &DAG) const {
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{SetCC, getZero(dl, MVT::i32, DAG)});
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}
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SDValue HexagonTargetLowering::WidenHvxTruncateToBool(SDValue Op,
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SelectionDAG &DAG) const {
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// Handle truncation to boolean vector where the result boolean type
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// needs widening (e.g., v16i32 -> v16i1 where v16i1 is not a standard
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// HVX predicate type, or v16i8 -> v16i1 in 128-byte mode).
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// Widen the input to HVX width, perform the truncate to the widened
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// boolean type, then extract the result.
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const SDLoc &dl(Op);
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SDValue Inp = Op.getOperand(0);
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MVT InpTy = ty(Inp);
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MVT ResTy = ty(Op);
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assert(ResTy.getVectorElementType() == MVT::i1 &&
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"Expected boolean result type");
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MVT ElemTy = InpTy.getVectorElementType();
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unsigned HwLen = Subtarget.getVectorLength();
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// Calculate the widened input type that fills the HVX register.
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unsigned WideLen = (8 * HwLen) / ElemTy.getSizeInBits();
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MVT WideInpTy = MVT::getVectorVT(ElemTy, WideLen);
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if (!Subtarget.isHVXVectorType(WideInpTy, false))
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return SDValue();
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// Widen the input to HVX width.
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SDValue WideInp = appendUndef(Inp, WideInpTy, DAG);
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// Perform the truncate to widened boolean type.
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MVT WideBoolTy = MVT::getVectorVT(MVT::i1, WideLen);
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SDValue WideTrunc = DAG.getNode(ISD::TRUNCATE, dl, WideBoolTy, WideInp);
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// Extract the result.
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EVT RetTy = typeLegalize(ResTy, DAG);
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return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, RetTy,
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{WideTrunc, getZero(dl, MVT::i32, DAG)});
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}
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SDValue
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HexagonTargetLowering::LowerHvxOperation(SDValue Op, SelectionDAG &DAG) const {
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unsigned Opc = Op.getOpcode();
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@ -3866,12 +3903,28 @@ HexagonTargetLowering::LowerHvxOperationWrapper(SDNode *N,
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case ISD::ANY_EXTEND:
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case ISD::SIGN_EXTEND:
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case ISD::ZERO_EXTEND:
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case ISD::TRUNCATE:
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if (Subtarget.isHVXElementType(ty(Op)) &&
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Subtarget.isHVXElementType(ty(Inp0))) {
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Results.push_back(CreateTLWrapper(Op, DAG));
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}
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break;
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case ISD::TRUNCATE:
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// Handle truncate to boolean vector when the input is not a
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// standard HVX vector type (single or pair). This covers cases
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// where the input needs widening (e.g., v64i8 -> v64i1 in
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// 128-byte mode) and cases where the result boolean type itself
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// needs widening (e.g., v16i32 -> v16i1). When the input is
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// already an HVX type, tablegen patterns handle the truncation
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// directly (e.g., v64i16 -> v64i1 via V6_vandvrt).
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if (ty(Op).getVectorElementType() == MVT::i1 &&
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!Subtarget.isHVXVectorType(ty(Inp0), false)) {
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if (SDValue T = WidenHvxTruncateToBool(Op, DAG))
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Results.push_back(T);
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} else if (Subtarget.isHVXElementType(ty(Op)) &&
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Subtarget.isHVXElementType(ty(Inp0))) {
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Results.push_back(CreateTLWrapper(Op, DAG));
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}
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break;
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case ISD::SETCC:
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if (shouldWidenToHvx(ty(Inp0), DAG)) {
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if (SDValue T = WidenHvxSetCC(Op, DAG))
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@ -3932,12 +3985,23 @@ HexagonTargetLowering::ReplaceHvxNodeResults(SDNode *N,
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case ISD::ANY_EXTEND:
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case ISD::SIGN_EXTEND:
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case ISD::ZERO_EXTEND:
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case ISD::TRUNCATE:
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if (Subtarget.isHVXElementType(ty(Op)) &&
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Subtarget.isHVXElementType(ty(Inp0))) {
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Results.push_back(CreateTLWrapper(Op, DAG));
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}
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break;
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case ISD::TRUNCATE:
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// Handle truncate to boolean vector when the input is not a
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// standard HVX vector type. See comment in LowerHvxOperationWrapper.
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if (ty(Op).getVectorElementType() == MVT::i1 &&
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!Subtarget.isHVXVectorType(ty(Inp0), false)) {
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if (SDValue T = WidenHvxTruncateToBool(Op, DAG))
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Results.push_back(T);
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} else if (Subtarget.isHVXElementType(ty(Op)) &&
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Subtarget.isHVXElementType(ty(Inp0))) {
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Results.push_back(CreateTLWrapper(Op, DAG));
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}
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break;
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case ISD::SETCC:
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if (shouldWidenToHvx(ty(Op), DAG)) {
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if (SDValue T = WidenHvxSetCC(Op, DAG))
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@ -742,6 +742,9 @@ let Predicates = [UseHVX] in {
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(V6_vandvrt HvxVR:$Vs, (ToI32 0x01010101))>;
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def: Pat<(VecQ32 (trunc HVI32:$Vs)),
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(V6_vandvrt HvxVR:$Vs, (ToI32 0x01010101))>;
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def: Pat<(VecQ8 (trunc HWI16:$Vss)),
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(Combineq(VecQ16(V6_vandvrt (HiVec $Vss), (ToI32 0x01010101))),
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(VecQ16 (V6_vandvrt (LoVec $Vss), (ToI32 0x01010101))))>;
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def: Pat<(VecQ16 (trunc HWI32:$Vss)),
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(Combineq(VecQ32(V6_vandvrt (HiVec $Vss), (ToI32 0x01010101))),
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(VecQ32 (V6_vandvrt (LoVec $Vss), (ToI32 0x01010101))))>;
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@ -1,18 +1,140 @@
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; RUN: llc --mtriple=hexagon -mattr=+hvxv79,+hvx-length128b < %s | FileCheck %s
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define void @f5(<64 x i32> %a0, ptr %a1) {
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; CHECK-LABEL: f5:
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; CHECK: [[REG0:(r[0-9]+)]] = ##16843009
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; CHECK-DAG: q[[Q0:[0-9]+]] = vand(v{{[0-9]+}},[[REG0]])
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; CHECK-DAG: q[[Q1:[0-9]+]] = vand(v{{[0-9]+}},[[REG0]])
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; CHECK: v{{[0-9]+}}.b = vpacke(v{{[0-9]+}}.h,v{{[0-9]+}}.h)
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; CHECK: v{{[0-9]+}}.b = vpacke(v{{[0-9]+}}.h,v{{[0-9]+}}.h)
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; CHECK: v[[VROR:[0-9]+]] = vror(v{{[0-9]+}},r{{[0-9]+}})
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; CHECK: v[[VOR:[0-9]+]] = vor(v[[VROR]],v{{[0-9]+}})
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; CHECK: q{{[0-9]+}} = vand(v[[VOR]],r{{[0-9]+}})
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b0:
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%v0 = trunc <64 x i32> %a0 to <64 x i1>
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store <64 x i1> %v0, ptr %a1, align 1
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;
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; Exhaustive tests for truncation of HVX vectors to boolean (i1) vectors.
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; In 128-byte HVX mode:
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; Single register (HvxVR): v128i8, v64i16, v32i32 (1024 bits)
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; Pair register (HvxWR): v256i8, v128i16, v64i32 (2048 bits)
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; Predicates (HvxQR): v128i1, v64i1, v32i1
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;
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; Tests cover:
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; - Full HVX width (single register): tablegen V6_vandvrt patterns
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; - HVX pairs: tablegen Combineq patterns
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; - Sub-HVX width: C++ WidenHvxTruncateToBool (widen + trunc + extract)
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;
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; Very small vectors (v8i16, v8i32) are scalarized by the legalizer
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; and do not exercise HVX paths, so they are not included here.
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;
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; ===========================================================================
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; Category 1: Full HVX single-register width -> HVX predicate (tablegen)
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; These match tablegen patterns VecQ{8,16,32} (trunc HVI{8,16,32})
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; directly via V6_vandvrt.
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; ===========================================================================
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; CHECK-LABEL: trunc_v128i8_to_v128i1:
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; CHECK: q{{[0-9]+}} = vand(v{{[0-9]+}},r{{[0-9]+}})
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define void @trunc_v128i8_to_v128i1(<128 x i8> %v, ptr %p) {
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%1 = trunc <128 x i8> %v to <128 x i1>
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store <128 x i1> %1, ptr %p, align 16
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ret void
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}
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; CHECK-LABEL: trunc_v64i16_to_v64i1:
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; CHECK: q{{[0-9]+}} = vand(v{{[0-9]+}},r{{[0-9]+}})
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define i64 @trunc_v64i16_to_v64i1(<64 x i16> %v) {
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%1 = trunc <64 x i16> %v to <64 x i1>
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%2 = bitcast <64 x i1> %1 to i64
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ret i64 %2
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}
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; CHECK-LABEL: trunc_v32i32_to_v32i1:
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; CHECK: q{{[0-9]+}} = vand(v{{[0-9]+}},r{{[0-9]+}})
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define i32 @trunc_v32i32_to_v32i1(<32 x i32> %v) {
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%1 = trunc <32 x i32> %v to <32 x i1>
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%2 = bitcast <32 x i1> %1 to i32
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ret i32 %2
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}
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; ===========================================================================
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; Category 2: HVX pair -> HVX predicate (tablegen, via Combineq)
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; These split the pair, apply V6_vandvrt to each half, and combine
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; the predicate halves.
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; ===========================================================================
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; CHECK-LABEL: trunc_v64i32_to_v64i1:
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; CHECK-DAG: q{{[0-9]+}} = vand(v{{[0-9]+}},r{{[0-9]+}})
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; CHECK-DAG: q{{[0-9]+}} = vand(v{{[0-9]+}},r{{[0-9]+}})
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define void @trunc_v64i32_to_v64i1(<64 x i32> %v, ptr %p) {
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%1 = trunc <64 x i32> %v to <64 x i1>
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store <64 x i1> %1, ptr %p, align 8
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ret void
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}
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; CHECK-LABEL: trunc_v128i16_to_v128i1:
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; CHECK-DAG: q{{[0-9]+}} = vand(v{{[0-9]+}},r{{[0-9]+}})
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; CHECK-DAG: q{{[0-9]+}} = vand(v{{[0-9]+}},r{{[0-9]+}})
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define void @trunc_v128i16_to_v128i1(<128 x i16> %v, ptr %p) {
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%1 = trunc <128 x i16> %v to <128 x i1>
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store <128 x i1> %1, ptr %p, align 16
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ret void
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}
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; ===========================================================================
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; Category 3: Sub-HVX width -> predicate (C++ WidenHvxTruncateToBool)
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; Input is narrower than a single HVX register. The input is widened
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; to full HVX width, truncated to widened bool, then the result
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; subvector is extracted.
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; ===========================================================================
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; --- Half HVX width (512-bit input) ---
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; CHECK-LABEL: trunc_v64i8_to_v64i1:
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; CHECK: q{{[0-9]+}} = vand(v{{[0-9]+}},r{{[0-9]+}})
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define i64 @trunc_v64i8_to_v64i1(<64 x i8> %v) {
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%1 = trunc <64 x i8> %v to <64 x i1>
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%2 = bitcast <64 x i1> %1 to i64
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ret i64 %2
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}
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; CHECK-LABEL: trunc_v32i16_to_v32i1:
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; CHECK: q{{[0-9]+}} = vand(v{{[0-9]+}},r{{[0-9]+}})
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define i32 @trunc_v32i16_to_v32i1(<32 x i16> %v) {
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%1 = trunc <32 x i16> %v to <32 x i1>
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%2 = bitcast <32 x i1> %1 to i32
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ret i32 %2
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}
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; CHECK-LABEL: trunc_v16i32_to_v16i1:
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; CHECK: q{{[0-9]+}} = vand(v{{[0-9]+}},r{{[0-9]+}})
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define i16 @trunc_v16i32_to_v16i1(<16 x i32> %v) {
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%1 = trunc <16 x i32> %v to <16 x i1>
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%2 = bitcast <16 x i1> %1 to i16
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ret i16 %2
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}
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; --- Quarter HVX width (256-bit input) ---
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; CHECK-LABEL: trunc_v32i8_to_v32i1:
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; CHECK: q{{[0-9]+}} = vand(v{{[0-9]+}},r{{[0-9]+}})
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define i32 @trunc_v32i8_to_v32i1(<32 x i8> %v) {
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%1 = trunc <32 x i8> %v to <32 x i1>
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%2 = bitcast <32 x i1> %1 to i32
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ret i32 %2
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}
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; CHECK-LABEL: trunc_v16i16_to_v16i1:
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; CHECK: q{{[0-9]+}} = vand(v{{[0-9]+}},r{{[0-9]+}})
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define i16 @trunc_v16i16_to_v16i1(<16 x i16> %v) {
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%1 = trunc <16 x i16> %v to <16 x i1>
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%2 = bitcast <16 x i1> %1 to i16
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ret i16 %2
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}
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; --- Eighth HVX width and smaller (128-bit input) ---
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; CHECK-LABEL: trunc_v16i8_to_v16i1:
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; CHECK: q{{[0-9]+}} = vand(v{{[0-9]+}},r{{[0-9]+}})
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define i16 @trunc_v16i8_to_v16i1(<16 x i8> %v) {
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%1 = trunc <16 x i8> %v to <16 x i1>
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%2 = bitcast <16 x i1> %1 to i16
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ret i16 %2
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}
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; CHECK-LABEL: trunc_v4i32_to_v4i1:
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; CHECK: q{{[0-9]+}} = vand(v{{[0-9]+}},r{{[0-9]+}})
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define i4 @trunc_v4i32_to_v4i1(<4 x i32> %v) {
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%1 = trunc <4 x i32> %v to <4 x i1>
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%2 = bitcast <4 x i1> %1 to i4
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ret i4 %2
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}
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